Jason c871281f1e Fix synthesis blockers in 9 RTL files for Vivado compatibility ...

Guard all $display/$error/$time calls with ifdef SIMULATION in:
- chirp_memory_loader_param.v (initial + always block debug prints)
- cic_decimator_4x_enhanced.v (5 saturation/overflow displays + monitor block)
- ddc_400m.v (FIR/baseband debug monitor block)
- fft_1024_inverse.v (IFFT config debug block)
- matched_filter_multi_segment.v (16 state machine displays + monitor)
- nco_400m_enhanced.v (initial block debug print)
- radar_receiver_final.v (frame/chirp counter displays)

Replace SystemVerilog constructs with Verilog-2001:
- usb_data_interface.v (typedef enum -> localparam + reg)
- usb_packet_analyzer.v (typedef enum -> localparam, output reg -> wire)

2026-03-15 14:53:35 +02:00

..

tb

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

ad9484_interface_400m.v

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2026-03-09 00:17:39 +00:00

cdc_modules.v

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2026-03-09 00:17:39 +00:00

chirp_lut_init.v

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2026-03-09 00:17:39 +00:00

chirp_memory_loader_param.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

cic_decimator_4x_enhanced.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

cntrt.xdc

Create cntrt.xdc

2026-03-10 02:42:15 +00:00

dac_interface_single.v

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2026-03-09 00:17:39 +00:00

ddc_400m.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

ddc_input_interface.v

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2026-03-09 00:17:39 +00:00

doppler_processor.v

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2026-03-09 00:17:39 +00:00

edge_detector.v

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2026-03-09 00:17:39 +00:00

fft_1024_forward.v

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2026-03-09 00:17:39 +00:00

fft_1024_inverse.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

fir_lowpass.v

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2026-03-09 00:17:39 +00:00

frequency_matched_filter.v

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2026-03-09 00:17:39 +00:00

latency_buffer_2159.v

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2026-03-09 00:17:39 +00:00

level_shifter_interface.v

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2026-03-10 01:31:50 +00:00

long_chirp_seg0_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg0_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg2_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg2_q.mem

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2026-03-09 00:17:39 +00:00

lvds_to_cmos_400m.v

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2026-03-09 00:17:39 +00:00

matched_filter_multi_segment.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

matched_filter_processing_chain.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

nco_400m_enhanced.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

plfm_chirp_controller.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_mode_controller.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

radar_receiver_final.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

radar_system_tb.v

Create radar_system_tb.v

2026-03-10 01:35:26 +00:00

radar_system_top.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_transmitter.v

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2026-03-09 00:17:39 +00:00

range_bin_decimator.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

short_chirp_i.mem

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2026-03-09 00:17:39 +00:00

short_chirp_q.mem

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2026-03-09 00:17:39 +00:00

usb_data_interface.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

usb_packet_analyzer.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00