Jason
c983a3c705
Phase 0+ timing optimization (attempts #13-22 + implementation): NCO (nco_400m_enhanced.v): - 4-stage pipeline: DSP48E1 accumulate -> LUT read -> negate -> quadrant MUX - DSP48E1 phase accumulator in P=P+C mode (eliminates 8-stage CARRY4 chain) - Registered phase_inc_dithered to break cascaded 32-bit add path DDC (ddc_400m.v): - Direct DSP48E1 instantiation for I/Q mixers (AREG=1, BREG=1, MREG=1, PREG=1) - CEP=1, RSTP=!reset_n for proper pipeline control - 3-stage dsp_valid_pipe for PREG=1 latency - Behavioral sim model under ifdef SIMULATION for Icarus compatibility CIC (cic_decimator_4x_enhanced.v): - 28-bit accumulators (was 36) per CIC width formula: 18 + 5*log2(4) = 28 - Removed integrator/comb saturation (CIC uses wrapping arithmetic by design) - Pipelined output saturation comparison CDC/ASYNC_REG: - ASYNC_REG attribute on all CDC synchronizer registers (cdc_modules.v, radar_system_top.v, usb_data_interface.v) - Sync reset in generate blocks (cdc_modules.v) Results: Vivado post-implementation WNS=+1.196ns, 0 failing endpoints, 850 LUTs (1.34%), 466 FFs (0.37%), 2 DSP48E1 (0.83%) on xc7a100t. All testbenches pass: 241/244 (3 known stub failures).
488 lines
16 KiB
Verilog
488 lines
16 KiB
Verilog
`timescale 1ns / 1ps
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/**
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* radar_system_top.v
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*
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* Complete Radar System Top Module
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* Integrates:
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* - Radar Transmitter (PLFM chirp generation)
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* - Radar Receiver (ADC interface, DDC, matched filtering, Doppler processing)
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* - USB Data Interface (FT601 for high-speed data transfer)
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*
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* Clock domains:
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* - clk_100m: System clock (100MHz)
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* - clk_120m_dac: DAC clock (120MHz)
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* - ft601_clk: FT601 interface clock (100MHz from FT601)
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*/
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module radar_system_top (
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// System Clocks
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input wire clk_100m, // 100MHz system clock
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input wire clk_120m_dac, // 120MHz DAC clock
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input wire ft601_clk_in, // FT601 clock (100MHz)
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input wire reset_n, // Active-low reset
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// ========== TRANSMITTER INTERFACES ==========
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// DAC Interface
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output wire [7:0] dac_data,
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output wire dac_clk,
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output wire dac_sleep,
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// RF Switch Control
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output wire fpga_rf_switch,
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// Mixer Enables
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output wire rx_mixer_en,
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output wire tx_mixer_en,
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// ADAR1000 Beamformer Control (via level shifters)
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output wire adar_tx_load_1, adar_rx_load_1,
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output wire adar_tx_load_2, adar_rx_load_2,
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output wire adar_tx_load_3, adar_rx_load_3,
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output wire adar_tx_load_4, adar_rx_load_4,
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output wire adar_tr_1, adar_tr_2, adar_tr_3, adar_tr_4,
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// Level Shifter SPI Interface (STM32F7 to ADAR1000)
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input wire stm32_sclk_3v3,
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input wire stm32_mosi_3v3,
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output wire stm32_miso_3v3,
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input wire stm32_cs_adar1_3v3, stm32_cs_adar2_3v3,
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input wire stm32_cs_adar3_3v3, stm32_cs_adar4_3v3,
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output wire stm32_sclk_1v8,
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output wire stm32_mosi_1v8,
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input wire stm32_miso_1v8,
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output wire stm32_cs_adar1_1v8, stm32_cs_adar2_1v8,
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output wire stm32_cs_adar3_1v8, stm32_cs_adar4_1v8,
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// ========== RECEIVER INTERFACES ==========
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// ADC Physical Interface (LVDS)
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input wire [7:0] adc_d_p, // ADC Data P (LVDS)
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input wire [7:0] adc_d_n, // ADC Data N (LVDS)
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input wire adc_dco_p, // Data Clock Output P (400MHz LVDS)
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input wire adc_dco_n, // Data Clock Output N (400MHz LVDS)
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output wire adc_pwdn, // ADC Power Down
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// ========== STM32 CONTROL INTERFACES ==========
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// Chirp/Beam Control (toggle signals from STM32)
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input wire stm32_new_chirp,
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input wire stm32_new_elevation,
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input wire stm32_new_azimuth,
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input wire stm32_mixers_enable,
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// ========== FT601 USB 3.0 INTERFACE ==========
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// Data bus
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inout wire [31:0] ft601_data, // 32-bit bidirectional data bus
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output wire [1:0] ft601_be, // Byte enable
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// Control signals
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output wire ft601_txe_n, // Transmit enable (active low)
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output wire ft601_rxf_n, // Receive enable (active low)
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input wire ft601_txe, // Transmit FIFO empty
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input wire ft601_rxf, // Receive FIFO full
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output wire ft601_wr_n, // Write strobe (active low)
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output wire ft601_rd_n, // Read strobe (active low)
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output wire ft601_oe_n, // Output enable (active low)
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output wire ft601_siwu_n, // Send immediate / Wakeup
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// FIFO flags
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input wire [1:0] ft601_srb, // Selected read buffer
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input wire [1:0] ft601_swb, // Selected write buffer
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// Clock output (optional)
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output wire ft601_clk_out,
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// ========== STATUS OUTPUTS ==========
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// Beam position tracking
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output wire [5:0] current_elevation,
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output wire [5:0] current_azimuth,
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output wire [5:0] current_chirp,
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output wire new_chirp_frame,
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// Doppler processing outputs (for debugging)
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output wire [31:0] dbg_doppler_data,
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output wire dbg_doppler_valid,
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output wire [4:0] dbg_doppler_bin,
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output wire [5:0] dbg_range_bin,
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// System status
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output wire [3:0] system_status
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);
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// ============================================================================
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// PARAMETERS
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// ============================================================================
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// System configuration
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parameter USE_LONG_CHIRP = 1'b1; // Default to long chirp
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parameter DOPPLER_ENABLE = 1'b1; // Enable Doppler processing
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parameter USB_ENABLE = 1'b1; // Enable USB data transfer
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// ============================================================================
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// INTERNAL SIGNALS
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// ============================================================================
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// Clock and reset
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wire clk_100m_buf;
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wire clk_120m_dac_buf;
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wire ft601_clk_buf;
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wire sys_reset_n;
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wire sys_reset_120m_n; // Reset synchronized to clk_120m_dac domain
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// Transmitter internal signals
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wire [7:0] tx_chirp_data;
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wire tx_chirp_valid;
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wire tx_chirp_done;
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wire tx_new_chirp_frame; // In clk_120m_dac domain
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wire tx_new_chirp_frame_sync; // Synchronized to clk_100m domain
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wire [5:0] tx_current_elevation;
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wire [5:0] tx_current_azimuth;
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wire [5:0] tx_current_chirp; // In clk_120m_dac domain
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wire [5:0] tx_current_chirp_sync; // Synchronized to clk_100m domain
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wire tx_current_chirp_sync_valid;
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// Receiver internal signals
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wire [31:0] rx_doppler_output;
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wire rx_doppler_valid;
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wire [4:0] rx_doppler_bin;
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wire [5:0] rx_range_bin;
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wire [31:0] rx_range_profile;
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wire rx_range_valid;
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wire [15:0] rx_doppler_real;
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wire [15:0] rx_doppler_imag;
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wire rx_doppler_data_valid;
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reg rx_cfar_detection;
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reg rx_cfar_valid;
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// Data packing for USB
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wire [31:0] usb_range_profile;
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wire usb_range_valid;
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wire [15:0] usb_doppler_real;
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wire [15:0] usb_doppler_imag;
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wire usb_doppler_valid;
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wire usb_cfar_detection;
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wire usb_cfar_valid;
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// System status
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reg [3:0] status_reg;
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// ============================================================================
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// CLOCK BUFFERING
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// ============================================================================
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BUFG bufg_100m (
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.I(clk_100m),
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.O(clk_100m_buf)
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);
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BUFG bufg_120m (
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.I(clk_120m_dac),
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.O(clk_120m_dac_buf)
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);
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BUFG bufg_ft601 (
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.I(ft601_clk_in),
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.O(ft601_clk_buf)
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);
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// Reset synchronization (clk_100m domain)
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(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync;
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always @(posedge clk_100m_buf or negedge reset_n) begin
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if (!reset_n) begin
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reset_sync <= 2'b00;
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end else begin
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reset_sync <= {reset_sync[0], 1'b1};
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end
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end
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assign sys_reset_n = reset_sync[1];
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// Reset synchronization (clk_120m_dac domain)
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// Ensures reset deassertion is synchronous to the DAC clock,
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// preventing recovery/removal timing violations on 120 MHz FFs.
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(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_120m;
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always @(posedge clk_120m_dac_buf or negedge reset_n) begin
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if (!reset_n) begin
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reset_sync_120m <= 2'b00;
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end else begin
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reset_sync_120m <= {reset_sync_120m[0], 1'b1};
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end
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end
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assign sys_reset_120m_n = reset_sync_120m[1];
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// ============================================================================
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// CLOCK DOMAIN CROSSING: TRANSMITTER (120 MHz) -> SYSTEM (100 MHz)
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// ============================================================================
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// CDC for chirp_counter: 6-bit multi-bit Gray-code synchronizer
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cdc_adc_to_processing #(
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.WIDTH(6),
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.STAGES(3)
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) cdc_chirp_counter (
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.src_clk(clk_120m_dac_buf),
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.dst_clk(clk_100m_buf),
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.reset_n(sys_reset_n),
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.src_data(tx_current_chirp),
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.src_valid(1'b1), // Always valid — counter updates continuously
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.dst_data(tx_current_chirp_sync),
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.dst_valid(tx_current_chirp_sync_valid)
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);
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// CDC for new_chirp_frame: single-bit 3-stage synchronizer
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cdc_single_bit #(
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.STAGES(3)
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) cdc_new_chirp_frame (
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.src_clk(clk_120m_dac_buf),
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.dst_clk(clk_100m_buf),
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.reset_n(sys_reset_n),
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.src_signal(tx_new_chirp_frame),
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.dst_signal(tx_new_chirp_frame_sync)
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);
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// ============================================================================
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// RADAR TRANSMITTER INSTANTIATION
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// ============================================================================
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radar_transmitter tx_inst (
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// System Clocks
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.clk_100m(clk_100m_buf),
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.clk_120m_dac(clk_120m_dac_buf),
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.reset_n(sys_reset_120m_n), // Use 120 MHz-synchronized reset
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// DAC Interface
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.dac_data(dac_data),
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.dac_clk(dac_clk),
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.dac_sleep(dac_sleep),
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// Mixer Enables
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.rx_mixer_en(rx_mixer_en),
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.tx_mixer_en(tx_mixer_en),
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// STM32 Control Interface
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.stm32_new_chirp(stm32_new_chirp),
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.stm32_new_elevation(stm32_new_elevation),
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.stm32_new_azimuth(stm32_new_azimuth),
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.stm32_mixers_enable(stm32_mixers_enable),
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// RF Switch Control
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.fpga_rf_switch(fpga_rf_switch),
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// ADAR1000 Control Interface
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.adar_tx_load_1(adar_tx_load_1),
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.adar_rx_load_1(adar_rx_load_1),
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.adar_tx_load_2(adar_tx_load_2),
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.adar_rx_load_2(adar_rx_load_2),
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.adar_tx_load_3(adar_tx_load_3),
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.adar_rx_load_3(adar_rx_load_3),
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.adar_tx_load_4(adar_tx_load_4),
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.adar_rx_load_4(adar_rx_load_4),
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.adar_tr_1(adar_tr_1),
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.adar_tr_2(adar_tr_2),
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.adar_tr_3(adar_tr_3),
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.adar_tr_4(adar_tr_4),
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// Level Shifter SPI Interface
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.stm32_sclk_3v3(stm32_sclk_3v3),
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.stm32_mosi_3v3(stm32_mosi_3v3),
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.stm32_miso_3v3(stm32_miso_3v3),
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.stm32_cs_adar1_3v3(stm32_cs_adar1_3v3),
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.stm32_cs_adar2_3v3(stm32_cs_adar2_3v3),
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.stm32_cs_adar3_3v3(stm32_cs_adar3_3v3),
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.stm32_cs_adar4_3v3(stm32_cs_adar4_3v3),
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.stm32_sclk_1v8(stm32_sclk_1v8),
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.stm32_mosi_1v8(stm32_mosi_1v8),
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.stm32_miso_1v8(stm32_miso_1v8),
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.stm32_cs_adar1_1v8(stm32_cs_adar1_1v8),
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.stm32_cs_adar2_1v8(stm32_cs_adar2_1v8),
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.stm32_cs_adar3_1v8(stm32_cs_adar3_1v8),
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.stm32_cs_adar4_1v8(stm32_cs_adar4_1v8),
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// Beam Position Tracking
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.current_elevation(tx_current_elevation),
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.current_azimuth(tx_current_azimuth),
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.current_chirp(tx_current_chirp),
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.new_chirp_frame(tx_new_chirp_frame)
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);
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// ============================================================================
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// RADAR RECEIVER INSTANTIATION
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// ============================================================================
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radar_receiver_final rx_inst (
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.clk(clk_100m_buf),
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.reset_n(sys_reset_n),
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// Chirp counter from transmitter (CDC-synchronized from 120 MHz domain)
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.chirp_counter(tx_current_chirp_sync),
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// ADC Physical Interface
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.adc_d_p(adc_d_p),
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.adc_d_n(adc_d_n),
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.adc_dco_p(adc_dco_p),
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.adc_dco_n(adc_dco_n),
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.adc_pwdn(adc_pwdn),
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// Doppler Outputs
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.doppler_output(rx_doppler_output),
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.doppler_valid(rx_doppler_valid),
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.doppler_bin(rx_doppler_bin),
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.range_bin(rx_range_bin)
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);
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// ============================================================================
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// DOPPLER DATA DECODING
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// ============================================================================
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// Decode 32-bit doppler output into real and imaginary parts
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// Format: {doppler_q[15:0], doppler_i[15:0]}
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assign rx_doppler_real = rx_doppler_output[15:0];
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assign rx_doppler_imag = rx_doppler_output[31:16];
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assign rx_doppler_data_valid = rx_doppler_valid;
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// For this implementation, we'll create a simple CFAR detection simulation
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// In a real system, this would come from a CFAR module
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reg [7:0] cfar_counter;
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reg [16:0] cfar_mag; // Approximate magnitude for threshold detection
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always @(posedge clk_100m_buf or negedge sys_reset_n) begin
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if (!sys_reset_n) begin
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cfar_counter <= 8'd0;
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rx_cfar_detection <= 1'b0;
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rx_cfar_valid <= 1'b0;
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cfar_mag <= 17'd0;
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end else begin
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rx_cfar_valid <= 1'b0;
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// Simple threshold detection on doppler magnitude
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if (rx_doppler_valid) begin
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// Calculate approximate magnitude (|I| + |Q|)
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cfar_mag = (rx_doppler_real[15] ? -rx_doppler_real : rx_doppler_real) +
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(rx_doppler_imag[15] ? -rx_doppler_imag : rx_doppler_imag);
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// Threshold detection
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if (cfar_mag > 17'd10000) begin
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rx_cfar_detection <= 1'b1;
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rx_cfar_valid <= 1'b1;
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cfar_counter <= cfar_counter + 1;
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end
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end
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end
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end
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// ============================================================================
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// DATA PACKING FOR USB
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// ============================================================================
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// For range profile, we'll use the doppler data as a placeholder
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// In a real system, this would come from the matched filter output
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assign usb_range_profile = rx_doppler_output;
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assign usb_range_valid = rx_doppler_valid;
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assign usb_doppler_real = rx_doppler_real;
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assign usb_doppler_imag = rx_doppler_imag;
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assign usb_doppler_valid = rx_doppler_valid;
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assign usb_cfar_detection = rx_cfar_detection;
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assign usb_cfar_valid = rx_cfar_valid;
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// ============================================================================
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// USB DATA INTERFACE INSTANTIATION
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// ============================================================================
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usb_data_interface usb_inst (
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.clk(clk_100m_buf),
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.reset_n(sys_reset_n),
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// Radar data inputs
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.range_profile(usb_range_profile),
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.range_valid(usb_range_valid),
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.doppler_real(usb_doppler_real),
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.doppler_imag(usb_doppler_imag),
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.doppler_valid(usb_doppler_valid),
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.cfar_detection(usb_cfar_detection),
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.cfar_valid(usb_cfar_valid),
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// FT601 Interface
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.ft601_data(ft601_data),
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.ft601_be(ft601_be),
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.ft601_txe_n(ft601_txe_n),
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.ft601_rxf_n(ft601_rxf_n),
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.ft601_txe(ft601_txe),
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.ft601_rxf(ft601_rxf),
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.ft601_wr_n(ft601_wr_n),
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.ft601_rd_n(ft601_rd_n),
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.ft601_oe_n(ft601_oe_n),
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.ft601_siwu_n(ft601_siwu_n),
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.ft601_srb(ft601_srb),
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.ft601_swb(ft601_swb),
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.ft601_clk_out(ft601_clk_out),
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.ft601_clk_in(ft601_clk_buf)
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);
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// ============================================================================
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// OUTPUT ASSIGNMENTS
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// ============================================================================
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assign current_elevation = tx_current_elevation;
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assign current_azimuth = tx_current_azimuth;
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assign current_chirp = tx_current_chirp_sync; // Use CDC-synchronized version
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assign new_chirp_frame = tx_new_chirp_frame_sync; // Use CDC-synchronized version
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assign dbg_doppler_data = rx_doppler_output;
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assign dbg_doppler_valid = rx_doppler_valid;
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assign dbg_doppler_bin = rx_doppler_bin;
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assign dbg_range_bin = rx_range_bin;
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// ============================================================================
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// SYSTEM STATUS MONITORING
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// ============================================================================
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|
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always @(posedge clk_100m_buf or negedge sys_reset_n) begin
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if (!sys_reset_n) begin
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status_reg <= 4'b0000;
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end else begin
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status_reg[0] <= stm32_mixers_enable; // Mixers enabled
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status_reg[1] <= ft601_txe; // USB TX ready
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status_reg[2] <= rx_doppler_valid; // Data valid
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status_reg[3] <= tx_new_chirp_frame_sync; // New chirp frame (CDC-sync'd)
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end
|
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end
|
|
|
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assign system_status = status_reg;
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|
|
|
// ============================================================================
|
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// DEBUG AND VERIFICATION
|
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// ============================================================================
|
|
|
|
`ifdef SIMULATION
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// Simulation-only debug monitoring
|
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reg [31:0] debug_cycle_counter;
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|
reg [31:0] data_packet_counter;
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|
|
|
always @(posedge clk_100m_buf) begin
|
|
debug_cycle_counter <= debug_cycle_counter + 1;
|
|
|
|
if (tx_new_chirp_frame_sync) begin
|
|
$display("[TOP] New chirp frame started at cycle %0d", debug_cycle_counter);
|
|
end
|
|
|
|
if (rx_doppler_valid) begin
|
|
data_packet_counter <= data_packet_counter + 1;
|
|
if (data_packet_counter < 10) begin
|
|
$display("[TOP] Doppler data[%0d]: bin=%0d, range=%0d, I=%0d, Q=%0d",
|
|
data_packet_counter, rx_doppler_bin, rx_range_bin,
|
|
rx_doppler_real, rx_doppler_imag);
|
|
end
|
|
end
|
|
|
|
if (data_packet_counter == 100) begin
|
|
$display("[TOP] First 100 doppler packets processed");
|
|
end
|
|
end
|
|
`endif
|
|
|
|
endmodule |