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b588e89f67ef40950583e11654e799cfe1f3968f
PLFM_RADAR/9_Firmware/9_2_FPGA/tb
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Jason b588e89f67 test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing 
G9B adds a 4-iteration reset sweep on top of the existing e2e harness:
- Reset is injected at four offsets (3/7/12/18 us) into a steady-state
  auto-scan burst, with mixed short/long hold durations (20-120 clk_100m)
  to exercise asynchronous assert paths through the FSM + CDCs.
- Each iteration asserts: system_status drops to 0 during reset,
  new_chirp_frame resumes post-release, and obs_range_valid_count
  advances — proving the full DDC->MF chain recovers, not just the
  transmitter FSM.

The stub and three existing testbenches are updated to drive the new
adc_or_p/n ports tied to 1'b0/1'b1, matching the F-0.1 RTL change.
2026-04-20 15:48:34 +05:45
..
cosim
fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H
2026-04-18 20:34:52 +05:45
golden
fix(fpga): registered reset fan-out at 400 MHz; default USB to FT2232H
2026-04-18 20:34:52 +05:45
ad9484_interface_400m_stub.v
test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing
2026-04-20 15:48:34 +05:45
cic_dc_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
cic_impulse_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
cic_sine_passband.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
ddc_120mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
fir_dc_output.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
fir_impulse_output.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
fir_sine_passband.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
gen_mf_golden_ref.py
fix: enforce strict ruff lint (17 rule sets) across entire repo
2026-04-12 14:21:03 +05:45
mf_golden_out_i_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_i_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_i_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_i_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_q_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_q_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_q_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_out_q_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_i_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_i_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_i_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_i_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_q_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_q_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_q_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_ref_q_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_i_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_i_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_i_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_i_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_q_case1.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_q_case2.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_q_case3.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_sig_q_case4.hex
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_golden_summary.txt
Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)
2026-03-15 13:37:10 +02:00
mf_pipeline_output.csv
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
nco_1mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_120mhz_output.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_freq_switch.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
nco_quadrature.csv
Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG
2026-03-16 01:02:07 +02:00
radar_system_tb.v
test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing
2026-04-20 15:48:34 +05:45
tb_ad9484_xsim.v
Add new testbenches and fix USB clock forwarding test
2026-03-16 22:24:34 +02:00
tb_cdc_modules.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
tb_cfar_ca.v
Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)
2026-03-20 04:57:34 +02:00
tb_chirp_contract.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_chirp_controller.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
tb_cic_decimator.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_ddc_400m.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
tb_ddc_cosim.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
tb_ddc_input_interface.v
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
2026-03-16 18:14:06 +02:00
tb_doppler_cosim.v
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00
tb_doppler_realdata.v
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00
tb_edge_detector.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_fft_engine.v
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00
tb_fir_lowpass.v
FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache
2026-03-19 20:39:01 +02:00
tb_fpga_self_test.v
Add radar dashboard GUI with replay mode for real ADI CN0566 data visualization, FPGA self-test module, and co-sim npy arrays
2026-03-20 19:02:06 +02:00
tb_freq_matched_filter.v
Add 8 Verilog testbenches with full coverage (144/144 pass)
2026-03-15 06:14:11 +02:00
tb_fullchain_mti_cfar_realdata.v
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00
tb_fullchain_realdata.v
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00
tb_latency_buffer.v
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
2026-03-18 01:28:42 +02:00
tb_matched_filter_processing_chain.v
Fix matched filter golden test paths (40/40 pass, was 37/40)
2026-03-19 12:20:37 +02:00
tb_mf_chain_synth.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
tb_mf_cosim.v
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
tb_mti_canceller.v
Integrate MTI canceller and DC notch filter for ground clutter removal
2026-03-20 16:39:17 +02:00
tb_multiseg_cosim.v
Fix overlap-save: fill full 1024-sample buffer per segment, zero-pad last partial segment
2026-03-16 19:15:23 +02:00
tb_nco_400m.v
Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)
2026-03-16 15:02:35 +02:00
tb_nco_xsim.v
Fix NCO XSim test 12: widen zero-crossing range for DSP48E1 quantization
2026-03-16 23:23:06 +02:00
tb_radar_mode_controller.v
Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)
2026-03-19 23:54:48 +02:00
tb_radar_receiver_final.v
test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing
2026-04-20 15:48:34 +05:45
tb_range_bin_decimator.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
tb_range_fft_realdata.v
Real-data co-simulation: range FFT, Doppler, full-chain all 2048/2048 exact match
2026-03-20 03:19:22 +02:00
tb_rx_gain_control.v
fix: 9 bugs from code review — RTL sign-ext & snapshot, thread safety, protocol fixes
2026-04-13 23:35:10 +05:45
tb_system_e2e.v
test(fpga): F-2.2 adversarial mid-frame reset sweep + F-0.1 TB plumbing
2026-04-20 15:48:34 +05:45
tb_threshold_detector.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
tb_usb_data_interface.v
feat(fpga): make FT2232H default USB interface, rewrite FT601 write FSM, add clock-loss watchdog
2026-04-16 16:18:52 +05:45