NawfalMotii79
26 lines
768 B
Verilog
26 lines
768 B
Verilog
module edge_detector_enhanced (
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input wire clk,
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input wire reset_n,
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input wire signal_in,
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output wire rising_falling_edge
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);
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reg signal_in_prev;
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reg signal_in_prev2;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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signal_in_prev <= 1'b0;
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signal_in_prev2 <= 1'b0;
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end else begin
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signal_in_prev <= signal_in;
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signal_in_prev2 <= signal_in_prev;
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end
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end
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// Rising edge: was low, now high (with synchronization) signal_in_prev & ~signal_in_prev2;
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//Falling edge: was high, now low (with synchronization) falling_edge = ~signal_in_prev & signal_in_prev2
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assign rising_falling_edge = (signal_in_prev & ~signal_in_prev2)|(~signal_in_prev & signal_in_prev2);
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endmodule |