Jason b823d83feb Add new testbenches and fix USB clock forwarding test ...

New testbenches:
- tb_latency_buffer.v: 13/13 tests for BRAM delay line (P1-3)
- tb_cdc_modules.v: 27/27 tests for all 3 CDC primitives (P1-4)
- tb_ad9484_xsim.v: XSim testbench for AD9484 with Xilinx BUFIO/IDDR
- tb_nco_xsim.v: XSim testbench for NCO DSP48E1 path verification

Fixes:
- tb_usb_data_interface.v: updated test 33 from divide-by-2 check to
  ODDR-style clock forwarding verification (39/39 pass)
- rx_final_doppler_out.csv: updated golden reference after bug fixes

2026-03-16 22:24:34 +02:00

..

adc_dc.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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adc_multi_target.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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adc_noise_only.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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adc_sine_1mhz.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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adc_single_target.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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bb_mf_test_i.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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bb_mf_test_q.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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compare_dc.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

compare_doppler.py

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

compare_mf_chirp.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

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compare_mf_dc.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

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compare_mf_impulse.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

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compare_mf_tone5.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

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compare_mf.py

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

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compare_multi_target.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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compare_noise_only.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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compare_sine_1mhz.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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compare_single_target.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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compare.py

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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doppler_golden_py_moving.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_moving.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_stationary.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_stationary.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_two_targets.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_two_targets.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_input_moving.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_input_stationary.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_input_two_targets.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

fpga_model.py

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

gen_chirp_mem.py

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

gen_doppler_golden.py

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

gen_mf_cosim_golden.py

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

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gen_multiseg_golden.py

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

mf_golden_py_chirp.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_dc.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_i_chirp.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_i_dc.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_i_impulse.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_i_tone5.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_impulse.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_q_chirp.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_q_dc.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_q_impulse.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_q_tone5.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_tone5.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

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mf_ref_dc_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_dc_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_impulse_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_impulse_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_tone5_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_tone5_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_dc_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_dc_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_impulse_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_impulse_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_tone5_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_tone5_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

multiseg_golden_seg0_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg0_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg1_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg1_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg2_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg2_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg3_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg3_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_input_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_input_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg0_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg0_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg1_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg1_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg2_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg2_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg3_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg3_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_input_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_input_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_ref_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_ref_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

radar_scene.py

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

ref_chirp_i.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

ref_chirp_q.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_bb_dc.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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rtl_bb_multi_target.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

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rtl_bb_noise_only.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_bb_sine_1mhz.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_bb_single_target.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_mf_chirp.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

rtl_mf_dc.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

rtl_mf_impulse.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

rtl_mf_tone5.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

rx_final_doppler_out.csv

Add new testbenches and fix USB clock forwarding test

2026-03-16 22:24:34 +02:00

scenario_info.txt

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

validate_mem_files.py

Add .mem file validator: verify FFT twiddle + chirp .mem files against radar parameters (55/56 PASS)

2026-03-16 19:02:45 +02:00