JunghwanNA a9ceb3c851 fix(cosim): align golden_reference ADC sign conversion with RTL ...

The golden reference used (adc_val - 128) << 9 which subtracts 65536,
but the Verilog RTL computes {1'b0,adc,9'b0} - {1'b0,8'hFF,9'b0}/2
which subtracts 0xFF00 = 65280. This creates a constant 256-LSB DC
offset between the golden reference and RTL for all 256 ADC values.

The bit-accurate model in fpga_model.py already uses the correct RTL
formula. This aligns golden_reference.py to match.

Verified: all 256 ADC input values now produce zero offset against
fpga_model.py.

2026-04-16 12:27:02 +09:00

..

constraints

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

formal

fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT (follow-up to PR #33)

2026-04-06 23:15:50 +03:00

scripts

feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix

2026-04-13 19:24:11 +05:45

tb

fix(cosim): align golden_reference ADC sign conversion with RTL

2026-04-16 12:27:02 +09:00

.gitignore

CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner

2026-03-19 11:31:46 +02:00

ad9484_interface_400m.v

fix(rtl,constraints): change IBUFDS to IOSTANDARD DEFAULT for multi-target bank voltage compatibility

2026-04-07 05:17:11 +03:00

adc_clk_mmcm_integration.md

Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix

2026-03-19 22:59:46 +02:00

adc_clk_mmcm.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

cdc_modules.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

cfar_ca.v

Pipeline CFAR noise computation: break critical path for timing closure

2026-03-20 05:24:08 +02:00

chirp_memory_loader_param.v

E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)

2026-03-20 01:45:00 +02:00

cic_decimator_4x_enhanced.v

feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix

2026-04-13 19:24:11 +05:45

dac_interface_single.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

ddc_400m.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

doppler_processor.v

Fix staggered-PRF Doppler processing with dual 16-point FFTs

2026-03-27 23:05:28 +02:00

edge_detector.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

fft_engine.v

FFT engine: merge SHIFT into WRITE (5→4 cycle butterfly, 20% throughput) + barrel-shift twiddle index

2026-03-20 00:20:59 +02:00

fft_twiddle_16.mem

Fix staggered-PRF Doppler processing with dual 16-point FFTs

2026-03-27 23:05:28 +02:00

fft_twiddle_1024.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fir_lowpass.v

fix(rtl): force FIR adder tree to fabric to free 30 DSPs for FFT butterfly on 50T

2026-04-07 14:45:47 +03:00

fpga_self_test.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

frequency_matched_filter.v

Convert async→sync reset on DSP/BRAM datapath registers for timing closure

2026-03-17 20:11:13 +02:00

latency_buffer.v

Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts

2026-03-18 01:28:42 +02:00

long_chirp_lut.mem

Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)

2026-03-19 10:31:16 +02:00

long_chirp_seg0_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg0_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

matched_filter_multi_segment.v

Fix matched filter synth errors: overlap_copy_count part-select width, add FSM default

2026-03-19 20:53:29 +02:00

matched_filter_processing_chain.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

mti_canceller.v

Integrate MTI canceller and DC notch filter for ground clutter removal

2026-03-20 16:39:17 +02:00

nco_400m_enhanced.v

Improve timing margins with targeted datapath register tuning

2026-03-17 23:51:04 +02:00

plfm_chirp_controller.v

E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)

2026-03-20 01:45:00 +02:00

radar_mode_controller.v

Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)

2026-03-19 23:54:48 +02:00

radar_receiver_final.v

feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix

2026-04-13 19:24:11 +05:45

radar_system_top_50t.v

feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix

2026-04-13 19:24:11 +05:45

radar_system_top_te0712_dev.v

Add TE0712/TE0701 split target with dedicated top, XDC, and build flow

2026-03-18 03:57:26 +02:00

radar_system_top_te0713_dev.v

Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments

2026-03-19 16:47:59 +02:00

radar_system_top_te0713_umft601x_dev.v

add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)

2026-03-21 20:43:52 +02:00

radar_system_top.v

feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix

2026-04-13 19:24:11 +05:45

radar_transmitter.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

range_bin_decimator.v

Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)

2026-03-20 04:38:35 +02:00

run_regression.sh

fix: regenerate golden hex for dual-16pt Doppler and add real-data TBs to regression

2026-04-09 02:36:14 +03:00

rx_gain_control.v

fix: 9 bugs from code review — RTL sign-ext & snapshot, thread safety, protocol fixes

2026-04-13 23:35:10 +05:45

short_chirp_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

short_chirp_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

usb_data_interface_ft2232h.v

feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix

2026-04-13 19:24:11 +05:45

usb_data_interface.v

fix: FPGA timing margins (WNS +0.002→+0.080ns) + 11 bug fixes from code review

2026-04-14 00:08:26 +05:45

xfft_16.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00