NawfalMotii79
107 lines
3.2 KiB
Verilog
107 lines
3.2 KiB
Verilog
`timescale 1ns / 1ps
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// latency_buffer_2159_fixed.v
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module latency_buffer_2159 #(
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parameter DATA_WIDTH = 32,
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parameter LATENCY = 3187
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) (
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input wire clk,
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input wire reset_n,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire valid_in,
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output wire [DATA_WIDTH-1:0] data_out,
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output wire valid_out
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);
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// ========== FIXED PARAMETERS ==========
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localparam ADDR_WIDTH = 12; // Enough for 4096 entries (>2159)
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// ========== FIXED LOGIC ==========
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] bram [0:4095];
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reg [ADDR_WIDTH-1:0] write_ptr;
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reg [ADDR_WIDTH-1:0] read_ptr;
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reg valid_out_reg;
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// Delay counter to track when LATENCY cycles have passed
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reg [ADDR_WIDTH-1:0] delay_counter;
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reg buffer_has_data; // Flag when buffer has accumulated LATENCY samples
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// ========== FIXED INITIALIZATION ==========
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integer k;
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initial begin
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for (k = 0; k < 4096; k = k + 1) begin
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bram[k] = {DATA_WIDTH{1'b0}};
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end
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write_ptr = 0;
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read_ptr = 0;
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valid_out_reg = 0;
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delay_counter = 0;
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buffer_has_data = 0;
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end
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// ========== FIXED STATE MACHINE ==========
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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write_ptr <= 0;
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read_ptr <= 0;
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valid_out_reg <= 0;
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delay_counter <= 0;
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buffer_has_data <= 0;
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end else begin
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// Default: no valid output
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valid_out_reg <= 0;
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// ===== WRITE SIDE =====
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if (valid_in) begin
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// Store data
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bram[write_ptr] <= data_in;
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// Increment write pointer (wrap at 4095)
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if (write_ptr == 4095) begin
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write_ptr <= 0;
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end else begin
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write_ptr <= write_ptr + 1;
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end
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// Count how many samples we've written
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if (delay_counter < LATENCY) begin
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delay_counter <= delay_counter + 1;
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// When we've written LATENCY samples, buffer is "primed"
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if (delay_counter == LATENCY - 1) begin
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buffer_has_data <= 1'b1;
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// $display("[LAT_BUF] Buffer now has %d samples (primed)", LATENCY);
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end
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end
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end
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// ===== READ SIDE =====
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// Only start reading after we have LATENCY samples in buffer
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if (buffer_has_data && valid_in) begin
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// Read pointer follows write pointer with LATENCY delay
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// Calculate: read_ptr = (write_ptr - LATENCY) mod 4096
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// Handle wrap-around correctly
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if (write_ptr >= LATENCY) begin
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read_ptr <= write_ptr - LATENCY;
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end else begin
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// Wrap around: 4096 + write_ptr - LATENCY
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read_ptr <= 4096 + write_ptr - LATENCY;
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end
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// Output is valid
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valid_out_reg <= 1'b1;
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//$display("[LAT_BUF] Reading: write_ptr=%d, read_ptr=%d, data=%h",
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// write_ptr, read_ptr, bram[read_ptr]);
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end
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end
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end
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// ========== OUTPUTS ==========
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assign data_out = bram[read_ptr];
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assign valid_out = valid_out_reg;
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endmodule |