NawfalMotii79
55 lines
1.4 KiB
Verilog
55 lines
1.4 KiB
Verilog
`timescale 1ns / 1ps
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// ddc_input_interface.v
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module ddc_input_interface (
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input wire clk, // 100MHz
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input wire reset_n,
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// DDC Input (18-bit)
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input wire signed [17:0] ddc_i,
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input wire signed [17:0] ddc_q,
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input wire valid_i,
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input wire valid_q,
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// Scaled output (16-bit)
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output reg signed [15:0] adc_i,
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output reg signed [15:0] adc_q,
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output reg adc_valid,
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// Status
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output wire data_sync_error
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);
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// Synchronize valid signals
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reg valid_i_reg, valid_q_reg;
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reg valid_sync;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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valid_i_reg <= 1'b0;
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valid_q_reg <= 1'b0;
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valid_sync <= 1'b0;
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adc_valid <= 1'b0;
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end else begin
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valid_i_reg <= valid_i;
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valid_q_reg <= valid_q;
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// Require both I and Q valid simultaneously
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valid_sync <= valid_i_reg && valid_q_reg;
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adc_valid <= valid_sync;
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end
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end
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// Scale 18-bit to 16-bit with rounding
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// Option: Keep most significant 16 bits with rounding
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always @(posedge clk) begin
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if (valid_sync) begin
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// Round to nearest: add 0.5 LSB before truncation
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adc_i <= ddc_i[17:2] + ddc_i[1]; // Rounding
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adc_q <= ddc_q[17:2] + ddc_q[1]; // Rounding
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end
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end
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// Error detection
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assign data_sync_error = (valid_i_reg ^ valid_q_reg);
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endmodule |