Jason
254c0e6f03
Reduce routing pressure on CIC/NCO critical paths and move Doppler BRAM read-address registers to sync-reset datapath logic so Build 13 closes with stronger setup/hold slack while preserving functional behavior.
369 lines
15 KiB
Verilog
369 lines
15 KiB
Verilog
`timescale 1ns / 1ps
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module nco_400m_enhanced (
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input wire clk_400m,
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input wire reset_n,
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input wire [31:0] frequency_tuning_word,
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input wire phase_valid,
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input wire [15:0] phase_offset,
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output reg signed [15:0] sin_out,
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output reg signed [15:0] cos_out,
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output reg dds_ready
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);
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// ============================================================================
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// 6-stage pipelined NCO for 400 MHz timing closure
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//
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// Stage 1: Phase accumulator update (DSP48E1 in P=P+C mode)
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// DSP48E1 does: P_reg <= P_reg + C_port (frequency_tuning_word)
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// The P register output IS the phase accumulator — no CARRY4 chain.
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// phase_accum_reg <= P_output[31:0] (fabric register captures DSP output)
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// Stage 2: Offset addition in fabric (registered)
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// phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0}
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// Breaking DSP→CARRY4 into two registered stages eliminates the
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// critical path (was -0.594ns WNS in Build 6)
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// Stage 3a: Register LUT address (lut_index) and quadrant from phase_with_offset
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// Only 2 registers driven (minimal fanout, short routes)
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// Stage 3b: LUT read using registered lut_index → register abs values + quadrant
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// Registered LUT address → combinational LUT6 read → register
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// Eliminates the routing-dominant critical path (-0.100ns in Build 8)
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// Stage 4: Compute negations from registered abs values → register neg values
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// (CARRY4 x4 chain has registered inputs, fits in 2.5ns easily)
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// Stage 5: Quadrant sign application → sin_out, cos_out (pure MUX, no arith)
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//
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// Total latency: 6 cycles from phase_valid to sin/cos output
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// Max logic levels per stage: Stage 1=DSP48E1(internal), Stage 2=4(CARRY4x5),
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// Stage 3a=1(LUT3 quadrant+index decode), Stage 3b=1(LUT6 ROM read),
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// Stage 4=4(CARRY4 chain), Stage 5=1(MUX)
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// ============================================================================
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// Phase accumulator — DSP48E1 P output provides the accumulated phase
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// In simulation: behavioral reg. In synthesis: DSP48E1 P[31:0].
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reg [31:0] phase_accum_reg; // Stage 1 output: registered DSP48E1 P[31:0]
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reg [31:0] phase_with_offset; // Stage 2 output: phase_accum_reg + offset
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// Stage 3a pipeline registers: registered LUT address + quadrant
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reg [5:0] lut_index_pipe_sin;
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reg [5:0] lut_index_pipe_cos;
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reg [1:0] quadrant_pipe;
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// Stage 3b pipeline registers: LUT output + quadrant
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reg [15:0] sin_abs_reg, cos_abs_reg;
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reg [1:0] quadrant_reg;
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// Stage 4 pipeline registers: pre-computed negations + abs copies + quadrant
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reg signed [15:0] sin_neg_reg, cos_neg_reg;
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reg [15:0] sin_abs_reg2, cos_abs_reg2; // Pass-through for Stage 5 MUX
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reg [1:0] quadrant_reg2; // Pass-through for Stage 5 MUX
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// Valid pipeline: tracks 6-stage latency
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reg [5:0] valid_pipe;
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// Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
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wire [7:0] lut_address = phase_with_offset[31:24];
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// Quarter-wave sine LUT (0-90 degrees only)
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// Force distributed RAM (LUTRAM) — the 64x16 LUT is only 1024 bits, far too
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// small for BRAM. BRAM CLK→DOADO delay (2.454ns) + downstream negation logic
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// (1.236ns) exceeded the 2.5ns period at 400 MHz (WNS = -2.238ns). LUTRAM
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// read is combinatorial (~0.5ns through LUTs), giving the Stage 2→3 negation
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// path ~2.1ns of budget which fits comfortably.
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(* ram_style = "distributed" *) reg [15:0] sin_lut [0:63]; // 64 entries for 0-90 degrees
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// Initialize sine LUT
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integer lut_init_i;
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initial begin
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for (lut_init_i = 0; lut_init_i < 64; lut_init_i = lut_init_i + 1) begin
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sin_lut[lut_init_i] = 16'h0000;
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end
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// Initialize quarter-wave sine LUT (0-90 degrees)
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// LUT[k] = round(32767 * sin(pi/2 * k / 64)), monotonically increasing
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// FIX: Original LUT peaked at index 42 then decreased — broke cos=sin[63-k] quadrature
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sin_lut[0] = 16'h0000; sin_lut[1] = 16'h0324; sin_lut[2] = 16'h0648; sin_lut[3] = 16'h096A;
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sin_lut[4] = 16'h0C8C; sin_lut[5] = 16'h0FAB; sin_lut[6] = 16'h12C8; sin_lut[7] = 16'h15E2;
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sin_lut[8] = 16'h18F9; sin_lut[9] = 16'h1C0B; sin_lut[10] = 16'h1F1A; sin_lut[11] = 16'h2223;
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sin_lut[12] = 16'h2528; sin_lut[13] = 16'h2826; sin_lut[14] = 16'h2B1F; sin_lut[15] = 16'h2E11;
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sin_lut[16] = 16'h30FB; sin_lut[17] = 16'h33DF; sin_lut[18] = 16'h36BA; sin_lut[19] = 16'h398C;
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sin_lut[20] = 16'h3C56; sin_lut[21] = 16'h3F17; sin_lut[22] = 16'h41CE; sin_lut[23] = 16'h447A;
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sin_lut[24] = 16'h471C; sin_lut[25] = 16'h49B4; sin_lut[26] = 16'h4C3F; sin_lut[27] = 16'h4EBF;
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sin_lut[28] = 16'h5133; sin_lut[29] = 16'h539B; sin_lut[30] = 16'h55F5; sin_lut[31] = 16'h5842;
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sin_lut[32] = 16'h5A82; sin_lut[33] = 16'h5CB3; sin_lut[34] = 16'h5ED7; sin_lut[35] = 16'h60EB;
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sin_lut[36] = 16'h62F1; sin_lut[37] = 16'h64E8; sin_lut[38] = 16'h66CF; sin_lut[39] = 16'h68A6;
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sin_lut[40] = 16'h6A6D; sin_lut[41] = 16'h6C23; sin_lut[42] = 16'h6DC9; sin_lut[43] = 16'h6F5E;
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sin_lut[44] = 16'h70E2; sin_lut[45] = 16'h7254; sin_lut[46] = 16'h73B5; sin_lut[47] = 16'h7504;
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sin_lut[48] = 16'h7641; sin_lut[49] = 16'h776B; sin_lut[50] = 16'h7884; sin_lut[51] = 16'h7989;
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sin_lut[52] = 16'h7A7C; sin_lut[53] = 16'h7B5C; sin_lut[54] = 16'h7C29; sin_lut[55] = 16'h7CE3;
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sin_lut[56] = 16'h7D89; sin_lut[57] = 16'h7E1D; sin_lut[58] = 16'h7E9C; sin_lut[59] = 16'h7F09;
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sin_lut[60] = 16'h7F61; sin_lut[61] = 16'h7FA6; sin_lut[62] = 16'h7FD8; sin_lut[63] = 16'h7FF5;
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end
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// Combinational: quadrant determination and LUT index (feeds Stage 3a registers)
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wire [1:0] quadrant_w = lut_address[7:6];
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wire [5:0] lut_index = (quadrant_w[0] ^ quadrant_w[1]) ? ~lut_address[5:0] : lut_address[5:0];
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// Combinational LUT read using REGISTERED lut_index_pipe (feeds Stage 3b registers)
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// These wires are driven by lut_index_pipe (registered in Stage 3a), so the
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// combinational path is just: lut_index_pipe_reg → LUT6 (distributed RAM read)
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// This eliminates the LUT3→LUT6 two-level critical path from Build 8.
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wire [15:0] sin_abs_w = sin_lut[lut_index_pipe_sin];
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wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
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// ============================================================================
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// Stage 1: Phase accumulator (DSP48E1) — accumulates FTW each cycle
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// Stage 2: Offset addition in fabric — breaks DSP→CARRY4 critical path
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//
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// The phase accumulator is the critical path bottleneck: a 32-bit addition
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// requires 8 CARRY4 stages in fabric (2.826 ns > 2.5 ns budget at 400 MHz).
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// Solution: Use DSP48E1 in P = P + C accumulate mode.
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// - C-port carries frequency_tuning_word (zero-extended to 48 bits)
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// - CREG=1 registers the tuning word inside the DSP
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// - PREG=1 registers the accumulator output (P = P + C each cycle)
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// - The DSP48E1 48-bit ALU performs the add internally at full speed
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// - Only P[31:0] is used (32-bit phase accumulator)
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//
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// Phase offset addition is split into a separate pipeline stage:
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// Stage 1: phase_accum_reg <= P[31:0] (just capture the DSP output)
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// Stage 2: phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0}
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// This eliminates the DSP48E1.P→CARRY4 chain critical path (-0.594ns in Build 6).
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// ============================================================================
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`ifdef SIMULATION
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// ---- Behavioral model for Icarus Verilog simulation ----
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// Mimics DSP48E1 accumulator: P <= P + C, with CREG=1, PREG=1
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// Stage 1: phase_accum_reg captures accumulator output
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// Stage 2: phase_with_offset adds phase offset
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reg [31:0] phase_accumulator;
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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phase_accumulator <= 32'h00000000;
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phase_accum_reg <= 32'h00000000;
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phase_with_offset <= 32'h00000000;
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end else if (phase_valid) begin
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// Stage 1: accumulate + capture
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phase_accumulator <= phase_accumulator + frequency_tuning_word;
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phase_accum_reg <= phase_accumulator;
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// Stage 2: offset addition (uses previous cycle's phase_accum_reg)
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phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0};
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end
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end
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`else
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// ---- DSP48E1 phase accumulator for Vivado synthesis ----
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// P = P + C mode: accumulates frequency_tuning_word each clock cycle
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// Uses 1 DSP48E1 (total design: 5 of 240 available = 2.08%)
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wire [47:0] phase_accum_p; // DSP48E1 P output (48 bits, use [31:0])
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DSP48E1 #(
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// Feature control
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.A_INPUT("DIRECT"),
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.B_INPUT("DIRECT"),
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.USE_DPORT("FALSE"),
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.USE_MULT("NONE"), // No multiplier — pure ALU accumulate
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.USE_SIMD("ONE48"),
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// Pipeline registers
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.AREG(0), // A-port unused for accumulate
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.BREG(0), // B-port unused for accumulate
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.CREG(1), // Register frequency_tuning_word on C-port
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.MREG(0), // No multiplier
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.PREG(1), // P register IS the phase accumulator
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.ADREG(0),
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.ACASCREG(0),
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.BCASCREG(0),
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.ALUMODEREG(0),
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.CARRYINREG(0),
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.CARRYINSELREG(0),
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.DREG(0),
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.INMODEREG(0),
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.OPMODEREG(0),
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// Pattern detector (unused)
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.AUTORESET_PATDET("NO_RESET"),
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.MASK(48'h3fffffffffff),
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.PATTERN(48'h000000000000),
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.SEL_MASK("MASK"),
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.SEL_PATTERN("PATTERN"),
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.USE_PATTERN_DETECT("NO_PATDET")
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) dsp_phase_accum (
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// Clock and reset
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.CLK(clk_400m),
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.RSTA(1'b0),
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.RSTB(1'b0),
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.RSTM(1'b0),
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.RSTP(!reset_n), // Reset P register (phase accumulator) on !reset_n
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.RSTC(!reset_n), // Reset C register (tuning word) on !reset_n
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.RSTALLCARRYIN(1'b0),
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.RSTALUMODE(1'b0),
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.RSTCTRL(1'b0),
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.RSTD(1'b0),
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.RSTINMODE(1'b0),
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// Clock enables
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.CEA1(1'b0),
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.CEA2(1'b0),
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.CEB1(1'b0),
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.CEB2(1'b0),
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.CEC(1'b1), // Always register C (tuning word updates)
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.CEM(1'b0),
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.CEP(phase_valid), // Only accumulate when phase_valid is asserted
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.CEAD(1'b0),
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.CEALUMODE(1'b0),
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.CECARRYIN(1'b0),
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.CECTRL(1'b0),
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.CED(1'b0),
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.CEINMODE(1'b0),
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// Data ports
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.A(30'b0), // Unused for P = P + C
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.B(18'b0), // Unused for P = P + C
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.C({16'b0, frequency_tuning_word}), // Zero-extend 32-bit FTW to 48 bits
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.D(25'b0),
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.CARRYIN(1'b0),
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// Control ports
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.OPMODE(7'b0101100), // Z=P (010), Y=C (11), X=0 (00) → P = P + C
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.ALUMODE(4'b0000), // Z + X + Y + CIN (standard add)
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.INMODE(5'b00000),
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.CARRYINSEL(3'b000),
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// Output ports
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.P(phase_accum_p),
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.PATTERNDETECT(),
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.PATTERNBDETECT(),
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.OVERFLOW(),
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.UNDERFLOW(),
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.CARRYOUT(),
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// Cascade ports (unused)
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.ACIN(30'b0),
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.BCIN(18'b0),
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.CARRYCASCIN(1'b0),
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.MULTSIGNIN(1'b0),
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.PCIN(48'b0),
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.ACOUT(),
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.BCOUT(),
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.CARRYCASCOUT(),
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.MULTSIGNOUT(),
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.PCOUT()
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);
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// Stage 1: Capture DSP48E1 P output into fabric register
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// Stage 2: Add phase offset to captured value
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// Split into two registered stages to break DSP48E1.P→CARRY4 critical path
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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phase_accum_reg <= 32'h00000000;
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phase_with_offset <= 32'h00000000;
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end else if (phase_valid) begin
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// Stage 1: just capture DSP output (no CARRY4 chain)
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phase_accum_reg <= phase_accum_p[31:0];
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// Stage 2: offset add (CARRY4 chain from registered fabric→fabric, easy timing)
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phase_with_offset <= phase_accum_reg + {phase_offset, 16'b0};
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end
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end
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`endif
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// ============================================================================
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// Stage 3a: Register LUT address and quadrant from phase_with_offset
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// Only 2 registers driven (lut_index_pipe + quadrant_pipe)
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// Minimal fanout → short routes → easy timing
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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lut_index_pipe_sin <= 6'b000000;
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lut_index_pipe_cos <= 6'b000000;
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quadrant_pipe <= 2'b00;
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end else if (valid_pipe[1]) begin
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lut_index_pipe_sin <= lut_index;
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lut_index_pipe_cos <= lut_index;
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quadrant_pipe <= quadrant_w;
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end
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end
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// ============================================================================
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// Stage 3b: LUT read using registered lut_index_pipe + register abs values
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// Registered address → combinational LUT6 read → register
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// Only 1 logic level (LUT6), trivial timing
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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sin_abs_reg <= 16'h0000;
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cos_abs_reg <= 16'h7FFF;
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quadrant_reg <= 2'b00;
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end else if (valid_pipe[2]) begin
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sin_abs_reg <= sin_abs_w;
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cos_abs_reg <= cos_abs_w;
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quadrant_reg <= quadrant_pipe;
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end
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end
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// ============================================================================
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// Stage 4: Compute negations from registered abs values
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// CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
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// Also pass through abs values and quadrant for Stage 5
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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sin_neg_reg <= 16'h0000;
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cos_neg_reg <= -16'h7FFF;
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sin_abs_reg2 <= 16'h0000;
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cos_abs_reg2 <= 16'h7FFF;
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quadrant_reg2 <= 2'b00;
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end else if (valid_pipe[3]) begin
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sin_neg_reg <= -sin_abs_reg;
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cos_neg_reg <= -cos_abs_reg;
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sin_abs_reg2 <= sin_abs_reg;
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cos_abs_reg2 <= cos_abs_reg;
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quadrant_reg2 <= quadrant_reg;
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end
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end
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// ============================================================================
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// Stage 5: Quadrant sign application → final sin/cos output
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// Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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sin_out <= 16'h0000;
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cos_out <= 16'h7FFF;
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end else if (valid_pipe[4]) begin
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case (quadrant_reg2)
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2'b00: begin // Quadrant I: sin+, cos+
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sin_out <= sin_abs_reg2;
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cos_out <= cos_abs_reg2;
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end
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2'b01: begin // Quadrant II: sin+, cos-
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sin_out <= sin_abs_reg2;
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cos_out <= cos_neg_reg;
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end
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2'b10: begin // Quadrant III: sin-, cos-
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sin_out <= sin_neg_reg;
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cos_out <= cos_neg_reg;
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end
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2'b11: begin // Quadrant IV: sin-, cos+
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sin_out <= sin_neg_reg;
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cos_out <= cos_abs_reg2;
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end
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endcase
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end
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end
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// ============================================================================
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// Valid pipeline and dds_ready (6-stage latency)
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// ============================================================================
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always @(posedge clk_400m or negedge reset_n) begin
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if (!reset_n) begin
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valid_pipe <= 6'b000000;
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dds_ready <= 1'b0;
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end else begin
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valid_pipe <= {valid_pipe[4:0], phase_valid};
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dds_ready <= valid_pipe[5];
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end
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end
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// Debug verification of LUT initialization (simulation only)
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`ifdef SIMULATION
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initial begin
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#10;
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$display("NCO: Sine LUT initialized with %0d entries", 64);
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end
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`endif
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endmodule
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