Jason
f393e96d69
- Set USB_MODE default to 1 (FT2232H) in radar_system_top.v; 200T build overrides to USB_MODE=0 via build_200t.tcl generic property - Rewrite FT601 write FSM: 4-state architecture with 3-word packed data, pending-flag gating, and frame sync counter - Add FT2232H read FSM rd_cmd_complete flag, stream field zeroing, and range_data_ready 1-cycle pipeline delay in both USB modules - Implement clock-loss watchdog: ft_heartbeat toggle + 16-bit timeout counter drives ft_clk_lost, feeding ft_effective_reset_n via 2-stage ASYNC_REG synchronizer chain - Fix sample_counter reset literal width (11'd0 -> 12'd0) - Add FT2232H I/O timing constraints to 50T XDC; fix dac_clk comments - Document vestigial ft601_txe_n/rxf_n ports (needed for 200T XDC) - Tie off AGC ports on TE0713 dev wrapper - Rewrite tb_usb_data_interface.v for new 4-state FSM (89 checks) - Add USB_MODE=1 regression runs; remove dead CHECK 5/6 loop - Update diag_log.h USB interface comment
683 lines
31 KiB
Verilog
683 lines
31 KiB
Verilog
/**
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* usb_data_interface.v
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*
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* FT601 USB 3.0 SuperSpeed FIFO Interface (32-bit bus, 100 MHz ft601_clk).
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* Used on the 200T premium dev board. Production 50T board uses
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* usb_data_interface_ft2232h.v (FT2232H, 8-bit, 60 MHz) instead.
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*
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* USB disconnect recovery:
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* A clock-activity watchdog in the clk domain detects when ft601_clk_in
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* stops (USB cable unplugged). After ~0.65 ms of silence (65536 system
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* clocks) it asserts ft601_clk_lost, which is OR'd into the FT-domain
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* reset so FSMs and FIFOs return to a clean state. When ft601_clk_in
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* resumes, a 2-stage reset synchronizer deasserts the reset cleanly.
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*/
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module usb_data_interface (
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input wire clk, // Main clock (100MHz recommended)
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input wire reset_n,
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input wire ft601_reset_n, // FT601-domain synchronized reset
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// Radar data inputs
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input wire [31:0] range_profile,
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input wire range_valid,
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input wire [15:0] doppler_real,
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input wire [15:0] doppler_imag,
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input wire doppler_valid,
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input wire cfar_detection,
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input wire cfar_valid,
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// FT601 Interface (Slave FIFO mode)
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// Data bus
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inout wire [31:0] ft601_data, // 32-bit bidirectional data bus
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output reg [3:0] ft601_be, // Byte enable (active-HIGH per FT601 datasheet / AN_378)
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// Control signals
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// VESTIGIAL OUTPUTS — kept for 200T board port compatibility.
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// On the 200T, these are constrained to physical pins G21 (TXE) and
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// G22 (RXF) in xc7a200t_fbg484.xdc. Removing them from the RTL would
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// break the 200T build. They are reset to 1 and never driven; the
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// actual FT601 flow-control inputs are ft601_txe and ft601_rxf below.
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output reg ft601_txe_n, // VESTIGIAL: unused output, always 1
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output reg ft601_rxf_n, // VESTIGIAL: unused output, always 1
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input wire ft601_txe, // TXE: Transmit FIFO Not Full (active-low: 0 = space available)
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input wire ft601_rxf, // RXF: Receive FIFO Not Empty (active-low: 0 = data available)
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output reg ft601_wr_n, // Write strobe (active low)
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output reg ft601_rd_n, // Read strobe (active low)
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output reg ft601_oe_n, // Output enable (active low)
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output reg ft601_siwu_n, // Send immediate / Wakeup
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// FIFO flags
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input wire [1:0] ft601_srb, // Selected read buffer
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input wire [1:0] ft601_swb, // Selected write buffer
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// Clock
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output wire ft601_clk_out, // Output clock to FT601 (forwarded via ODDR)
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input wire ft601_clk_in, // Clock from FT601 (60/100MHz)
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// ========== HOST COMMAND OUTPUTS (Gap 4: USB Read Path) ==========
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// These outputs are registered in the ft601_clk domain and must be
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// CDC-synchronized by the consumer (radar_system_top.v) before use
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// in the clk_100m domain.
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//
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// Command word format: {opcode[7:0], addr[7:0], value[15:0]}
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// 0x01 = Set radar mode (value[1:0] -> mode_controller mode)
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// 0x02 = Single chirp trigger (value ignored, pulse cmd_valid)
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// 0x03 = Set CFAR threshold (value[15:0] -> threshold)
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// 0x04 = Set stream control (value[2:0] -> enable range/doppler/cfar)
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// 0x10-0x15 = Chirp timing configuration (Gap 2)
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// 0xFF = Status request (triggers status response packet)
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output reg [31:0] cmd_data, // Last received command word
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output reg cmd_valid, // Pulse: new command received (ft601_clk domain)
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output reg [7:0] cmd_opcode, // Decoded opcode for convenience
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output reg [7:0] cmd_addr, // Decoded register address
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output reg [15:0] cmd_value, // Decoded value
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// Gap 2: Stream control input (clk_100m domain, CDC'd internally)
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// Bit 0 = range stream enable
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// Bit 1 = doppler stream enable
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// Bit 2 = cfar/detection stream enable
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input wire [2:0] stream_control,
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// Gap 2: Status readback inputs (clk_100m domain, CDC'd internally)
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// When status_request pulses, the write FSM sends a status response
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// packet containing the current register values.
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input wire status_request, // 1-cycle pulse in clk_100m when 0xFF received
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input wire [15:0] status_cfar_threshold, // Current CFAR threshold
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input wire [2:0] status_stream_ctrl, // Current stream control
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input wire [1:0] status_radar_mode, // Current radar mode
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input wire [15:0] status_long_chirp, // Current long chirp cycles
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input wire [15:0] status_long_listen, // Current long listen cycles
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input wire [15:0] status_guard, // Current guard cycles
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input wire [15:0] status_short_chirp, // Current short chirp cycles
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input wire [15:0] status_short_listen, // Current short listen cycles
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input wire [5:0] status_chirps_per_elev, // Current chirps per elevation
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input wire [1:0] status_range_mode, // Fix 7: Current range mode (0x20)
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// Self-test status readback (opcode 0x31 / included in 0xFF status packet)
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input wire [4:0] status_self_test_flags, // Per-test PASS(1)/FAIL(0) latched
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input wire [7:0] status_self_test_detail, // Diagnostic detail byte latched
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input wire status_self_test_busy, // Self-test FSM still running
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// AGC status readback
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input wire [3:0] status_agc_current_gain,
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input wire [7:0] status_agc_peak_magnitude,
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input wire [7:0] status_agc_saturation_count,
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input wire status_agc_enable
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);
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// USB packet structure (same as before)
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localparam HEADER = 8'hAA;
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localparam FOOTER = 8'h55;
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// FT601 configuration
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localparam FT601_DATA_WIDTH = 32;
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localparam FT601_BURST_SIZE = 512; // Max burst size in bytes
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// ============================================================================
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// WRITE FSM State definitions (Verilog-2001 compatible)
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// ============================================================================
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// Rewritten: data packet is now 3 x 32-bit writes (11 payload bytes + 1 pad).
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// Word 0: {HEADER, range[31:24], range[23:16], range[15:8]} BE=1111
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// Word 1: {range[7:0], doppler_real[15:8], doppler_real[7:0], doppler_imag[15:8]} BE=1111
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// Word 2: {doppler_imag[7:0], detection, FOOTER, 8'h00} BE=1110
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localparam [3:0] IDLE = 4'd0,
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SEND_DATA_WORD = 4'd1,
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SEND_STATUS = 4'd2,
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WAIT_ACK = 4'd3;
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reg [3:0] current_state;
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reg [1:0] data_word_idx; // 0..2 for 3-word data packet
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reg [31:0] ft601_data_out;
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reg ft601_data_oe; // Output enable for bidirectional data bus
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// Pre-packed data words (registered snapshot of CDC'd data)
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reg [31:0] data_pkt_word0;
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reg [31:0] data_pkt_word1;
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reg [31:0] data_pkt_word2;
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reg [3:0] data_pkt_be2; // BE for last word (BE=1110 since byte 3 is pad)
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// ============================================================================
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// READ FSM State definitions (Gap 4: USB Read Path)
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// ============================================================================
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// FT601 245 synchronous FIFO read protocol:
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// 1. Host has data available: RXF_N = 0 (active low)
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// 2. FPGA asserts OE_N = 0 (bus turnaround: FT601 starts driving data bus)
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// 3. Wait 1 cycle for bus turnaround settling
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// 4. FPGA asserts RD_N = 0 (start reading: data valid on each posedge)
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// 5. Sample ft601_data[31:0] while RD_N = 0 and RXF_N = 0
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// 6. Deassert RD_N = 1, then OE_N = 1
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//
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// The read FSM only activates when the write FSM is IDLE and RXF indicates
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// data is available. This prevents bus contention between TX and RX.
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localparam [2:0] RD_IDLE = 3'd0, // Waiting for RXF
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RD_OE_ASSERT = 3'd1, // Assert OE_N=0, wait turnaround
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RD_READING = 3'd2, // Assert RD_N=0, sample data
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RD_DEASSERT = 3'd3, // Deassert RD_N, then OE_N
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RD_PROCESS = 3'd4; // Process received command word
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reg [2:0] read_state;
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reg [31:0] rx_data_captured; // Data word read from host
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// ========== CDC INPUT SYNCHRONIZERS (clk domain -> ft601_clk_in domain) ==========
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// The valid signals arrive from clk_100m but the state machine runs on ft601_clk_in.
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// Even though both are 100 MHz, they are asynchronous clocks and need synchronization.
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// 2-stage synchronizers for valid signals
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(* ASYNC_REG = "TRUE" *) reg [1:0] range_valid_sync;
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(* ASYNC_REG = "TRUE" *) reg [1:0] doppler_valid_sync;
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(* ASYNC_REG = "TRUE" *) reg [1:0] cfar_valid_sync;
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// Delayed versions of sync[1] for proper edge detection
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reg range_valid_sync_d;
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reg doppler_valid_sync_d;
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reg cfar_valid_sync_d;
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// Holding registers: data captured in SOURCE domain (clk_100m) when valid
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// asserts, then read by ft601 domain after synchronized valid edge.
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// This is safe because the data is stable for the entire time the valid
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// pulse is being synchronized (2+ ft601_clk cycles).
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reg [31:0] range_profile_hold;
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reg [15:0] doppler_real_hold;
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reg [15:0] doppler_imag_hold;
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reg cfar_detection_hold;
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// Gap 2: Status request toggle register (clk_100m domain).
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// Declared here (before the always block) to satisfy iverilog forward-ref rules.
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reg status_req_toggle_100m;
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// Source-domain holding registers (clk domain)
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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range_profile_hold <= 32'd0;
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doppler_real_hold <= 16'd0;
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doppler_imag_hold <= 16'd0;
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cfar_detection_hold <= 1'b0;
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status_req_toggle_100m <= 1'b0;
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end else begin
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if (range_valid)
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range_profile_hold <= range_profile;
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if (doppler_valid) begin
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doppler_real_hold <= doppler_real;
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doppler_imag_hold <= doppler_imag;
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end
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if (cfar_valid)
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cfar_detection_hold <= cfar_detection;
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// Gap 2: Toggle on status request pulse (CDC to ft601_clk)
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if (status_request)
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status_req_toggle_100m <= ~status_req_toggle_100m;
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end
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end
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// ============================================================================
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// CLOCK-ACTIVITY WATCHDOG (clk domain)
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// ============================================================================
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// Detects when ft601_clk_in stops (USB cable unplugged). A toggle register
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// in the ft601_clk domain flips every edge. The clk domain synchronizes it
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// and checks for transitions. If no transition is seen for 2^16 = 65536
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// clk cycles (~0.65 ms at 100 MHz), ft601_clk_lost asserts.
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// Toggle register: flips every ft601_clk edge (ft601_clk domain)
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reg ft601_heartbeat;
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always @(posedge ft601_clk_in or negedge ft601_reset_n) begin
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if (!ft601_reset_n)
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ft601_heartbeat <= 1'b0;
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else
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ft601_heartbeat <= ~ft601_heartbeat;
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end
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// Synchronize heartbeat into clk domain (2-stage)
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(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_hb_sync;
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reg ft601_hb_prev;
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reg [15:0] ft601_clk_timeout;
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reg ft601_clk_lost;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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ft601_hb_sync <= 2'b00;
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ft601_hb_prev <= 1'b0;
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ft601_clk_timeout <= 16'd0;
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ft601_clk_lost <= 1'b0;
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end else begin
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ft601_hb_sync <= {ft601_hb_sync[0], ft601_heartbeat};
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ft601_hb_prev <= ft601_hb_sync[1];
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if (ft601_hb_sync[1] != ft601_hb_prev) begin
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// ft601_clk is alive — reset counter, clear lost flag
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ft601_clk_timeout <= 16'd0;
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ft601_clk_lost <= 1'b0;
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end else if (!ft601_clk_lost) begin
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if (ft601_clk_timeout == 16'hFFFF)
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ft601_clk_lost <= 1'b1;
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else
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ft601_clk_timeout <= ft601_clk_timeout + 16'd1;
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end
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end
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end
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// Effective FT601-domain reset: asserted by global reset OR clock loss.
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// Deassertion synchronized to ft601_clk via 2-stage sync to avoid
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// metastability on the recovery edge.
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(* ASYNC_REG = "TRUE" *) reg [1:0] ft601_reset_sync;
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wire ft601_reset_raw_n = ft601_reset_n & ~ft601_clk_lost;
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always @(posedge ft601_clk_in or negedge ft601_reset_raw_n) begin
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if (!ft601_reset_raw_n)
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ft601_reset_sync <= 2'b00;
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else
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ft601_reset_sync <= {ft601_reset_sync[0], 1'b1};
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end
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wire ft601_effective_reset_n = ft601_reset_sync[1];
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// FT601-domain captured data (sampled from holding regs on sync'd edge)
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reg [31:0] range_profile_cap;
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reg [15:0] doppler_real_cap;
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reg [15:0] doppler_imag_cap;
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reg cfar_detection_cap;
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// Data-pending flags (ft601_clk domain).
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// Set when a valid edge is detected, cleared when the write FSM consumes
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// or skips the data. Prevents the write FSM from blocking forever when
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// a stream's valid hasn't fired yet (e.g., Doppler needs 32 chirps).
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reg doppler_data_pending;
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reg cfar_data_pending;
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// 1-cycle delayed range trigger. range_valid_ft fires on the same clock
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// edge that range_profile_cap is captured (non-blocking). If the FSM
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// reads range_profile_cap on that same edge it sees the STALE value.
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// Delaying the trigger by one cycle guarantees the capture register has
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// settled before the FSM packs the data words.
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reg range_data_ready;
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// Frame sync: sample counter (ft601_clk domain, wraps at NUM_CELLS)
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// Bit 7 of detection byte is set when sample_counter == 0 (frame start).
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localparam [11:0] NUM_CELLS = 12'd2048; // 64 range x 32 doppler
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reg [11:0] sample_counter;
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// Gap 2: CDC for stream_control (clk_100m -> ft601_clk_in)
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// stream_control changes infrequently (only on host USB command), so
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// per-bit 2-stage synchronizers are sufficient. No Gray coding needed
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// because the bits are independent enables.
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// Fix #5: Default to range-only (3'b001) on reset to prevent write FSM
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// deadlock before host configures streams. With all streams enabled on
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// reset, the first range_valid triggers the write FSM which then blocks
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// forever on SEND_DOPPLER_DATA (Doppler hasn't produced data yet).
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(* ASYNC_REG = "TRUE" *) reg [2:0] stream_ctrl_sync_0;
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(* ASYNC_REG = "TRUE" *) reg [2:0] stream_ctrl_sync_1;
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wire stream_range_en = stream_ctrl_sync_1[0];
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wire stream_doppler_en = stream_ctrl_sync_1[1];
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wire stream_cfar_en = stream_ctrl_sync_1[2];
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// Gap 2: Status request CDC (toggle CDC, same pattern as cmd_valid)
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// status_request is a 1-cycle pulse in clk_100m. Toggle→sync→edge-detect.
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// NOTE: status_req_toggle_100m declared above (before source-domain always block)
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(* ASYNC_REG = "TRUE" *) reg [1:0] status_req_sync;
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reg status_req_sync_prev;
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wire status_req_ft601 = status_req_sync[1] ^ status_req_sync_prev;
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// Status snapshot: captured in ft601_clk domain when status request arrives.
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// The clk_100m-domain status inputs are stable for many cycles after the
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// command decode, so sampling them a few ft601_clk cycles later is safe.
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reg [31:0] status_words [0:5]; // 6 status words (word 5 = self-test)
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reg [2:0] status_word_idx;
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wire range_valid_ft;
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wire doppler_valid_ft;
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wire cfar_valid_ft;
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always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
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if (!ft601_effective_reset_n) begin
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range_valid_sync <= 2'b00;
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doppler_valid_sync <= 2'b00;
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cfar_valid_sync <= 2'b00;
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range_valid_sync_d <= 1'b0;
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doppler_valid_sync_d <= 1'b0;
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cfar_valid_sync_d <= 1'b0;
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range_profile_cap <= 32'd0;
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doppler_real_cap <= 16'd0;
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doppler_imag_cap <= 16'd0;
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cfar_detection_cap <= 1'b0;
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range_data_ready <= 1'b0;
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// Fix #5: Default to range-only on reset (prevents write FSM deadlock)
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stream_ctrl_sync_0 <= 3'b001;
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stream_ctrl_sync_1 <= 3'b001;
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// Gap 2: status request CDC reset
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status_req_sync <= 2'b00;
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status_req_sync_prev <= 1'b0;
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status_word_idx <= 3'd0;
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end else begin
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// Synchronize valid strobes (2-stage sync chain)
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range_valid_sync <= {range_valid_sync[0], range_valid};
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doppler_valid_sync <= {doppler_valid_sync[0], doppler_valid};
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cfar_valid_sync <= {cfar_valid_sync[0], cfar_valid};
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// Gap 2: stream control CDC (2-stage)
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stream_ctrl_sync_0 <= stream_control;
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stream_ctrl_sync_1 <= stream_ctrl_sync_0;
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// Gap 2: status request CDC (toggle sync + edge detect)
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status_req_sync <= {status_req_sync[0], status_req_toggle_100m};
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status_req_sync_prev <= status_req_sync[1];
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// Gap 2: Capture status snapshot when request arrives in ft601 domain
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if (status_req_ft601) begin
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// Pack register values into 5x 32-bit status words
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// Word 0: {0xFF[31:24], mode[23:22], stream[21:19], 3'b000[18:16], threshold[15:0]}
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status_words[0] <= {8'hFF, status_radar_mode, status_stream_ctrl,
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3'b000, status_cfar_threshold};
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// Word 1: {long_chirp_cycles[15:0], long_listen_cycles[15:0]}
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status_words[1] <= {status_long_chirp, status_long_listen};
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// Word 2: {guard_cycles[15:0], short_chirp_cycles[15:0]}
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status_words[2] <= {status_guard, status_short_chirp};
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// Word 3: {short_listen_cycles[15:0], chirps_per_elev[5:0], 10'b0}
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status_words[3] <= {status_short_listen, 10'd0, status_chirps_per_elev};
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// Word 4: AGC metrics + range_mode
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status_words[4] <= {status_agc_current_gain, // [31:28]
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status_agc_peak_magnitude, // [27:20]
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status_agc_saturation_count, // [19:12]
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status_agc_enable, // [11]
|
|
9'd0, // [10:2] reserved
|
|
status_range_mode}; // [1:0]
|
|
// Word 5: Self-test results {reserved[6:0], busy, reserved[7:0], detail[7:0], reserved[2:0], flags[4:0]}
|
|
status_words[5] <= {7'd0, status_self_test_busy,
|
|
8'd0, status_self_test_detail,
|
|
3'd0, status_self_test_flags};
|
|
end
|
|
|
|
// Delayed version of sync[1] for edge detection
|
|
range_valid_sync_d <= range_valid_sync[1];
|
|
doppler_valid_sync_d <= doppler_valid_sync[1];
|
|
cfar_valid_sync_d <= cfar_valid_sync[1];
|
|
|
|
// Capture data on rising edge of FULLY SYNCHRONIZED valid (sync[1])
|
|
// Data in holding regs is stable by the time sync[1] rises (2+ cycles)
|
|
if (range_valid_sync[1] && !range_valid_sync_d)
|
|
range_profile_cap <= range_profile_hold;
|
|
if (doppler_valid_sync[1] && !doppler_valid_sync_d) begin
|
|
doppler_real_cap <= doppler_real_hold;
|
|
doppler_imag_cap <= doppler_imag_hold;
|
|
end
|
|
if (cfar_valid_sync[1] && !cfar_valid_sync_d) begin
|
|
cfar_detection_cap <= cfar_detection_hold;
|
|
end
|
|
|
|
// 1-cycle delayed trigger: ensures range_profile_cap has settled
|
|
// before the FSM reads it for word packing.
|
|
range_data_ready <= range_valid_ft;
|
|
end
|
|
end
|
|
|
|
// Rising-edge detect on FULLY SYNCHRONIZED valid (sync[1], not sync[0])
|
|
// This provides full 2-stage metastability protection before use.
|
|
assign range_valid_ft = range_valid_sync[1] && !range_valid_sync_d;
|
|
assign doppler_valid_ft = doppler_valid_sync[1] && !doppler_valid_sync_d;
|
|
assign cfar_valid_ft = cfar_valid_sync[1] && !cfar_valid_sync_d;
|
|
|
|
// FT601 data bus direction control
|
|
assign ft601_data = ft601_data_oe ? ft601_data_out : 32'hzzzz_zzzz;
|
|
|
|
always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
|
|
if (!ft601_effective_reset_n) begin
|
|
current_state <= IDLE;
|
|
read_state <= RD_IDLE;
|
|
data_word_idx <= 2'd0;
|
|
ft601_data_out <= 0;
|
|
ft601_data_oe <= 0;
|
|
ft601_be <= 4'b1111; // All bytes enabled for 32-bit mode
|
|
ft601_txe_n <= 1;
|
|
ft601_rxf_n <= 1;
|
|
ft601_wr_n <= 1;
|
|
ft601_rd_n <= 1;
|
|
ft601_oe_n <= 1;
|
|
ft601_siwu_n <= 1;
|
|
rx_data_captured <= 32'd0;
|
|
cmd_data <= 32'd0;
|
|
cmd_valid <= 1'b0;
|
|
cmd_opcode <= 8'd0;
|
|
cmd_addr <= 8'd0;
|
|
cmd_value <= 16'd0;
|
|
doppler_data_pending <= 1'b0;
|
|
cfar_data_pending <= 1'b0;
|
|
data_pkt_word0 <= 32'd0;
|
|
data_pkt_word1 <= 32'd0;
|
|
data_pkt_word2 <= 32'd0;
|
|
data_pkt_be2 <= 4'b1110;
|
|
sample_counter <= 12'd0;
|
|
// NOTE: ft601_clk_out is driven by the clk-domain always block below.
|
|
// Do NOT assign it here (ft601_clk_in domain) — causes multi-driven net.
|
|
end else begin
|
|
// Default: clear one-shot signals
|
|
cmd_valid <= 1'b0;
|
|
|
|
// Data-pending flag management: set on valid edge, cleared when
|
|
// consumed or skipped by write FSM. Must be in this always block
|
|
// (not the CDC sync block) to avoid Vivado multiple-driver DRC error.
|
|
if (doppler_valid_ft)
|
|
doppler_data_pending <= 1'b1;
|
|
if (cfar_valid_ft)
|
|
cfar_data_pending <= 1'b1;
|
|
|
|
// ================================================================
|
|
// READ FSM — host-to-FPGA command path (Gap 4)
|
|
//
|
|
// The read FSM takes priority over write when both could activate.
|
|
// It only starts when the write FSM is IDLE and ft601_rxf
|
|
// indicates data from host is available.
|
|
// ================================================================
|
|
case (read_state)
|
|
RD_IDLE: begin
|
|
// Only start reading if write FSM is idle and host has data.
|
|
// ft601_rxf active-low: 0 means data available from host.
|
|
if (current_state == IDLE && !ft601_rxf) begin
|
|
ft601_oe_n <= 1'b0; // Assert OE: tell FT601 to drive bus
|
|
ft601_data_oe <= 1'b0; // FPGA releases bus (FT601 drives)
|
|
read_state <= RD_OE_ASSERT;
|
|
end
|
|
end
|
|
|
|
RD_OE_ASSERT: begin
|
|
// 1-cycle turnaround: OE_N asserted, bus settling.
|
|
// FT601 spec requires 1 clock of OE_N before RD_N assertion.
|
|
if (!ft601_rxf) begin
|
|
ft601_rd_n <= 1'b0; // Assert RD: start reading
|
|
read_state <= RD_READING;
|
|
end else begin
|
|
// Host withdrew data — abort
|
|
ft601_oe_n <= 1'b1;
|
|
read_state <= RD_IDLE;
|
|
end
|
|
end
|
|
|
|
RD_READING: begin
|
|
// Data is valid on ft601_data. Sample it.
|
|
// For now we read a single 32-bit command word per transaction.
|
|
rx_data_captured <= ft601_data;
|
|
ft601_rd_n <= 1'b1; // Deassert RD
|
|
read_state <= RD_DEASSERT;
|
|
end
|
|
|
|
RD_DEASSERT: begin
|
|
// Deassert OE_N (1 cycle after RD_N deasserted)
|
|
ft601_oe_n <= 1'b1;
|
|
read_state <= RD_PROCESS;
|
|
end
|
|
|
|
RD_PROCESS: begin
|
|
// Decode the received command word and pulse cmd_valid.
|
|
// Format: {opcode[31:24], addr[23:16], value[15:0]}
|
|
cmd_data <= rx_data_captured;
|
|
cmd_opcode <= rx_data_captured[31:24];
|
|
cmd_addr <= rx_data_captured[23:16];
|
|
cmd_value <= rx_data_captured[15:0];
|
|
cmd_valid <= 1'b1;
|
|
read_state <= RD_IDLE;
|
|
end
|
|
|
|
default: read_state <= RD_IDLE;
|
|
endcase
|
|
|
|
// ================================================================
|
|
// WRITE FSM — FPGA-to-host data streaming (existing)
|
|
//
|
|
// Only operates when read FSM is idle (no bus contention).
|
|
// ================================================================
|
|
if (read_state == RD_IDLE) begin
|
|
case (current_state)
|
|
IDLE: begin
|
|
ft601_wr_n <= 1;
|
|
ft601_data_oe <= 0; // Release data bus
|
|
// Gap 2: Status readback takes priority
|
|
if (status_req_ft601 && ft601_rxf) begin
|
|
current_state <= SEND_STATUS;
|
|
status_word_idx <= 3'd0;
|
|
end
|
|
// Trigger on range_data_ready (1 cycle after range_valid_ft)
|
|
// so that range_profile_cap has settled from the CDC block.
|
|
// Gate on pending flags: only send when all enabled
|
|
// streams have fresh data (avoids stale doppler/CFAR)
|
|
else if (range_data_ready && stream_range_en
|
|
&& (!stream_doppler_en || doppler_data_pending)
|
|
&& (!stream_cfar_en || cfar_data_pending)) begin
|
|
// Don't start write if a read is about to begin
|
|
if (ft601_rxf) begin // rxf=1 means no host data pending
|
|
// Pack 11-byte data packet into 3 x 32-bit words
|
|
// Doppler fields zeroed when stream disabled
|
|
// CFAR field zeroed when stream disabled
|
|
data_pkt_word0 <= {HEADER,
|
|
range_profile_cap[31:24],
|
|
range_profile_cap[23:16],
|
|
range_profile_cap[15:8]};
|
|
data_pkt_word1 <= {range_profile_cap[7:0],
|
|
stream_doppler_en ? doppler_real_cap[15:8] : 8'd0,
|
|
stream_doppler_en ? doppler_real_cap[7:0] : 8'd0,
|
|
stream_doppler_en ? doppler_imag_cap[15:8] : 8'd0};
|
|
data_pkt_word2 <= {stream_doppler_en ? doppler_imag_cap[7:0] : 8'd0,
|
|
stream_cfar_en
|
|
? {(sample_counter == 12'd0), 6'b0, cfar_detection_cap}
|
|
: {(sample_counter == 12'd0), 7'd0},
|
|
FOOTER,
|
|
8'h00}; // pad byte
|
|
data_pkt_be2 <= 4'b1110; // 3 valid bytes + 1 pad
|
|
data_word_idx <= 2'd0;
|
|
current_state <= SEND_DATA_WORD;
|
|
end
|
|
end
|
|
end
|
|
|
|
SEND_DATA_WORD: begin
|
|
if (!ft601_txe) begin
|
|
ft601_data_oe <= 1;
|
|
ft601_wr_n <= 0;
|
|
case (data_word_idx)
|
|
2'd0: begin
|
|
ft601_data_out <= data_pkt_word0;
|
|
ft601_be <= 4'b1111;
|
|
end
|
|
2'd1: begin
|
|
ft601_data_out <= data_pkt_word1;
|
|
ft601_be <= 4'b1111;
|
|
end
|
|
2'd2: begin
|
|
ft601_data_out <= data_pkt_word2;
|
|
ft601_be <= data_pkt_be2;
|
|
end
|
|
default: ;
|
|
endcase
|
|
if (data_word_idx == 2'd2) begin
|
|
data_word_idx <= 2'd0;
|
|
current_state <= WAIT_ACK;
|
|
end else begin
|
|
data_word_idx <= data_word_idx + 2'd1;
|
|
end
|
|
end
|
|
end
|
|
|
|
// Gap 2: Status readback — send 6 x 32-bit status words
|
|
// Format: HEADER, status_words[0..5], FOOTER
|
|
SEND_STATUS: begin
|
|
if (!ft601_txe) begin
|
|
ft601_data_oe <= 1;
|
|
ft601_be <= 4'b1111;
|
|
case (status_word_idx)
|
|
3'd0: begin
|
|
// Send status header marker (0xBB = status response)
|
|
ft601_data_out <= {24'b0, 8'hBB};
|
|
ft601_be <= 4'b0001;
|
|
end
|
|
3'd1: ft601_data_out <= status_words[0];
|
|
3'd2: ft601_data_out <= status_words[1];
|
|
3'd3: ft601_data_out <= status_words[2];
|
|
3'd4: ft601_data_out <= status_words[3];
|
|
3'd5: ft601_data_out <= status_words[4];
|
|
3'd6: ft601_data_out <= status_words[5];
|
|
3'd7: begin
|
|
// Send status footer
|
|
ft601_data_out <= {24'b0, FOOTER};
|
|
ft601_be <= 4'b0001;
|
|
end
|
|
default: ;
|
|
endcase
|
|
ft601_wr_n <= 0;
|
|
if (status_word_idx == 3'd7) begin
|
|
status_word_idx <= 3'd0;
|
|
current_state <= WAIT_ACK;
|
|
end else begin
|
|
status_word_idx <= status_word_idx + 1;
|
|
end
|
|
end
|
|
end
|
|
|
|
WAIT_ACK: begin
|
|
ft601_wr_n <= 1;
|
|
ft601_data_oe <= 0; // Release data bus
|
|
// Clear pending flags — data consumed
|
|
doppler_data_pending <= 1'b0;
|
|
cfar_data_pending <= 1'b0;
|
|
// Advance frame sync counter
|
|
if (sample_counter == NUM_CELLS - 12'd1)
|
|
sample_counter <= 12'd0;
|
|
else
|
|
sample_counter <= sample_counter + 12'd1;
|
|
current_state <= IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
end
|
|
|
|
// ============================================================================
|
|
// FT601 clock output forwarding
|
|
// ============================================================================
|
|
// Forward ft601_clk_in back out via ODDR so that the forwarded clock at the
|
|
// pin has the same insertion delay as the data outputs (both go through the
|
|
// same BUFG). This makes the output delay analysis relative to the generated
|
|
// clock at the pin, where insertion delays cancel.
|
|
|
|
`ifndef SIMULATION
|
|
ODDR #(
|
|
.DDR_CLK_EDGE("OPPOSITE_EDGE"),
|
|
.INIT(1'b0),
|
|
.SRTYPE("SYNC")
|
|
) oddr_ft601_clk (
|
|
.Q(ft601_clk_out),
|
|
.C(ft601_clk_in),
|
|
.CE(1'b1),
|
|
.D1(1'b1),
|
|
.D2(1'b0),
|
|
.R(1'b0),
|
|
.S(1'b0)
|
|
);
|
|
`else
|
|
// Simulation: behavioral clock forwarding
|
|
reg ft601_clk_out_sim;
|
|
always @(posedge ft601_clk_in or negedge ft601_effective_reset_n) begin
|
|
if (!ft601_effective_reset_n)
|
|
ft601_clk_out_sim <= 1'b0;
|
|
else
|
|
ft601_clk_out_sim <= 1'b1;
|
|
end
|
|
// In simulation, just pass the clock through
|
|
assign ft601_clk_out = ft601_clk_in;
|
|
`endif
|
|
|
|
endmodule |