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PLFM_RADAR/9_Firmware/9_2_FPGA/tb/cosim
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Jason 4985eccbae Wire self-test results (0x31) to USB status readback path, add fpga_self_test to regression 
- usb_data_interface.v: Add 3 self-test status inputs, expand status packet
  from 7 words (header + 5 data + footer) to 8 words (header + 6 data + footer).
  New status_words[5] carries {busy, detail[7:0], flags[4:0]}.
- radar_system_top.v: Wire self_test_flags_latched, self_test_detail_latched,
  self_test_busy to usb_data_interface ports. Add opcode 0x31 as status
  readback alias so host can read self-test results.
- tb_usb_data_interface.v: Add self-test port connections, verify word 5 in
  Group 16, add Group 18 (busy flag + partial failure variant). 81 checks pass.
- run_regression.sh: Add fpga_self_test.v to PROD_RTL lint list and system-
  level compile lists. Add tb_fpga_self_test as Phase 1 unit test.
- 24/24 regression tests pass, lint clean (0 errors, 4 advisory warnings).
2026-03-20 20:03:11 +02:00
..
real_data
Add radar dashboard GUI with replay mode for real ADI CN0566 data visualization, FPGA self-test module, and co-sim npy arrays
2026-03-20 19:02:06 +02:00
adc_dc.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
adc_multi_target.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
adc_noise_only.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
adc_sine_1mhz.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
adc_single_target.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
bb_mf_test_i.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
bb_mf_test_q.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
compare_dc.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
compare_doppler.py
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
compare_mf_chirp.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
compare_mf_dc.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
compare_mf_impulse.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
compare_mf_tone5.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
compare_mf.py
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
compare_multi_target.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
compare_noise_only.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
compare_sine_1mhz.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
compare_single_target.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
compare.py
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
doppler_golden_py_moving.csv
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
doppler_golden_py_moving.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
doppler_golden_py_stationary.csv
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
doppler_golden_py_stationary.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
doppler_golden_py_two_targets.csv
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
doppler_golden_py_two_targets.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
doppler_input_moving.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
doppler_input_stationary.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
doppler_input_two_targets.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
fpga_model.py
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
gen_chirp_mem.py
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
gen_doppler_golden.py
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
gen_mf_cosim_golden.py
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
gen_multiseg_golden.py
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
mf_golden_py_chirp.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_dc.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_i_chirp.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_i_dc.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_i_impulse.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_i_tone5.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_impulse.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_q_chirp.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_q_dc.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_q_impulse.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_q_tone5.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_golden_py_tone5.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_ref_dc_i.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_ref_dc_q.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_ref_impulse_i.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_ref_impulse_q.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_ref_tone5_i.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_ref_tone5_q.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_sig_dc_i.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_sig_dc_q.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_sig_impulse_i.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_sig_impulse_q.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_sig_tone5_i.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
mf_sig_tone5_q.hex
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
multiseg_golden_seg0_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_golden_seg0_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_golden_seg1_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_golden_seg1_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_golden_seg2_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_golden_seg2_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_golden_seg3_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_golden_seg3_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_golden.csv
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_input_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_input_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_ref_seg0_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_ref_seg0_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_ref_seg1_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_ref_seg1_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_ref_seg2_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_ref_seg2_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_ref_seg3_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_ref_seg3_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_short_golden_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_short_golden_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_short_golden.csv
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_short_input_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_short_input_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_short_ref_i.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
multiseg_short_ref_q.hex
Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
2026-03-16 18:09:26 +02:00
radar_scene.py
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
ref_chirp_i.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
ref_chirp_q.hex
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
rtl_bb_dc.csv
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
rtl_bb_multi_target.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
rtl_bb_noise_only.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
rtl_bb_sine_1mhz.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
rtl_bb_single_target.csv
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
rtl_mf_chirp.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
rtl_mf_dc.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
rtl_mf_impulse.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
rtl_mf_tone5.csv
Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)
2026-03-16 16:23:01 +02:00
rx_final_doppler_out.csv
Wire self-test results (0x31) to USB status readback path, add fpga_self_test to regression
2026-03-20 20:03:11 +02:00
scenario_info.txt
Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation
2026-03-16 16:01:40 +02:00
validate_mem_files.py
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
2026-03-18 01:28:42 +02:00