XDC (xc7a50t_ftg256.xdc):
- Tighten FT2232H set_input_delay -min from 0.0 -> 1.0 ns
(Tco_min + trace_min estimate; 0.0 was unrealistic and under-constrained hold).
- Tighten FT2232H set_output_delay -max from 11.667 -> 5.5 ns
(Tsu_FT ~5 ns + trace_max; previous value budgeted the full 16.67 ns period).
- Replace pairwise 'set_false_path -from CLK -to CLK' CDC waivers with
'set_clock_groups -asynchronous' for the four domain pairs:
clk_100m <-> adc_dco_p, clk_100m <-> clk_120m_dac,
clk_100m <-> ft_clkout, clk_120m_dac <-> ft_clkout.
Rationale: clock-groups is the idiomatic SDC form. Pairwise false_path is
over-broad and masks inadvertent unrelated CDCs introduced in future PRs.
Narrow register-level false_path on reset_sync_reg[*] is kept.
radar_system_top_50t.v:
- Add top-level differential input ports adc_or_p/n (AD9484 overflow flag,
pads M6/N6) and fpga_adc_clock_p/n (AD9523->ADC sample clock tap, pads
N11/N12, input-only to avoid contention with AD9523 driver).
- Anchor both via IBUFDS (DIFF_TERM=TRUE, IOSTANDARD=LVDS_25) wrapped in
(* DONT_TOUCH = "TRUE" *) so synthesis cannot strip the ports.
- Buffered nets (adc_or_buf, fpga_adc_clock_buf) are intentionally
unconsumed pending a follow-up PR that wires adc_or_buf into the
receive-path status flags (issue: numeric-saturation visibility to MCU)
and decides whether fpga_adc_clock_buf is diagnostic-only or feeds an
MMCM (in which case the buffer will need to move to a clock-capable
path).
Not validated locally: no Verilator / Vivado on the dev host. Requires
report_timing_summary and report_cdc on the remote Vivado 2025.2 host
before bitstream release.
Jason
9a3a080c42