NawfalMotii79
297 lines
11 KiB
C
297 lines
11 KiB
C
/**
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* MIT License
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*
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* Copyright (c) 2020 Jimmy Pentz
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*
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* Reach me at: github.com/jgpentz, jpentz1( at )gmail.com
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sells
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in all
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* copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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/* ADAR1000 4-Channel, X Band and Ku Band Beamformer */
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#ifndef LIB_ADAR1000_H_
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#define LIB_ADAR1000_H_
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extern SPI_HandleTypeDef hspi1;
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#ifndef NULL
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#define NULL (0)
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#endif
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// ----------------------------------------------------------------------------
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// Includes
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// ----------------------------------------------------------------------------
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#include "main.h"
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#include "hardware_config.h"
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#include "stm32f7xx_hal.h"
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#include "stm32f7xx_hal_spi.h"
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#include "stm32f7xx_hal_gpio.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include <string.h>
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#ifdef __cplusplus
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extern "C" { // Prevent C++ name mangling
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#endif
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// ----------------------------------------------------------------------------
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// Datatypes
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// ----------------------------------------------------------------------------
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extern const uint8_t VM_GAIN[128];
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extern const uint8_t VM_I[128];
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extern const uint8_t VM_Q[128];
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/// A function pointer prototype for a SPI transfer, the 3 parameters would be
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/// p_txData, p_rxData, and size (number of bytes to transfer), respectively.
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typedef uint32_t (*Adar_SpiTransfer)( uint8_t *, uint8_t *, uint32_t);
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typedef struct
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{
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uint8_t dev_addr; ///< 2-bit device hardware address, 0x00, 0x01, 0x10, 0x11
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Adar_SpiTransfer Transfer; ///< Function pointer to the function used for SPI transfers
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uint8_t * p_rx_buffer; ///< Data buffer to store received bytes into
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}const AdarDevice;
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/// Use this to store bias current values into, as seen in the datasheet
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/// Table 6. SPI Settings for Different Power Modules
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typedef struct
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{
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uint8_t rx_lna; ///< nominal: 8, low power: 5
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uint8_t rx_vm; ///< nominal: 5, low power: 2
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uint8_t rx_vga; ///< nominal: 10, low power: 3
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uint8_t tx_vm; ///< nominal: 5, low power: 2
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uint8_t tx_vga; ///< nominal: 5, low power: 5
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uint8_t tx_drv; ///< nominal: 6, low power: 3
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} AdarBiasCurrents;
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/// Useful for queries regarding the device info
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typedef struct
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{
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uint8_t norm_operating_mode : 2;
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uint8_t cust_operating_mode : 2;
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uint8_t dev_status : 4;
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uint8_t chip_type;
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uint16_t product_id;
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uint8_t scratchpad;
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uint8_t spi_rev;
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uint16_t vendor_id;
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uint8_t rev_id;
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} AdarDeviceInfo;
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/// Return types for functions in this library
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typedef enum {
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ADAR_ERROR_NOERROR = 0,
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ADAR_ERROR_FAILED = 1,
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ADAR_ERROR_INVALIDADDR = 2,
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} AdarErrorCodes;
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// ----------------------------------------------------------------------------
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// Function Prototypes
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// ----------------------------------------------------------------------------
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void Adar_AdcInit(const AdarDevice * p_adar, uint8_t broadcast_bit);
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uint8_t Adar_AdcRead(const AdarDevice * p_adar, uint8_t broadcast_bit);
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uint8_t Adar_GetDeviceInfo(const AdarDevice * p_adar, AdarDeviceInfo * info);
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uint8_t Adar_Read(const AdarDevice * p_adar, uint32_t mem_addr);
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void Adar_ReadBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size);
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uint8_t Adar_SetBiasCurrents(const AdarDevice * p_adar, AdarBiasCurrents * p_bias, uint8_t broadcast_bit);
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uint8_t Adar_SetBiasVoltages(const AdarDevice * p_adar, uint8_t bias_on_voltage[5], uint8_t bias_off_voltage[5]);
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uint8_t Adar_SetRamBypass(const AdarDevice * p_adar, uint8_t broadcast_bit);
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uint8_t Adar_SetRxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast_bit);
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uint8_t Adar_SetRxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast_bit);
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uint8_t Adar_SetTxBias(const AdarDevice * p_adar, uint8_t broadcast_bit);
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uint8_t Adar_SetTxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast_bit);
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uint8_t Adar_SetTxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast_bit);
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void Adar_SoftReset(const AdarDevice * p_adar);
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void Adar_SoftResetAll(const AdarDevice * p_adar);
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void Adar_Write(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data, uint8_t broadcast_bit);
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void Adar_WriteBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size);
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void Adar_WriteConfigA(const AdarDevice * p_adar, uint8_t flags, uint8_t broadcast);
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uint8_t Adar_WriteVerify(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data);
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void Adar_SetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast);
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void Adar_ResetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast);
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// ----------------------------------------------------------------------------
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// Preprocessor Definitions and Constants
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// ----------------------------------------------------------------------------
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// Using BROADCAST_ON will send a command to all ADARs that share a bus
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#define BROADCAST_OFF 0
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#define BROADCAST_ON 1
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// The minimum size of a read from the ADARs consists of 3 bytes
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#define ADAR1000_RD_SIZE 3
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// Address at which the TX RAM starts
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#define ADAR_TX_RAM_START_ADDR 0x1800
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// ADC Defines
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#define ADAR1000_ADC_2MHZ_CLK 0x00
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#define ADAR1000_ADC_EN 0x60
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#define ADAR1000_ADC_ST_CONV 0x70
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/* REGISTER DEFINITIONS */
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#define REG_INTERFACE_CONFIG_A 0x000
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#define REG_INTERFACE_CONFIG_B 0x001
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#define REG_DEV_CONFIG 0x002
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#define REG_SCRATCHPAD 0x00A
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#define REG_TRANSFER 0x00F
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#define REG_CH1_RX_GAIN 0x010
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#define REG_CH2_RX_GAIN 0x011
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#define REG_CH3_RX_GAIN 0x012
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#define REG_CH4_RX_GAIN 0x013
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#define REG_CH1_RX_PHS_I 0x014
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#define REG_CH1_RX_PHS_Q 0x015
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#define REG_CH2_RX_PHS_I 0x016
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#define REG_CH2_RX_PHS_Q 0x017
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#define REG_CH3_RX_PHS_I 0x018
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#define REG_CH3_RX_PHS_Q 0x019
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#define REG_CH4_RX_PHS_I 0x01A
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#define REG_CH4_RX_PHS_Q 0x01B
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#define REG_CH1_TX_GAIN 0x01C
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#define REG_CH2_TX_GAIN 0x01D
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#define REG_CH3_TX_GAIN 0x01E
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#define REG_CH4_TX_GAIN 0x01F
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#define REG_CH1_TX_PHS_I 0x020
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#define REG_CH1_TX_PHS_Q 0x021
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#define REG_CH2_TX_PHS_I 0x022
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#define REG_CH2_TX_PHS_Q 0x023
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#define REG_CH3_TX_PHS_I 0x024
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#define REG_CH3_TX_PHS_Q 0x025
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#define REG_CH4_TX_PHS_I 0x026
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#define REG_CH4_TX_PHS_Q 0x027
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#define REG_LOAD_WORKING 0x028
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#define REG_PA_CH1_BIAS_ON 0x029
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#define REG_PA_CH2_BIAS_ON 0x02A
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#define REG_PA_CH3_BIAS_ON 0x02B
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#define REG_PA_CH4_BIAS_ON 0x02C
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#define REG_LNA_BIAS_ON 0x02D
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#define REG_RX_ENABLES 0x02E
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#define REG_TX_ENABLES 0x02F
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#define REG_MISC_ENABLES 0x030
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#define REG_SW_CONTROL 0x031
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#define REG_ADC_CONTROL 0x032
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#define REG_ADC_CONTROL_TEMP_EN 0xf0
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#define REG_ADC_OUT 0x033
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#define REG_BIAS_CURRENT_RX_LNA 0x034
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#define REG_BIAS_CURRENT_RX 0x035
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#define REG_BIAS_CURRENT_TX 0x036
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#define REG_BIAS_CURRENT_TX_DRV 0x037
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#define REG_MEM_CTL 0x038
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#define REG_RX_CHX_MEM 0x039
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#define REG_TX_CHX_MEM 0x03A
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#define REG_RX_CH1_MEM 0x03D
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#define REG_RX_CH2_MEM 0x03E
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#define REG_RX_CH3_MEM 0x03F
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#define REG_RX_CH4_MEM 0x040
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#define REG_TX_CH1_MEM 0x041
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#define REG_TX_CH2_MEM 0x042
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#define REG_TX_CH3_MEM 0x043
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#define REG_TX_CH4_MEM 0x044
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#define REG_PA_CH1_BIAS_OFF 0x046
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#define REG_PA_CH2_BIAS_OFF 0x047
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#define REG_PA_CH3_BIAS_OFF 0x048
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#define REG_PA_CH4_BIAS_OFF 0x049
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#define REG_LNA_BIAS_OFF 0x04A
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#define REG_TX_BEAM_STEP_START 0x04D
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#define REG_TX_BEAM_STEP_STOP 0x04E
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#define REG_RX_BEAM_STEP_START 0x04F
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#define REG_RX_BEAM_STEP_STOP 0x050
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// REGISTER CONSTANTS
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#define INTERFACE_CONFIG_A_SOFTRESET ((1 << 7) | (1 << 0))
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#define INTERFACE_CONFIG_A_LSB_FIRST ((1 << 6) | (1 << 1))
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#define INTERFACE_CONFIG_A_ADDR_ASCN ((1 << 5) | (1 << 2))
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#define INTERFACE_CONFIG_A_SDO_ACTIVE ((1 << 4) | (1 << 3))
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#define LD_WRK_REGS_LDRX_OVERRIDE (1 << 0)
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#define LD_WRK_REGS_LDTX_OVERRIDE (1 << 1)
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#define RX_ENABLES_TX_VGA_EN (1 << 0)
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#define RX_ENABLES_TX_VM_EN (1 << 1)
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#define RX_ENABLES_TX_DRV_EN (1 << 2)
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#define RX_ENABLES_CH3_TX_EN (1 << 3)
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#define RX_ENABLES_CH2_TX_EN (1 << 4)
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#define RX_ENABLES_CH1_TX_EN (1 << 5)
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#define RX_ENABLES_CH0_TX_EN (1 << 6)
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#define TX_ENABLES_TX_VGA_EN (1 << 0)
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#define TX_ENABLES_TX_VM_EN (1 << 1)
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#define TX_ENABLES_TX_DRV_EN (1 << 2)
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#define TX_ENABLES_CH3_TX_EN (1 << 3)
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#define TX_ENABLES_CH2_TX_EN (1 << 4)
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#define TX_ENABLES_CH1_TX_EN (1 << 5)
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#define TX_ENABLES_CH0_TX_EN (1 << 6)
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#define MISC_ENABLES_CH4_DET_EN (1 << 0)
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#define MISC_ENABLES_CH3_DET_EN (1 << 1)
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#define MISC_ENABLES_CH2_DET_EN (1 << 2)
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#define MISC_ENABLES_CH1_DET_EN (1 << 3)
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#define MISC_ENABLES_LNA_BIAS_OUT_EN (1 << 4)
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#define MISC_ENABLES_BIAS_EN (1 << 5)
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#define MISC_ENABLES_BIAS_CTRL (1 << 6)
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#define MISC_ENABLES_SW_DRV_TR_MODE_SEL (1 << 7)
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#define SW_CTRL_POL (1 << 0)
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#define SW_CTRL_TR_SPI (1 << 1)
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#define SW_CTRL_TR_SOURCE (1 << 2)
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#define SW_CTRL_SW_DRV_EN_POL (1 << 3)
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#define SW_CTRL_SW_DRV_EN_TR (1 << 4)
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#define SW_CTRL_RX_EN (1 << 5)
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#define SW_CTRL_TX_EN (1 << 6)
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#define SW_CTRL_SW_DRV_TR_STATE (1 << 7)
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#define MEM_CTRL_RX_CHX_RAM_BYPASS (1 << 0)
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#define MEM_CTRL_TX_CHX_RAM_BYPASS (1 << 1)
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#define MEM_CTRL_RX_BEAM_STEP_EN (1 << 2)
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#define MEM_CTRL_TX_BEAM_STEP_EN (1 << 3)
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#define MEM_CTRL_BIAS_RAM_BYPASS (1 << 5)
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#define MEM_CTRL_BEAM_RAM_BYPASS (1 << 6)
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#define MEM_CTRL_SCAN_MODE_EN (1 << 7)
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#ifdef __cplusplus
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} // End extern "C"
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#endif
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#endif /* LIB_ADAR1000_H_ */
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