NawfalMotii79
353 lines
10 KiB
Verilog
353 lines
10 KiB
Verilog
`timescale 1ns / 1ps
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module radar_receiver_final (
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input wire clk, // 100MHz
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input wire reset_n,
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// ADC Physical Interface (LVDS Inputs)
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input wire [7:0] adc_d_p, // ADC Data P (LVDS)
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input wire [7:0] adc_d_n, // ADC Data N (LVDS)
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input wire adc_dco_p, // Data Clock Output P (400MHz LVDS)
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input wire adc_dco_n, // Data Clock Output N (400MHz LVDS)
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output wire adc_pwdn,
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output reg [31:0] doppler_output,
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output reg doppler_valid,
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output reg [4:0] doppler_bin,
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output reg [5:0] range_bin
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);
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// ========== INTERNAL SIGNALS ==========
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wire use_long_chirp;
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wire [5:0] chirp_counter;
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wire chirp_start;
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wire azimuth_change;
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wire elevation_change;
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wire [1:0] segment_request;
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wire mem_request;
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wire [15:0] ref_i, ref_q;
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wire mem_ready;
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wire [15:0] adc_i_scaled, adc_q_scaled;
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wire adc_valid_sync;
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// Reference signals for the processing chain
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wire [15:0] long_chirp_real, long_chirp_imag;
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wire [15:0] short_chirp_real, short_chirp_imag;
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// ========== DOPPLER PROCESSING SIGNALS ==========
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wire [31:0] range_data_32bit;
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wire range_data_valid;
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wire new_chirp_frame;
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// Doppler processor outputs
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wire [31:0] doppler_spectrum;
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wire doppler_spectrum_valid;
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wire [4:0] doppler_bin_out;
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wire [5:0] doppler_range_bin_out;
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wire doppler_processing;
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wire doppler_frame_done;
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// ========== RANGE BIN DECIMATOR SIGNALS ==========
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wire signed [15:0] decimated_range_i;
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wire signed [15:0] decimated_range_q;
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wire decimated_range_valid;
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wire [5:0] decimated_range_bin;
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// ========== MODULE INSTANTIATIONS ==========
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reg clk_400m;
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lvds_to_cmos_400m clk_400m_inst(
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// ADC Physical Interface (LVDS Inputs)
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.clk_400m_p(adc_dco_p), // Data Clock Output P (400MHz LVDS, 2.5V)
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.clk_400m_n(adc_dco_n), // Data Clock Output N (400MHz LVDS, 2.5V)
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.reset_n(reset_n), // Active-low reset
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// CMOS Output Interface (400MHz Domain)
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.clk_400m_cmos(clk_400m) // ADC data clock (CMOS, 3.3V)
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);
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// 1. ADC + CDC + AGC
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// CMOS Output Interface (400MHz Domain)
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wire [7:0] adc_data_cmos; // 8-bit ADC data (CMOS)
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wire adc_dco_cmos; // ADC data clock (CMOS, 400MHz)
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wire adc_valid; // Data valid signal
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wire [7:0] cdc_data_cmos; // 8-bit ADC data (CMOS)
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wire cdc_valid; // Data valid signal
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ad9484_lvds_to_cmos_400m adc (
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.adc_d_p(adc_d_p),
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.adc_d_n(adc_d_n),
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.adc_dco_p(adc_dco_p),
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.adc_dco_n(adc_dco_n),
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.reset_n(reset_n),
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.adc_data_cmos(adc_data_cmos),
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.adc_dco_cmos(adc_dco_cmos),
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.adc_valid(adc_valid),
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.adc_pwdn(adc_pwdn)
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);
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cdc_adc_to_processing #(
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.WIDTH(8),
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.STAGES(3)
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)cdc(
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.src_clk(adc_dco_cmos),
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.dst_clk(clk_400m),
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.reset_n(reset_n),
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.src_data(adc_data_cmos),
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.src_valid(adc_valid),
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.dst_data(cdc_data_cmos),
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.dst_valid(cdc_valid)
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);
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// 2. DDC Input Interface
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wire signed [17:0] ddc_out_i;
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wire signed [17:0] ddc_out_q;
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wire ddc_valid_i;
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wire ddc_valid_q;
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ddc_400m_enhanced ddc(
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.clk_400m(clk_400m), // 400MHz clock from ADC DCO
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.clk_100m(clk), // 100MHz system clock //used by the 2 FIR
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.reset_n(reset_n),
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.adc_data(cdc_data_cmos), // ADC data at 400MHz (unsigned 0-255)
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.adc_data_valid_i(cdc_valid), // Valid at 400MHz
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.adc_data_valid_q(cdc_valid), // Valid at 400MHz
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.baseband_i(ddc_out_i), // I output at 100MHz
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.baseband_q(ddc_out_q), // Q output at 100MHz
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.baseband_valid_i(ddc_valid_i), // Valid at 100MHz
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.baseband_valid_q(ddc_valid_q),
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.mixers_enable(1'b1),
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.bypass_mode(1'b1)
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);
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ddc_input_interface ddc_if (
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.clk(clk),
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.reset_n(reset_n),
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.ddc_i(ddc_out_i),
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.ddc_q(ddc_out_q),
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.valid_i(ddc_valid_i),
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.valid_q(ddc_valid_q),
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.adc_i(adc_i_scaled),
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.adc_q(adc_q_scaled),
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.adc_valid(adc_valid_sync),
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.data_sync_error()
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);
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// 3. Dual Chirp Memory Loader
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chirp_memory_loader_param chirp_mem (
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.clk(clk),
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.reset_n(reset_n),
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.segment_select(segment_request),
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.mem_request(mem_request),
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.use_long_chirp(use_long_chirp),
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.sample_addr(sample_addr_from_chain),
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.ref_i(ref_i),
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.ref_q(ref_q),
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.mem_ready(mem_ready)
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);
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// Sample address generator
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reg [9:0] sample_addr_reg;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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sample_addr_reg <= 0;
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end else if (mem_request) begin
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sample_addr_reg <= sample_addr_reg + 1;
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if (sample_addr_reg == 1023) sample_addr_reg <= 0;
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end
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end
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assign sample_addr_wire = sample_addr_reg;
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// 4. CRITICAL: Reference Chirp Latency Buffer
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// This aligns reference data with FFT output (2159 cycle delay)
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wire [15:0] delayed_ref_i, delayed_ref_q;
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wire mem_ready_delayed;
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latency_buffer_2159 #(
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.DATA_WIDTH(32), // 16-bit I + 16-bit Q
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.LATENCY(3187)
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) ref_latency_buffer (
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.clk(clk),
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.reset_n(reset_n),
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.data_in({ref_i, ref_q}),
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.valid_in(mem_request),
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.data_out({delayed_ref_i, delayed_ref_q}),
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.valid_out(mem_ready_delayed)
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);
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// Assign delayed reference signals
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assign long_chirp_real = delayed_ref_i;
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assign long_chirp_imag = delayed_ref_q;
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assign short_chirp_real = delayed_ref_i;
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assign short_chirp_imag = delayed_ref_q;
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// 5. Dual Chirp Matched Filter
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wire [9:0] sample_addr_from_chain;
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wire signed [15:0] range_profile_i;
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wire signed [15:0] range_profile_q;
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wire range_valid;
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matched_filter_multi_segment mf_dual (
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.clk(clk),
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.reset_n(reset_n),
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.ddc_i({{2{adc_i_scaled[15]}}, adc_i_scaled}),
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.ddc_q({{2{adc_q_scaled[15]}}, adc_q_scaled}),
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.ddc_valid(adc_valid_sync),
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.use_long_chirp(use_long_chirp),
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.chirp_counter(chirp_counter),
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.mc_new_chirp(mc_new_chirp),
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.mc_new_elevation(mc_new_elevation),
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.mc_new_azimuth(mc_new_azimuth),
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.long_chirp_real(delayed_ref_i), // From latency buffer
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.long_chirp_imag(delayed_ref_q),
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.short_chirp_real(delayed_ref_i), // Same for short chirp
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.short_chirp_imag(delayed_ref_q),
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.segment_request(segment_request),
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.mem_request(mem_request),
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.sample_addr_out(sample_addr_from_chain),
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.ref_i(16'd0), // Direct ref to multi_seg
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.ref_q(16'd0),
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.mem_ready(mem_ready),
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.pc_i_w(range_profile_i),
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.pc_q_w(range_profile_q),
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.pc_valid_w(range_valid)
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);
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// ========== CRITICAL: RANGE BIN DECIMATOR ==========
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// Convert 1024 range bins to 64 bins for Doppler
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range_bin_decimator #(
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.INPUT_BINS(1024),
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.OUTPUT_BINS(64),
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.DECIMATION_FACTOR(16)
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) range_decim (
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.clk(clk),
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.reset_n(reset_n),
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.range_i_in(range_profile_i),
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.range_q_in(range_profile_q),
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.range_valid_in(range_valid),
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.range_i_out(decimated_range_i),
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.range_q_out(decimated_range_q),
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.range_valid_out(decimated_range_valid),
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.range_bin_index(decimated_range_bin),
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.decimation_mode(2'b01), // Peak detection mode
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.start_bin(10'd0)
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);
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// ========== FRAME SYNC USING chirp_counter ==========
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reg [5:0] chirp_counter_prev;
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reg new_frame_pulse;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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chirp_counter_prev <= 6'd0;
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new_frame_pulse <= 1'b0;
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end else begin
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// Default: no pulse
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new_frame_pulse <= 1'b0;
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// ===== CHOOSE ONE FRAME DETECTION METHOD =====
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// METHOD A: Detect frame start at chirp_counter = 0
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// (Assumes frames are 64 chirps: 0-63)
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//if (chirp_counter == 6'd0 && chirp_counter_prev != 6'd0) begin
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// new_frame_pulse <= 1'b1;
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//end
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// METHOD B: Detect frame start at chirp_counter = 0 AND 32
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// (For 32-chirp frames in a 64-chirp sequence)
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if ((chirp_counter == 6'd0 || chirp_counter == 6'd32) &&
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(chirp_counter_prev != chirp_counter)) begin
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new_frame_pulse <= 1'b1;
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end
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// METHOD C: Programmable frame start
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// localparam FRAME_START_CHIRP = 6'd0; // Set based on your sequence
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// if (chirp_counter == FRAME_START_CHIRP &&
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// chirp_counter_prev != FRAME_START_CHIRP) begin
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// new_frame_pulse <= 1'b1;
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// end
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// Store previous value
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chirp_counter_prev <= chirp_counter;
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end
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end
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assign new_chirp_frame = new_frame_pulse;
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// ========== DATA PACKING FOR DOPPLER ==========
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assign range_data_32bit = {decimated_range_q, decimated_range_i};
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assign range_data_valid = decimated_range_valid;
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// ========== DOPPLER PROCESSOR ==========
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doppler_processor_optimized #(
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.DOPPLER_FFT_SIZE(32),
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.RANGE_BINS(64),
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.CHIRPS_PER_FRAME(32) // MUST MATCH YOUR ACTUAL FRAME SIZE!
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) doppler_proc (
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.clk(clk),
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.reset_n(reset_n),
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.range_data(range_data_32bit),
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.data_valid(range_data_valid),
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.new_chirp_frame(new_chirp_frame),
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// Outputs
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.doppler_output(doppler_output),
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.doppler_valid(doppler_valid),
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.doppler_bin(doppler_bin),
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.range_bin(doppler_range_bin_out),
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// Status
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.processing_active(doppler_processing),
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.frame_complete(doppler_frame_done),
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.status()
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);
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// ========== OUTPUT CONNECTIONS ==========
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assign doppler_range_bin = doppler_range_bin_out;
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assign doppler_processing_active = doppler_processing;
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assign doppler_frame_complete = doppler_frame_done;
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// ========== STATUS ==========
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// ========== DEBUG AND VERIFICATION ==========
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reg [31:0] frame_counter;
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reg [5:0] chirps_in_current_frame;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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frame_counter <= 0;
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chirps_in_current_frame <= 0;
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end else begin
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// Count chirps in current frame
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if (range_data_valid && decimated_range_bin == 0) begin
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// First range bin of a chirp
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chirps_in_current_frame <= chirps_in_current_frame + 1;
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end
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// Detect frame completion
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if (new_chirp_frame) begin
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frame_counter <= frame_counter + 1;
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$display("[TOP] Frame %0d started. Previous frame had %0d chirps",
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frame_counter, chirps_in_current_frame);
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chirps_in_current_frame <= 0;
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end
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// Monitor chirp counter pattern
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if (chirp_counter != chirp_counter_prev) begin
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$display("[TOP] chirp_counter: %0d ? %0d",
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chirp_counter_prev, chirp_counter);
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end
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end
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end
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endmodule |