NawfalMotii79
51 lines
1.2 KiB
Verilog
51 lines
1.2 KiB
Verilog
`timescale 1ns / 1ps
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/**
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* level_shifter_interface.v
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*
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* Simple level shifter interface for STM32 to ADAR1000 communication
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* Converts 3.3V SPI signals to 1.8V for ADAR1000 beamformer chips
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*/
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module level_shifter_interface (
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input wire clk,
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input wire reset_n,
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// 3.3V side (from STM32)
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input wire sclk_3v3,
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input wire mosi_3v3,
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output wire miso_3v3,
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input wire cs_3v3,
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// 1.8V side (to ADAR1000)
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output wire sclk_1v8,
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output wire mosi_1v8,
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input wire miso_1v8,
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output wire cs_1v8
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);
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// Simple level shifting through synchronization
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reg sclk_sync, mosi_sync, cs_sync;
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reg miso_sync;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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sclk_sync <= 1'b0;
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mosi_sync <= 1'b0;
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cs_sync <= 1'b1;
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miso_sync <= 1'b0;
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end else begin
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sclk_sync <= sclk_3v3;
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mosi_sync <= mosi_3v3;
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cs_sync <= cs_3v3;
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miso_sync <= miso_1v8;
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end
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end
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// Output assignments (direct connection with synchronization)
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assign sclk_1v8 = sclk_sync;
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assign mosi_1v8 = mosi_sync;
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assign cs_1v8 = cs_sync;
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assign miso_3v3 = miso_sync;
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endmodule |