NawfalMotii79
124 lines
4.5 KiB
Verilog
124 lines
4.5 KiB
Verilog
`timescale 1ns / 1ps
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module fir_lowpass_parallel_enhanced (
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input wire clk,
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input wire reset_n,
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input wire signed [17:0] data_in,
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input wire data_valid,
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output reg signed [17:0] data_out,
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output reg data_out_valid,
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output wire fir_ready,
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output wire filter_overflow
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);
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parameter TAPS = 32;
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parameter COEFF_WIDTH = 18;
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parameter DATA_WIDTH = 18;
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parameter ACCUM_WIDTH = 36;
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// Filter coefficients
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reg signed [COEFF_WIDTH-1:0] coeff [0:TAPS-1];
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// Parallel delay line
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reg signed [DATA_WIDTH-1:0] delay_line [0:TAPS-1];
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// Parallel multiply-accumulate structure
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wire signed [DATA_WIDTH+COEFF_WIDTH-1:0] mult_result [0:TAPS-1];
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// Wires for parallel addition (combinatorial)
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wire signed [ACCUM_WIDTH-1:0] sum_stage1_0, sum_stage1_1, sum_stage1_2, sum_stage1_3;
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wire signed [ACCUM_WIDTH-1:0] sum_stage2_0, sum_stage2_1;
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wire signed [ACCUM_WIDTH-1:0] sum_stage3;
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// Registered accumulator
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reg signed [ACCUM_WIDTH-1:0] accumulator_reg;
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// Initialize coefficients
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initial begin
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// Proper low-pass filter coefficients
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coeff[ 0] = 18'sh00AD; coeff[ 1] = 18'sh00CE; coeff[ 2] = 18'sh3FD87; coeff[ 3] = 18'sh02A6;
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coeff[ 4] = 18'sh00E0; coeff[ 5] = 18'sh3F8C0; coeff[ 6] = 18'sh0A45; coeff[ 7] = 18'sh3FD82;
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coeff[ 8] = 18'sh3F0B5; coeff[ 9] = 18'sh1CAD; coeff[10] = 18'sh3EE59; coeff[11] = 18'sh3E821;
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coeff[12] = 18'sh4841; coeff[13] = 18'sh3B340; coeff[14] = 18'sh3E299; coeff[15] = 18'sh1FFFF;
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coeff[16] = 18'sh1FFFF; coeff[17] = 18'sh3E299; coeff[18] = 18'sh3B340; coeff[19] = 18'sh4841;
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coeff[20] = 18'sh3E821; coeff[21] = 18'sh3EE59; coeff[22] = 18'sh1CAD; coeff[23] = 18'sh3F0B5;
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coeff[24] = 18'sh3FD82; coeff[25] = 18'sh0A45; coeff[26] = 18'sh3F8C0; coeff[27] = 18'sh00E0;
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coeff[28] = 18'sh02A6; coeff[29] = 18'sh3FD87; coeff[30] = 18'sh00CE; coeff[31] = 18'sh00AD;
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end
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// Generate parallel multipliers
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genvar k;
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generate
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for (k = 0; k < TAPS; k = k + 1) begin : mult_gen
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assign mult_result[k] = delay_line[k] * coeff[k];
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end
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endgenerate
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// COMBINATORIAL PARALLEL ADDITION TREE
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// Stage 1: Group of 8
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assign sum_stage1_0 = mult_result[0] + mult_result[1] + mult_result[2] + mult_result[3] +
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mult_result[4] + mult_result[5] + mult_result[6] + mult_result[7];
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assign sum_stage1_1 = mult_result[8] + mult_result[9] + mult_result[10] + mult_result[11] +
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mult_result[12] + mult_result[13] + mult_result[14] + mult_result[15];
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assign sum_stage1_2 = mult_result[16] + mult_result[17] + mult_result[18] + mult_result[19] +
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mult_result[20] + mult_result[21] + mult_result[22] + mult_result[23];
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assign sum_stage1_3 = mult_result[24] + mult_result[25] + mult_result[26] + mult_result[27] +
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mult_result[28] + mult_result[29] + mult_result[30] + mult_result[31];
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// Stage 2: Combine groups of 2
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assign sum_stage2_0 = sum_stage1_0 + sum_stage1_1;
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assign sum_stage2_1 = sum_stage1_2 + sum_stage1_3;
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// Stage 3: Final sum
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assign sum_stage3 = sum_stage2_0 + sum_stage2_1;
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integer i;
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// SINGLE-CYCLE PIPELINE PROCESSING
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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// Reset delay line
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for (i = 0; i < TAPS; i = i + 1) begin
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delay_line[i] <= 0;
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end
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accumulator_reg <= 0;
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data_out <= 0;
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data_out_valid <= 0;
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end else begin
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// Always shift in new data when valid
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if (data_valid) begin
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// Shift delay line
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for (i = TAPS-1; i > 0; i = i - 1) begin
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delay_line[i] <= delay_line[i-1];
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end
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delay_line[0] <= data_in;
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// Register the combinatorial sum
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accumulator_reg <= sum_stage3;
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// Output with 1-cycle latency
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data_out_valid <= 1'b1;
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end else begin
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data_out_valid <= 1'b0;
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end
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// Output saturation logic (registered)
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if (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) begin
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data_out <= (2**(DATA_WIDTH-1))-1;
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end else if (accumulator_reg < -(2**(ACCUM_WIDTH-2))) begin
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data_out <= -(2**(DATA_WIDTH-1));
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end else begin
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// Round and truncate (keep middle bits)
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data_out <= accumulator_reg[ACCUM_WIDTH-2:DATA_WIDTH-1];
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end
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end
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end
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// Always ready to accept new data
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assign fir_ready = 1'b1;
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// Overflow detection (simplified)
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assign filter_overflow = (accumulator_reg > (2**(ACCUM_WIDTH-2)-1)) ||
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(accumulator_reg < -(2**(ACCUM_WIDTH-2)));
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endmodule |