Jason
1acedf494c
Production FPGA: Artix-7 XC7A200T-2FBG484I (33,650 slices, 740 DSP48E1, 365 BRAM, -2 speed grade). Pin-mapped across 6 banks with proper VCCO assignment (3.3V/2.5V/1.8V). RTL timing primitives added for clean timing closure: - ad9484_interface_400m.v: BUFIO for IDDR capture at 400MHz DDR, BUFG for fabric logic, reset synchronizer (P1-7) - dac_interface_single.v: ODDR for dac_clk forwarding + dac_data[7:0] output registration, eliminates clock-forwarding insertion delay - usb_data_interface.v: ODDR for ft601_clk_out forwarding, FSM runs on ft601_clk_in domain with CDC synchronizers Constraints: - New production XDC (xc7a200t_fbg484.xdc): 182 pins, generated clocks for ODDR outputs, BUFIO/DDR input delays, fixed false_path strategy (from reset source, not to CLR pins), IOB packing on cells not ports - Preserved upstream XDC as xc7a50t_ftg256.xdc for reference - Updated cntrt.xdc with DRC fixes (I/O standards, missing constraints)
81 lines
2.5 KiB
Verilog
81 lines
2.5 KiB
Verilog
module dac_interface_enhanced (
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input wire clk_120m,
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input wire reset_n,
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input wire [7:0] chirp_data,
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input wire chirp_valid,
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output wire [7:0] dac_data,
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output wire dac_clk,
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output wire dac_sleep
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);
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// ============================================================================
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// DAC data register (fabric FF — feeds ODDR D1/D2 inputs)
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// ============================================================================
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reg [7:0] dac_data_reg;
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always @(posedge clk_120m or negedge reset_n) begin
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if (!reset_n) begin
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dac_data_reg <= 8'd128; // Center value
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end else if (chirp_valid) begin
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dac_data_reg <= chirp_data;
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end else begin
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dac_data_reg <= 8'd128; // Default to center when no chirp
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end
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end
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`ifndef SIMULATION
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// ============================================================================
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// ODDR for dac_clk forwarding (Xilinx 7-series)
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// D1=1, D2=0 produces a clock replica aligned to clk_120m rising edge.
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// The ODDR is placed in the IOB, giving near-zero skew between the
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// forwarded clock and ODDR data outputs in the same bank.
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// ============================================================================
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ODDR #(
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.DDR_CLK_EDGE("OPPOSITE_EDGE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) oddr_dac_clk (
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.Q(dac_clk),
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.C(clk_120m),
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.CE(1'b1),
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.D1(1'b1),
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.D2(1'b0),
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.R(1'b0),
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.S(1'b0)
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);
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// ============================================================================
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// ODDR for dac_data[7:0] — packs output FFs into IOBs
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// D1=D2=same value → SDR behavior through ODDR, but placed in IOB.
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// This eliminates fabric routing delay to the output pad.
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// ============================================================================
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genvar i;
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generate
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for (i = 0; i < 8; i = i + 1) begin : oddr_dac_data_gen
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ODDR #(
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.DDR_CLK_EDGE("OPPOSITE_EDGE"),
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.INIT(1'b0),
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.SRTYPE("SYNC")
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) oddr_dac_data (
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.Q(dac_data[i]),
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.C(clk_120m),
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.CE(1'b1),
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.D1(dac_data_reg[i]),
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.D2(dac_data_reg[i]),
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.R(1'b0),
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.S(1'b0)
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);
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end
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endgenerate
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`else
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// ============================================================================
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// Simulation behavioral equivalent
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// ============================================================================
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assign dac_clk = clk_120m;
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assign dac_data = dac_data_reg;
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`endif
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assign dac_sleep = 1'b0;
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endmodule |