NawfalMotii79
135 lines
4.3 KiB
Verilog
135 lines
4.3 KiB
Verilog
`timescale 1ns / 1ps
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/**
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* usb_packet_analyzer.v
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*
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* Analyzes USB packet format from FT601 interface
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* Verifies header/footer and data integrity
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*/
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module usb_packet_analyzer (
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input wire clk,
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input wire reset_n,
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input wire [31:0] usb_data,
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input wire usb_wr_strobe,
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output reg packet_valid,
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output reg [7:0] packet_type,
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output reg [31:0] packet_data,
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output reg [31:0] error_count
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);
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// Packet structure
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localparam HEADER = 8'hAA;
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localparam FOOTER = 8'h55;
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localparam HEADER_POS = 24; // Header in bits [31:24]
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// States
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typedef enum {
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ST_IDLE,
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ST_HEADER,
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ST_RANGE,
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ST_DOPPLER,
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ST_DETECTION,
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ST_FOOTER
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} state_t;
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state_t current_state, next_state;
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reg [7:0] byte_count;
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reg [31:0] error_reg;
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reg [31:0] packet_count;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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current_state <= ST_IDLE;
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byte_count <= 8'd0;
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error_reg <= 32'd0;
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packet_count <= 32'd0;
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packet_valid <= 1'b0;
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packet_type <= 8'd0;
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packet_data <= 32'd0;
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end else begin
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packet_valid <= 1'b0;
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case (current_state)
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ST_IDLE: begin
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if (usb_wr_strobe && usb_data[31:24] == HEADER) begin
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current_state <= ST_HEADER;
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packet_count <= packet_count + 1;
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$display("[USB_ANALYZER] Packet %0d started at time %0t",
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packet_count + 1, $time);
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end
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end
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ST_HEADER: begin
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if (usb_wr_strobe) begin
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current_state <= ST_RANGE;
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byte_count <= 8'd0;
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end
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end
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ST_RANGE: begin
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if (usb_wr_strobe) begin
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if (byte_count == 8'd0) begin
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packet_data[31:24] <= usb_data[7:0];
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byte_count <= 8'd1;
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end else if (byte_count == 8'd1) begin
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packet_data[23:16] <= usb_data[7:0];
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byte_count <= 8'd2;
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end else if (byte_count == 8'd2) begin
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packet_data[15:8] <= usb_data[7:0];
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byte_count <= 8'd3;
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end else if (byte_count == 8'd3) begin
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packet_data[7:0] <= usb_data[7:0];
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current_state <= ST_DOPPLER;
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byte_count <= 8'd0;
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$display("[USB_ANALYZER] Range data: 0x%08h", packet_data);
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end
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end
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end
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ST_DOPPLER: begin
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if (usb_wr_strobe) begin
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if (byte_count == 8'd0) begin
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packet_data[31:16] <= usb_data[31:16]; // Doppler real
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byte_count <= 8'd1;
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end else if (byte_count == 8'd1) begin
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packet_data[15:0] <= usb_data[31:16]; // Doppler imag
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current_state <= ST_DETECTION;
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byte_count <= 8'd0;
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$display("[USB_ANALYZER] Doppler data: real=0x%04h, imag=0x%04h",
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packet_data[31:16], packet_data[15:0]);
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end
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end
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end
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ST_DETECTION: begin
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if (usb_wr_strobe) begin
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packet_type <= usb_data[0];
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current_state <= ST_FOOTER;
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$display("[USB_ANALYZER] Detection: %b", usb_data[0]);
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end
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end
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ST_FOOTER: begin
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if (usb_wr_strobe) begin
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if (usb_data[7:0] == FOOTER) begin
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packet_valid <= 1'b1;
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$display("[USB_ANALYZER] Packet %0d valid, footer OK", packet_count);
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end else begin
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error_reg <= error_reg + 1;
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$error("[USB_ANALYZER] Invalid footer: expected 0x55, got 0x%02h",
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usb_data[7:0]);
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end
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current_state <= ST_IDLE;
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end
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end
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default: current_state <= ST_IDLE;
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endcase
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end
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end
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assign error_count = error_reg;
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endmodule
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