Jason
0537b40dcc
Three-tier test orchestrator validates opcode maps, bit widths, packet layouts, and round-trip correctness across FPGA RTL, Python GUI, and STM32 firmware. Catches 3 real bugs: - status_words[0] 37-bit truncation in both USB interfaces - Python radar_mode readback at wrong bit position (bit 21 vs 24) - RadarSettings.cpp buffer overread (min check 74 vs required 82) 29 tests: 24 pass, 5 xfail (documenting confirmed bugs). 4th CI job added: cross-layer-tests (Python + iverilog + cc).
13 lines
163 B
Plaintext
13 lines
163 B
Plaintext
# Simulation outputs (generated by iverilog TB)
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cmd_results.txt
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data_packet.txt
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status_packet.txt
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*.vcd
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*.vvp
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# Compiled C stub
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stm32_stub
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# Python
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__pycache__/
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