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75854a39cab20857146496c12fb21107f3ca453e
PLFM_RADAR/9_Firmware/9_2_FPGA
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Jason 75854a39ca docs: update constraints README with USB_MODE architecture and build guide 
Add USB Interface Architecture section documenting the USB_MODE parameter,
generate block mechanism, per-target wrapper pattern, FT2232H pin map, and
build quick-reference. Update top modules table (50T now uses
radar_system_top_50t), bank voltage tables, and signal differences to
reflect the FT2232H/FT601 dual-interface design.
2026-04-07 21:34:38 +03:00
..
constraints
docs: update constraints README with USB_MODE architecture and build guide
2026-04-07 21:34:38 +03:00
formal
fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT (follow-up to PR #33)
2026-04-06 23:15:50 +03:00
scripts
feat(usb): add FT2232H USB 2.0 interface for 50T production board
2026-04-07 19:22:16 +03:00
tb
feat(usb): add FT2232H USB 2.0 interface for 50T production board
2026-04-07 19:22:16 +03:00
.gitignore
CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
2026-03-19 11:31:46 +02:00
ad9484_interface_400m.v
fix(rtl,constraints): change IBUFDS to IOSTANDARD DEFAULT for multi-target bank voltage compatibility
2026-04-07 05:17:11 +03:00
adc_clk_mmcm_integration.md
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
adc_clk_mmcm.v
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
cdc_modules.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
cfar_ca.v
Pipeline CFAR noise computation: break critical path for timing closure
2026-03-20 05:24:08 +02:00
chirp_memory_loader_param.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
cic_decimator_4x_enhanced.v
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
dac_interface_single.v
Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I
2026-03-16 22:24:22 +02:00
ddc_400m.v
feat(usb): add FT2232H USB 2.0 interface for 50T production board
2026-04-07 19:22:16 +03:00
ddc_input_interface.v
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
2026-03-16 18:14:06 +02:00
doppler_processor.v
Fix staggered-PRF Doppler processing with dual 16-point FFTs
2026-03-27 23:05:28 +02:00
edge_detector.v
Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator
2026-03-17 13:48:47 +02:00
fft_engine.v
FFT engine: merge SHIFT into WRITE (5→4 cycle butterfly, 20% throughput) + barrel-shift twiddle index
2026-03-20 00:20:59 +02:00
fft_twiddle_16.mem
Fix staggered-PRF Doppler processing with dual 16-point FFTs
2026-03-27 23:05:28 +02:00
fft_twiddle_1024.mem
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
fir_lowpass.v
fix(rtl): force FIR adder tree to fabric to free 30 DSPs for FFT butterfly on 50T
2026-04-07 14:45:47 +03:00
fpga_self_test.v
Add radar dashboard GUI with replay mode for real ADI CN0566 data visualization, FPGA self-test module, and co-sim npy arrays
2026-03-20 19:02:06 +02:00
frequency_matched_filter.v
Convert async→sync reset on DSP/BRAM datapath registers for timing closure
2026-03-17 20:11:13 +02:00
latency_buffer.v
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
2026-03-18 01:28:42 +02:00
long_chirp_lut.mem
Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)
2026-03-19 10:31:16 +02:00
long_chirp_seg0_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg0_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg1_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg1_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg2_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg2_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg3_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg3_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
matched_filter_multi_segment.v
Fix matched filter synth errors: overlap_copy_count part-select width, add FSM default
2026-03-19 20:53:29 +02:00
matched_filter_processing_chain.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
mti_canceller.v
Integrate MTI canceller and DC notch filter for ground clutter removal
2026-03-20 16:39:17 +02:00
nco_400m_enhanced.v
Improve timing margins with targeted datapath register tuning
2026-03-17 23:51:04 +02:00
plfm_chirp_controller.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
radar_mode_controller.v
Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)
2026-03-19 23:54:48 +02:00
radar_receiver_final.v
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00
radar_system_top_50t.v
feat(usb): add FT2232H USB 2.0 interface for 50T production board
2026-04-07 19:22:16 +03:00
radar_system_top_te0712_dev.v
Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
2026-03-18 03:57:26 +02:00
radar_system_top_te0713_dev.v
Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments
2026-03-19 16:47:59 +02:00
radar_system_top_te0713_umft601x_dev.v
add TE0713+UMFT601X-B FT601 integration dev bitstream (timing clean)
2026-03-21 20:43:52 +02:00
radar_system_top.v
feat(usb): add FT2232H USB 2.0 interface for 50T production board
2026-04-07 19:22:16 +03:00
radar_transmitter.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
range_bin_decimator.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
run_regression.sh
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00
rx_gain_control.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
short_chirp_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
short_chirp_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
usb_data_interface_ft2232h.v
fix: add explicit reset for status_words to suppress Synth 8-7137 warning
2026-04-07 19:35:43 +03:00
usb_data_interface.v
Wire self-test results (0x31) to USB status readback path, add fpga_self_test to regression
2026-03-20 20:03:11 +02:00
xfft_16.v
fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide
2026-04-07 02:51:48 +03:00