NawfalMotii79
158 lines
4.2 KiB
Verilog
158 lines
4.2 KiB
Verilog
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 19:04:35 12/14/2025
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// Design Name:
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// Module Name: radar_transmitter
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module radar_transmitter(
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// System Clocks
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input wire clk_100m, // System clock
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input wire clk_120m_dac, // 120MHz DAC clock
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input wire reset_n,
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// DAC Interface
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output wire [7:0] dac_data,
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output wire dac_clk,
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output wire dac_sleep,
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output wire rx_mixer_en,
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output wire tx_mixer_en,
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// STM32 Control Interface
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input wire stm32_new_chirp,
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input wire stm32_new_elevation,
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input wire stm32_new_azimuth,
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input wire stm32_mixers_enable,
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output wire fpga_rf_switch,
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// ADAR1000 Control Interface
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output wire adar_tx_load_1,
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output wire adar_rx_load_1,
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output wire adar_tx_load_2,
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output wire adar_rx_load_2,
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output wire adar_tx_load_3,
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output wire adar_rx_load_3,
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output wire adar_tx_load_4,
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output wire adar_rx_load_4,
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output wire adar_tr_1,
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output wire adar_tr_2,
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output wire adar_tr_3,
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output wire adar_tr_4,
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// Level Shifter SPI Interface (STM32F7 to ADAR1000)
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input wire stm32_sclk_3v3,
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input wire stm32_mosi_3v3,
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output wire stm32_miso_3v3,
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input wire stm32_cs_adar1_3v3,
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input wire stm32_cs_adar2_3v3,
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input wire stm32_cs_adar3_3v3,
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input wire stm32_cs_adar4_3v3,
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output wire stm32_sclk_1v8,
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output wire stm32_mosi_1v8,
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input wire stm32_miso_1v8,
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output wire stm32_cs_adar1_1v8,
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output wire stm32_cs_adar2_1v8,
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output wire stm32_cs_adar3_1v8,
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output wire stm32_cs_adar4_1v8,
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// Beam Position Tracking
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output wire [5:0] current_elevation,
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output wire [5:0] current_azimuth,
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output wire [5:0] current_chirp,
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output wire new_chirp_frame
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);
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// Edge Detection Signals
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wire new_chirp_pulse;
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wire new_elevation_pulse;
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wire new_azimuth_pulse;
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// Chirp Control Signals
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wire [7:0] chirp_data;
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wire chirp_valid;
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wire chirp_sequence_done;
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// Enhanced STM32 Input Edge Detection with Debouncing
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edge_detector_enhanced chirp_edge (
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.clk(clk_100m),
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.reset_n(reset_n),
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.signal_in(stm32_new_chirp),
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.rising_falling_edge(new_chirp_pulse)
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);
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edge_detector_enhanced elevation_edge (
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.clk(clk_100m),
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.reset_n(reset_n),
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.signal_in(stm32_new_elevation),
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.rising_falling_edge(new_elevation_pulse)
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);
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edge_detector_enhanced azimuth_edge (
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.clk(clk_100m),
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.reset_n(reset_n),
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.signal_in(stm32_new_azimuth),
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.rising_falling_edge(new_azimuth_pulse)
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);
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// Enhanced PLFM Chirp Generation
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plfm_chirp_controller_enhanced plfm_chirp_inst (
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.clk_120m(clk_120m_dac),
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.clk_100m(clk_100m),
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.reset_n(reset_n),
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.new_chirp(new_chirp_pulse),
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.new_elevation(new_elevation_pulse),
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.new_azimuth(new_azimuth_pulse),
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.new_chirp_frame(new_chirp_frame),
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.mixers_enable(stm32_mixers_enable),
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.chirp_data(chirp_data),
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.chirp_valid(chirp_valid),
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.chirp_done(chirp_sequence_done),
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.rf_switch_ctrl(fpga_rf_switch),
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.rx_mixer_en(rx_mixer_en),
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.tx_mixer_en(tx_mixer_en),
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.adar_tx_load_1(adar_tx_load_1),
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.adar_rx_load_1(adar_rx_load_1),
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.adar_tx_load_2(adar_tx_load_2),
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.adar_rx_load_2(adar_rx_load_2),
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.adar_tx_load_3(adar_tx_load_3),
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.adar_rx_load_3(adar_rx_load_3),
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.adar_tx_load_4(adar_tx_load_4),
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.adar_rx_load_4(adar_rx_load_4),
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.adar_tr_1(adar_tr_1),
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.adar_tr_2(adar_tr_2),
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.adar_tr_3(adar_tr_3),
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.adar_tr_4(adar_tr_4),
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.elevation_counter(current_elevation),
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.azimuth_counter(current_azimuth),
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.chirp_counter(current_chirp)
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);
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// Enhanced DAC Interface
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dac_interface_enhanced dac_interface_inst (
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.clk_120m(clk_120m_dac),
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.reset_n(reset_n),
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.chirp_data(chirp_data),
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.chirp_valid(chirp_valid),
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.dac_data(dac_data),
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.dac_clk(dac_clk),
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.dac_sleep(dac_sleep)
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);
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endmodule
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