Jason
537 lines
21 KiB
Verilog
537 lines
21 KiB
Verilog
`timescale 1ns / 1ps
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// ============================================================================
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// doppler_processor.v — Staggered-PRF Doppler Processor (CORRECTED)
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// ============================================================================
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//
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// ARCHITECTURE:
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// This module implements dual 16-point FFTs for the AERIS-10 staggered-PRF
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// waveform. The radar transmits 16 long-PRI chirps followed by 16 short-PRI
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// chirps per frame (32 total). Rather than a single 32-point FFT over the
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// non-uniformly sampled frame (which is signal-processing invalid), this
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// module processes each sub-frame independently:
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//
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// Sub-frame 0 (long PRI): chirps 0..15 → 16-pt windowed FFT
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// Sub-frame 1 (short PRI): chirps 16..31 → 16-pt windowed FFT
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//
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// Each sub-frame produces 16 Doppler bins per range bin. The outputs are
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// tagged with a sub_frame bit and the 4-bit bin index is packed into the
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// existing 5-bit doppler_bin port as {sub_frame, bin[3:0]}.
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//
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// This architecture enables downstream staggered-PRF ambiguity resolution:
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// the same target velocity maps to DIFFERENT Doppler bins at different PRIs,
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// and comparing the two sub-frame results resolves velocity ambiguity.
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//
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// INTERFACE COMPATIBILITY:
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// The port list is a superset of the original module. Existing instantiations
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// that don't connect `sub_frame` will still work. The FORMAL ports are
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// retained. CHIRPS_PER_FRAME must be 32 (16 per sub-frame).
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//
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// WINDOW:
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// 16-point Hamming window (Q15), symmetric. Computed as:
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// w[n] = 0.54 - 0.46 * cos(2*pi*n/15), n=0..15
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// ============================================================================
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module doppler_processor_optimized #(
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parameter DOPPLER_FFT_SIZE = 16, // FFT size per sub-frame (was 32)
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parameter RANGE_BINS = 64,
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parameter CHIRPS_PER_FRAME = 32, // Total chirps in frame (16+16)
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parameter CHIRPS_PER_SUBFRAME = 16, // Chirps per sub-frame
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parameter WINDOW_TYPE = 0, // 0=Hamming, 1=Rectangular
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parameter DATA_WIDTH = 16
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)(
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input wire clk,
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input wire reset_n,
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input wire [31:0] range_data,
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input wire data_valid,
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input wire new_chirp_frame,
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output reg [31:0] doppler_output,
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output reg doppler_valid,
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output reg [4:0] doppler_bin, // {sub_frame, bin[3:0]}
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output reg [5:0] range_bin,
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output reg sub_frame, // 0=long PRI, 1=short PRI
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output wire processing_active,
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output wire frame_complete,
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output reg [3:0] status
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`ifdef FORMAL
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,
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output wire [2:0] fv_state,
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output wire [10:0] fv_mem_write_addr,
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output wire [10:0] fv_mem_read_addr,
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output wire [5:0] fv_write_range_bin,
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output wire [4:0] fv_write_chirp_index,
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output wire [5:0] fv_read_range_bin,
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output wire [4:0] fv_read_doppler_index,
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output wire [9:0] fv_processing_timeout,
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output wire fv_frame_buffer_full,
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output wire fv_mem_we,
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output wire [10:0] fv_mem_waddr_r
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`endif
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);
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// ==============================================
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// Window Coefficients — 16-point Hamming (Q15)
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// ==============================================
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// w[n] = 0.54 - 0.46 * cos(2*pi*n/15), n=0..15
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// Symmetric: w[n] = w[15-n]
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reg [DATA_WIDTH-1:0] window_coeff [0:15];
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integer w;
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initial begin
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if (WINDOW_TYPE == 0) begin
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// 16-point Hamming window, Q15 format
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// Computed: round(32767 * (0.54 - 0.46*cos(2*pi*n/15)))
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window_coeff[0] = 16'h0A3D; // 0.0800 * 32767 = 2621
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window_coeff[1] = 16'h0E5C; // 0.1116 * 32767 = 3676
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window_coeff[2] = 16'h1B6D; // 0.2138 * 32767 = 7021
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window_coeff[3] = 16'h3088; // 0.3790 * 32767 = 12424
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window_coeff[4] = 16'h4B33; // 0.5868 * 32767 = 19251
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window_coeff[5] = 16'h6573; // 0.7930 * 32767 = 25971
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window_coeff[6] = 16'h7642; // 0.9245 * 32767 = 30274
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window_coeff[7] = 16'h7F62; // 0.9932 * 32767 = 32610
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window_coeff[8] = 16'h7F62; // symmetric
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window_coeff[9] = 16'h7642;
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window_coeff[10] = 16'h6573;
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window_coeff[11] = 16'h4B33;
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window_coeff[12] = 16'h3088;
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window_coeff[13] = 16'h1B6D;
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window_coeff[14] = 16'h0E5C;
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window_coeff[15] = 16'h0A3D;
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end else begin
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for (w = 0; w < 16; w = w + 1) begin
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window_coeff[w] = 16'h7FFF;
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end
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end
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end
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// ==============================================
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// Memory Declaration - FIXED SIZE
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// ==============================================
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localparam MEM_DEPTH = RANGE_BINS * CHIRPS_PER_FRAME;
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] doppler_i_mem [0:MEM_DEPTH-1];
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] doppler_q_mem [0:MEM_DEPTH-1];
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// ==============================================
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// Control Registers
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// ==============================================
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reg [5:0] write_range_bin;
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reg [4:0] write_chirp_index;
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reg [5:0] read_range_bin;
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reg [4:0] read_doppler_index;
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reg frame_buffer_full;
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reg [9:0] chirps_received;
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reg [1:0] chirp_state;
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// Sub-frame tracking
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reg current_sub_frame; // 0=processing long, 1=processing short
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// ==============================================
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// FFT Interface
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// ==============================================
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reg fft_start;
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wire fft_ready;
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reg [DATA_WIDTH-1:0] fft_input_i;
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reg [DATA_WIDTH-1:0] fft_input_q;
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reg signed [31:0] mult_i, mult_q;
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reg signed [DATA_WIDTH-1:0] window_val_reg;
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reg signed [31:0] mult_i_raw, mult_q_raw;
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reg fft_input_valid;
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reg fft_input_last;
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wire [DATA_WIDTH-1:0] fft_output_i;
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wire [DATA_WIDTH-1:0] fft_output_q;
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wire fft_output_valid;
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wire fft_output_last;
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// ==============================================
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// Addressing
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// ==============================================
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wire [10:0] mem_write_addr;
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wire [10:0] mem_read_addr;
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assign mem_write_addr = (write_chirp_index * RANGE_BINS) + write_range_bin;
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assign mem_read_addr = (read_doppler_index * RANGE_BINS) + read_range_bin;
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// ==============================================
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// State Machine
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// ==============================================
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reg [2:0] state;
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localparam S_IDLE = 3'b000;
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localparam S_ACCUMULATE = 3'b001;
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localparam S_PRE_READ = 3'b101;
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localparam S_LOAD_FFT = 3'b010;
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localparam S_FFT_WAIT = 3'b011;
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localparam S_OUTPUT = 3'b100;
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// Frame sync detection
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reg new_chirp_frame_d1;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) new_chirp_frame_d1 <= 0;
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else new_chirp_frame_d1 <= new_chirp_frame;
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end
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wire frame_start_pulse = new_chirp_frame & ~new_chirp_frame_d1;
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// ==============================================
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// Main State Machine
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// ==============================================
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reg [4:0] fft_sample_counter; // Reduced: only need 0..17 for 16-pt FFT
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reg [9:0] processing_timeout;
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// Memory write enable and data signals
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reg mem_we;
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reg [10:0] mem_waddr_r;
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reg [DATA_WIDTH-1:0] mem_wdata_i, mem_wdata_q;
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// Memory read data
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reg [DATA_WIDTH-1:0] mem_rdata_i, mem_rdata_q;
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`ifdef FORMAL
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assign fv_state = state;
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assign fv_mem_write_addr = mem_write_addr;
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assign fv_mem_read_addr = mem_read_addr;
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assign fv_write_range_bin = write_range_bin;
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assign fv_write_chirp_index = write_chirp_index;
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assign fv_read_range_bin = read_range_bin;
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assign fv_read_doppler_index = read_doppler_index;
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assign fv_processing_timeout = processing_timeout;
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assign fv_frame_buffer_full = frame_buffer_full;
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assign fv_mem_we = mem_we;
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assign fv_mem_waddr_r = mem_waddr_r;
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`endif
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// ----------------------------------------------------------
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// Separate always block for memory writes — NO async reset
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// ----------------------------------------------------------
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always @(posedge clk) begin
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if (mem_we) begin
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doppler_i_mem[mem_waddr_r] <= mem_wdata_i;
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doppler_q_mem[mem_waddr_r] <= mem_wdata_q;
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end
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mem_rdata_i <= doppler_i_mem[mem_read_addr];
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mem_rdata_q <= doppler_q_mem[mem_read_addr];
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end
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// ----------------------------------------------------------
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// Block 1: FSM / Control — async reset
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// ----------------------------------------------------------
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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state <= S_IDLE;
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write_range_bin <= 0;
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write_chirp_index <= 0;
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frame_buffer_full <= 0;
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doppler_valid <= 0;
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fft_start <= 0;
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fft_input_valid <= 0;
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fft_input_last <= 0;
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fft_sample_counter <= 0;
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processing_timeout <= 0;
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status <= 0;
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chirps_received <= 0;
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chirp_state <= 0;
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doppler_output <= 0;
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doppler_bin <= 0;
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range_bin <= 0;
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sub_frame <= 0;
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current_sub_frame <= 0;
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end else begin
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doppler_valid <= 0;
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fft_input_valid <= 0;
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fft_input_last <= 0;
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if (processing_timeout > 0) begin
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processing_timeout <= processing_timeout - 1;
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end
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case (state)
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S_IDLE: begin
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if (frame_start_pulse) begin
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write_chirp_index <= 0;
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write_range_bin <= 0;
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frame_buffer_full <= 0;
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chirps_received <= 0;
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end
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if (data_valid && !frame_buffer_full) begin
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state <= S_ACCUMULATE;
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write_range_bin <= 1;
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end
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end
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S_ACCUMULATE: begin
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if (data_valid) begin
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if (write_range_bin < RANGE_BINS - 1) begin
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write_range_bin <= write_range_bin + 1;
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end else begin
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write_range_bin <= 0;
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write_chirp_index <= write_chirp_index + 1;
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chirps_received <= chirps_received + 1;
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if (write_chirp_index >= CHIRPS_PER_FRAME - 1) begin
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frame_buffer_full <= 1;
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chirp_state <= 0;
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state <= S_PRE_READ;
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fft_sample_counter <= 0;
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write_chirp_index <= 0;
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write_range_bin <= 0;
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// Start with sub-frame 0 (long PRI chirps 0..15)
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current_sub_frame <= 0;
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end
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end
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end
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end
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S_PRE_READ: begin
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// Prime BRAM pipeline for current sub-frame
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// read_doppler_index already set in Block 2 to sub-frame base
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fft_start <= 1;
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state <= S_LOAD_FFT;
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end
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S_LOAD_FFT: begin
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fft_start <= 0;
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// Pipeline: 2 priming cycles + CHIRPS_PER_SUBFRAME data cycles
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if (fft_sample_counter <= 1) begin
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fft_sample_counter <= fft_sample_counter + 1;
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end else if (fft_sample_counter <= CHIRPS_PER_SUBFRAME + 1) begin
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fft_input_valid <= 1;
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if (fft_sample_counter == CHIRPS_PER_SUBFRAME + 1) begin
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fft_input_last <= 1;
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state <= S_FFT_WAIT;
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fft_sample_counter <= 0;
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processing_timeout <= 1000;
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end else begin
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fft_sample_counter <= fft_sample_counter + 1;
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end
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end
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end
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S_FFT_WAIT: begin
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if (fft_output_valid) begin
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doppler_output <= {fft_output_q[15:0], fft_output_i[15:0]};
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// Pack: {sub_frame, bin[3:0]}
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doppler_bin <= {current_sub_frame, fft_sample_counter[3:0]};
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range_bin <= read_range_bin;
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sub_frame <= current_sub_frame;
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doppler_valid <= 1;
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fft_sample_counter <= fft_sample_counter + 1;
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if (fft_output_last) begin
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state <= S_OUTPUT;
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fft_sample_counter <= 0;
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end
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end
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if (processing_timeout == 0) begin
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state <= S_OUTPUT;
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end
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end
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S_OUTPUT: begin
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if (current_sub_frame == 0) begin
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// Just finished long PRI sub-frame — now do short PRI
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current_sub_frame <= 1;
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fft_sample_counter <= 0;
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state <= S_PRE_READ;
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// read_range_bin stays the same, read_doppler_index
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// will be set to CHIRPS_PER_SUBFRAME in Block 2
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end else begin
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// Finished both sub-frames for this range bin
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current_sub_frame <= 0;
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if (read_range_bin < RANGE_BINS - 1) begin
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fft_sample_counter <= 0;
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state <= S_PRE_READ;
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// read_range_bin incremented in Block 2
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end else begin
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state <= S_IDLE;
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frame_buffer_full <= 0;
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end
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end
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end
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endcase
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status <= {state, frame_buffer_full};
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end
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end
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// ----------------------------------------------------------
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// Block 2: BRAM address/data & DSP datapath — synchronous reset
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// ----------------------------------------------------------
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always @(posedge clk) begin
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if (!reset_n) begin
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mem_we <= 0;
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mem_waddr_r <= 0;
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mem_wdata_i <= 0;
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mem_wdata_q <= 0;
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mult_i <= 0;
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mult_q <= 0;
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mult_i_raw <= 0;
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mult_q_raw <= 0;
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window_val_reg <= 0;
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fft_input_i <= 0;
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fft_input_q <= 0;
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read_range_bin <= 0;
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read_doppler_index <= 0;
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end else begin
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mem_we <= 0;
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case (state)
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S_IDLE: begin
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if (data_valid && !frame_buffer_full) begin
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mem_we <= 1;
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mem_waddr_r <= mem_write_addr;
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mem_wdata_i <= range_data[15:0];
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mem_wdata_q <= range_data[31:16];
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end
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end
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S_ACCUMULATE: begin
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if (data_valid) begin
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mem_we <= 1;
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mem_waddr_r <= mem_write_addr;
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mem_wdata_i <= range_data[15:0];
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mem_wdata_q <= range_data[31:16];
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if (write_range_bin >= RANGE_BINS - 1 &&
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write_chirp_index >= CHIRPS_PER_FRAME - 1) begin
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read_range_bin <= 0;
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// Start reading from chirp 0 (long PRI sub-frame)
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read_doppler_index <= 0;
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end
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end
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end
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S_PRE_READ: begin
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// Set read_doppler_index to first chirp of current sub-frame + 1
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// (because address is presented this cycle, data arrives next)
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if (current_sub_frame == 0)
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read_doppler_index <= 1; // Long PRI: chirps 0..15
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else
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read_doppler_index <= CHIRPS_PER_SUBFRAME + 1; // Short PRI: chirps 16..31
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// BREG priming: window coeff for sample 0
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window_val_reg <= $signed(window_coeff[0]);
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end
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S_LOAD_FFT: begin
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if (fft_sample_counter == 0) begin
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// Pipe stage 1: multiply using pre-registered BREG value
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mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
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mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
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window_val_reg <= $signed(window_coeff[1]);
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// Advance to chirp base+2
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if (current_sub_frame == 0)
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read_doppler_index <= (2 < CHIRPS_PER_SUBFRAME) ? 2
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: CHIRPS_PER_SUBFRAME - 1;
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else
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read_doppler_index <= (CHIRPS_PER_SUBFRAME + 2 < CHIRPS_PER_FRAME)
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? CHIRPS_PER_SUBFRAME + 2
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: CHIRPS_PER_FRAME - 1;
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end else if (fft_sample_counter == 1) begin
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mult_i <= mult_i_raw;
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mult_q <= mult_q_raw;
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mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
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mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
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if (2 < CHIRPS_PER_SUBFRAME)
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window_val_reg <= $signed(window_coeff[2]);
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// Advance to chirp base+3
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begin : advance_chirp3
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reg [4:0] next_chirp;
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next_chirp = (current_sub_frame == 0) ? 3 : CHIRPS_PER_SUBFRAME + 3;
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if (next_chirp < CHIRPS_PER_FRAME)
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read_doppler_index <= next_chirp;
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else
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read_doppler_index <= CHIRPS_PER_FRAME - 1;
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end
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end else if (fft_sample_counter <= CHIRPS_PER_SUBFRAME + 1) begin
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// Steady state
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fft_input_i <= (mult_i + (1 << 14)) >>> 15;
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fft_input_q <= (mult_q + (1 << 14)) >>> 15;
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mult_i <= mult_i_raw;
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mult_q <= mult_q_raw;
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if (fft_sample_counter <= CHIRPS_PER_SUBFRAME - 1) begin
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mult_i_raw <= $signed(mem_rdata_i) * window_val_reg;
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mult_q_raw <= $signed(mem_rdata_q) * window_val_reg;
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// Window coeff index within sub-frame
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begin : advance_window
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reg [4:0] win_idx;
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win_idx = fft_sample_counter[3:0] + 1;
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if (win_idx < CHIRPS_PER_SUBFRAME)
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window_val_reg <= $signed(window_coeff[win_idx]);
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|
end
|
|
// Advance BRAM read
|
|
begin : advance_bram
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reg [4:0] chirp_offset;
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|
reg [4:0] chirp_base;
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|
chirp_offset = fft_sample_counter[3:0] + 2;
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|
chirp_base = (current_sub_frame == 0) ? 0 : CHIRPS_PER_SUBFRAME;
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|
if (chirp_base + chirp_offset < CHIRPS_PER_FRAME)
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|
read_doppler_index <= chirp_base + chirp_offset;
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else
|
|
read_doppler_index <= CHIRPS_PER_FRAME - 1;
|
|
end
|
|
end
|
|
|
|
if (fft_sample_counter == CHIRPS_PER_SUBFRAME + 1) begin
|
|
// Reset read index for potential next operation
|
|
if (current_sub_frame == 0)
|
|
read_doppler_index <= CHIRPS_PER_SUBFRAME; // Ready for short sub-frame
|
|
else
|
|
read_doppler_index <= 0;
|
|
end
|
|
end
|
|
end
|
|
|
|
S_OUTPUT: begin
|
|
if (current_sub_frame == 0) begin
|
|
// Transitioning to short PRI sub-frame
|
|
// Set read_doppler_index to start of short sub-frame
|
|
read_doppler_index <= CHIRPS_PER_SUBFRAME;
|
|
end else begin
|
|
// Both sub-frames done
|
|
if (read_range_bin < RANGE_BINS - 1) begin
|
|
read_range_bin <= read_range_bin + 1;
|
|
read_doppler_index <= 0; // Next range bin starts with long sub-frame
|
|
end
|
|
end
|
|
end
|
|
|
|
default: begin
|
|
// S_FFT_WAIT: no BRAM-write or address operations needed
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// ==============================================
|
|
// FFT Module — 16-point
|
|
// ==============================================
|
|
xfft_16 fft_inst (
|
|
.aclk(clk),
|
|
.aresetn(reset_n),
|
|
.s_axis_config_tdata(8'h01),
|
|
.s_axis_config_tvalid(fft_start),
|
|
.s_axis_config_tready(fft_ready),
|
|
.s_axis_data_tdata({fft_input_q, fft_input_i}),
|
|
.s_axis_data_tvalid(fft_input_valid),
|
|
.s_axis_data_tlast(fft_input_last),
|
|
.m_axis_data_tdata({fft_output_q, fft_output_i}),
|
|
.m_axis_data_tvalid(fft_output_valid),
|
|
.m_axis_data_tlast(fft_output_last),
|
|
.m_axis_data_tready(1'b1)
|
|
);
|
|
|
|
// ==============================================
|
|
// Status Outputs
|
|
// ==============================================
|
|
assign processing_active = (state != S_IDLE);
|
|
assign frame_complete = (state == S_IDLE && frame_buffer_full == 0);
|
|
|
|
endmodule
|