Jason 5fd632bc47 Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator ...

CDC fixes across 6 RTL files based on post-implementation report_cdc analysis:
- P0: sync stm32_mixers_enable and new_chirp_pulse to clk_120m via toggle CDC
       in radar_transmitter, add ft601 reset synchronizer and USB holding
       registers with proper edge detection in usb_data_interface
- P1: add ASYNC_REG to edge_detector, convert new_chirp_frame to toggle CDC,
       fix USB valid edge detect to use fully-synced signal
- P2: register Gray encoding in cdc_adc_to_processing source domain, sync
       ft601_txe and stm32_mixers_enable for status_reg in radar_system_top
- Safety: add in_bin_count overflow guard in range_bin_decimator to prevent
          downstream BRAM corruption

All 13 regression test suites pass (159 individual tests).

2026-03-17 13:48:47 +02:00

..

constraints

Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

2026-03-16 23:17:38 +02:00

formal

Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs

2026-03-17 12:47:22 +02:00

scripts

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

tb

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

ad9484_interface_400m.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

cdc_modules.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

chirp_memory_loader_param.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cic_decimator_4x_enhanced.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

dac_interface_single.v

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

ddc_400m.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

doppler_processor.v

Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs

2026-03-17 12:47:22 +02:00

edge_detector.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

fft_engine.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

fft_twiddle_32.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fft_twiddle_1024.mem

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

fir_lowpass.v

Fix P0/P1 RTL bugs found during pre-hardware audit

2026-03-16 22:24:06 +02:00

frequency_matched_filter.v

Add files via upload

2026-03-09 00:17:39 +00:00

latency_buffer_2159.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

long_chirp_seg0_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg0_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg1_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg2_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

long_chirp_seg3_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

matched_filter_multi_segment.v

Fix overlap-save: fill full 1024-sample buffer per segment, zero-pad last partial segment

2026-03-16 19:15:23 +02:00

matched_filter_processing_chain.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00

nco_400m_enhanced.v

Fix P0/P1 RTL bugs found during pre-hardware audit

2026-03-16 22:24:06 +02:00

plfm_chirp_controller.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_mode_controller.v

Add SymbiYosys formal verification for 6 modules, fix 2 doppler bugs

2026-03-17 12:47:22 +02:00

radar_receiver_final.v

Fix P0/P1 RTL bugs found during pre-hardware audit

2026-03-16 22:24:06 +02:00

radar_system_top.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

radar_transmitter.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

range_bin_decimator.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

short_chirp_i.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

short_chirp_q.mem

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

usb_data_interface.v

Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator

2026-03-17 13:48:47 +02:00

xfft_32.v

Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference

2026-03-16 10:25:07 +02:00