Jason 558f49cd4a Add 8 Verilog testbenches with full coverage (144/144 pass) ...

Testbenches for: edge_detector (17), nco_400m (20), cic_decimator (14),
fir_lowpass (13), freq_matched_filter (14), ddc_400m full-chain (7),
chirp_controller (39), chirp_contract regression (20).

Includes CSV output data for waveform verification.
Add .gitignore to exclude VCD/VVP build artifacts.

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..

cic_dc_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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cic_impulse_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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cic_sine_passband.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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ddc_120mhz_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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fir_dc_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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fir_impulse_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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fir_sine_passband.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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mf_pipeline_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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nco_1mhz_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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nco_120mhz_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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nco_freq_switch.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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nco_quadrature.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

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tb_chirp_contract.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

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tb_chirp_controller.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

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tb_cic_decimator.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

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tb_ddc_400m.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

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tb_edge_detector.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

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tb_fir_lowpass.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

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tb_freq_matched_filter.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

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tb_nco_400m.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

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