Jason
fcf3999e39
Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source and destination clock domains use correctly-synchronized resets. Previously cdc_chirp_counter's destination-side sync chain (100MHz) was reset by sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings. RTL changes: - cdc_modules.v: split reset port, source logic uses src_reset_n, destination sync chains + output logic use dst_reset_n - radar_system_top.v: cdc_chirp_counter gets proper per-domain resets - ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst) - formal/fv_cdc_adc.v: updated wrapper for new port interface Build 7 fixes (previously untouched): - radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync - latency_buffer_2159.v: BRAM read registration - constraints: ft601 IOB -quiet fix - tb_latency_buffer.v: updated for BRAM changes Testbench hardening (tb_cdc_modules.v, +31 new assertions): - A5-A7: split-domain reset tests (staggered deassertion, independent dst reset while src active — catches the P0 bug class) - A8: port connectivity (no X/Z on outputs) - B7: cdc_single_bit port connectivity - C6: cdc_handshake reset recovery + port connectivity Full regression: 13/13 test suites pass (257 total assertions).
129 lines
4.0 KiB
Verilog
129 lines
4.0 KiB
Verilog
`timescale 1ns / 1ps
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// latency_buffer_2159_fixed.v
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module latency_buffer_2159 #(
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parameter DATA_WIDTH = 32,
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parameter LATENCY = 3187
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) (
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input wire clk,
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input wire reset_n,
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input wire [DATA_WIDTH-1:0] data_in,
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input wire valid_in,
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output wire [DATA_WIDTH-1:0] data_out,
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output wire valid_out
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);
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// ========== FIXED PARAMETERS ==========
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localparam ADDR_WIDTH = 12; // Enough for 4096 entries (>2159)
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// ========== FIXED LOGIC ==========
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(* ram_style = "block" *) reg [DATA_WIDTH-1:0] bram [0:4095];
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reg [ADDR_WIDTH-1:0] write_ptr;
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reg [ADDR_WIDTH-1:0] read_ptr;
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reg valid_out_reg;
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// Delay counter to track when LATENCY cycles have passed
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reg [ADDR_WIDTH-1:0] delay_counter;
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reg buffer_has_data; // Flag when buffer has accumulated LATENCY samples
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// ========== FIXED INITIALIZATION ==========
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integer k;
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initial begin
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for (k = 0; k < 4096; k = k + 1) begin
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bram[k] = {DATA_WIDTH{1'b0}};
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end
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write_ptr = 0;
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read_ptr = 0;
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valid_out_reg = 0;
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delay_counter = 0;
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buffer_has_data = 0;
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end
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// ========== BRAM WRITE (synchronous only, no async reset) ==========
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// Xilinx Block RAMs do not support asynchronous resets.
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// Separating the BRAM write into its own always block avoids Synth 8-3391.
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// The initial block above handles power-on initialization for FPGA.
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always @(posedge clk) begin
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if (valid_in) begin
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bram[write_ptr] <= data_in;
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end
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end
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// ========== CONTROL LOGIC (with async reset) ==========
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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write_ptr <= 0;
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read_ptr <= 0;
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valid_out_reg <= 0;
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delay_counter <= 0;
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buffer_has_data <= 0;
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end else begin
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// Default: no valid output
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valid_out_reg <= 0;
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// ===== WRITE SIDE =====
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if (valid_in) begin
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// Increment write pointer (wrap at 4095)
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if (write_ptr == 4095) begin
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write_ptr <= 0;
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end else begin
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write_ptr <= write_ptr + 1;
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end
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// Count how many samples we've written
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if (delay_counter < LATENCY) begin
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delay_counter <= delay_counter + 1;
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// When we've written LATENCY samples, buffer is "primed"
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if (delay_counter == LATENCY - 1) begin
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buffer_has_data <= 1'b1;
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end
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end
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end
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// ===== READ SIDE =====
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// Only start reading after we have LATENCY samples in buffer
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if (buffer_has_data && valid_in) begin
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// Read pointer follows write pointer with LATENCY delay
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// Calculate: read_ptr = (write_ptr - LATENCY) mod 4096
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// Handle wrap-around correctly
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if (write_ptr >= LATENCY) begin
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read_ptr <= write_ptr - LATENCY;
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end else begin
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// Wrap around: 4096 + write_ptr - LATENCY
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read_ptr <= 4096 + write_ptr - LATENCY;
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end
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// Output is valid
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valid_out_reg <= 1'b1;
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end
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end
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end
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// ========== BRAM READ (synchronous — required for Block RAM inference) ==========
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// Xilinx Block RAMs physically register the read output. An async read
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// (assign data_out = bram[addr]) forces Vivado to use distributed LUTRAM
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// instead, wasting ~704 LUTs. Registering the read adds 1 cycle of latency,
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// compensated by the valid pipeline stage below.
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reg [DATA_WIDTH-1:0] data_out_reg;
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always @(posedge clk) begin
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data_out_reg <= bram[read_ptr];
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end
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// Pipeline valid_out_reg by 1 cycle to align with registered BRAM read
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reg valid_out_pipe;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n)
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valid_out_pipe <= 1'b0;
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else
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valid_out_pipe <= valid_out_reg;
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end
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assign data_out = data_out_reg;
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assign valid_out = valid_out_pipe;
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endmodule |