Jason 44460e7443 fix(constraints): change adc_pwdn from LVCMOS33 to LVCMOS25 for Bank 14 compatibility ...

The placer enforces a single VCCO per bank. LVDS_25 forces Bank 14
to VCCO=2.5V, which conflicts with LVCMOS33 (needs 3.3V). Changing
adc_pwdn to LVCMOS25 resolves [Place 30-372] bank incompatibility.
The AD9484 PWDN pin has CMOS-level thresholds (~0.8V), so 2.5V
output drives it correctly.

2026-04-07 06:07:47 +03:00

..

9_1_Microcontroller

Gap 3 Safety Architecture: IWDG watchdog, Emergency_Stop PA rail cutoff, temp max, periodic IDQ re-read, emergency state ordering + 5 tests (20/20 pass)

2026-03-19 21:58:39 +02:00

9_2_FPGA

fix(constraints): change adc_pwdn from LVCMOS33 to LVCMOS25 for Bank 14 compatibility

2026-04-07 06:07:47 +03:00

9_3_GUI

fix(rtl,gui,cosim,formal): adapt surrounding files for dual 16-pt FFT (follow-up to PR #33)

2026-04-06 23:15:50 +03:00

tools

Add UART diagnostic capture tool for board-day bring-up

2026-03-19 16:32:54 +02:00