Jason ed6f79c6d3 FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache ...

FIR: Add coeff_reg/mult_reg pipeline stages to fix 68 DPIP-1 + 35 DPOP-2
DRC warnings. Valid pipeline widened 7→9 bits (+2 cycle latency).

Matched filter: Migrate input_buffer_i/q from register arrays to BRAM
(~33K FF savings). Overlap-save uses register cache captured during
ST_PROCESSING to avoid BRAM read/write conflicts during overlap copy.
New ST_OVERLAP_COPY state writes cached tail samples back sequentially.

Both changes pass 18/18 FPGA regression. Golden data regenerated for
+2 FIR latency baseline.

2026-03-19 20:39:01 +02:00

..

adc_dc.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

adc_multi_target.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

adc_noise_only.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

adc_sine_1mhz.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

adc_single_target.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

bb_mf_test_i.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

bb_mf_test_q.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

compare_dc.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

compare_doppler.py

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

compare_mf_chirp.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

compare_mf_dc.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

compare_mf_impulse.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

compare_mf_tone5.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

compare_mf.py

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

compare_multi_target.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

compare_noise_only.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

compare_sine_1mhz.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

compare_single_target.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

compare.py

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

doppler_golden_py_moving.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_moving.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_stationary.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_stationary.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_two_targets.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_golden_py_two_targets.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_input_moving.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_input_stationary.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

doppler_input_two_targets.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

fpga_model.py

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

gen_chirp_mem.py

Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001

2026-03-16 19:53:40 +02:00

gen_doppler_golden.py

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

gen_mf_cosim_golden.py

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

gen_multiseg_golden.py

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

mf_golden_py_chirp.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_dc.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_i_chirp.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_i_dc.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_i_impulse.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_i_tone5.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_impulse.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_q_chirp.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_q_dc.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_q_impulse.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_q_tone5.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_golden_py_tone5.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_dc_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_dc_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_impulse_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_impulse_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_tone5_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_ref_tone5_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_dc_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_dc_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_impulse_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_impulse_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_tone5_i.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

mf_sig_tone5_q.hex

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

multiseg_golden_seg0_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg0_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg1_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg1_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg2_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg2_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg3_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden_seg3_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_golden.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_input_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_input_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg0_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg0_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg1_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg1_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg2_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg2_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg3_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_ref_seg3_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_golden.csv

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_input_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_input_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_ref_i.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

multiseg_short_ref_q.hex

Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites

2026-03-16 18:09:26 +02:00

radar_scene.py

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

ref_chirp_i.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

ref_chirp_q.hex

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_bb_dc.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_bb_multi_target.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_bb_noise_only.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_bb_sine_1mhz.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_bb_single_target.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

rtl_mf_chirp.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

rtl_mf_dc.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

rtl_mf_impulse.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

rtl_mf_tone5.csv

Add matched-filter co-simulation: bit-perfect validation of Python model vs synthesis-branch RTL (4/4 scenarios, correlation=1.0)

2026-03-16 16:23:01 +02:00

rx_final_doppler_out.csv

FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache

2026-03-19 20:39:01 +02:00

scenario_info.txt

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

validate_mem_files.py

Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts

2026-03-18 01:28:42 +02:00