Jason
5499827ab7
FMC LPC dev build for TE0713/TE0701 + UMFT601X-B stack. Fixed timing closure: replaced set_output_delay with set_max_delay -datapath_only to eliminate false IBUF+BUFG clock skew penalty on source-synchronous outputs. Removed erroneous set_input_delay on output-only ft601_be[*]. Added IOB packing for siwu_n, false paths for async GPIO/reset/wakeup. Strategy: Performance_ExplorePostRoutePhysOpt. Results: WNS +0.059 ns, WHS +0.121 ns, DRC 0 errors, 0 failing endpoints. Bitstream: docs/artifacts/te0713-te0701-umft601x-dev-2026-03-21.bit
24688 lines
1.8 MiB
Plaintext
24688 lines
1.8 MiB
Plaintext
Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2025 Advanced Micro Devices, Inc. All Rights Reserved.
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| Tool Version : Vivado v.2025.2 (lin64) Build 6299465 Fri Nov 14 12:34:56 MST 2025
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| Date : Sat Mar 21 20:41:16 2026
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| Host : jason-pc running 64-bit Ubuntu 24.04.4 LTS
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| Command : report_timing_summary -report_unconstrained -max_paths 100 -file /home/jason-stone/PLFM_RADAR_work/PLFM_RADAR/9_Firmware/9_2_FPGA/vivado_te0713_umft601x_dev/reports/timing_summary.rpt
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| Design : radar_system_top_te0713_umft601x_dev
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| Device : 7a200t-fbg484
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| Speed File : -2 PRODUCTION 1.23 2018-06-13
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| Design State : Physopt postRoute
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---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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Timing Summary Report
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------------------------------------------------------------------------------------------------
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| Timer Settings
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| --------------
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------------------------------------------------------------------------------------------------
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Enable Multi Corner Analysis : Yes
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Enable Pessimism Removal : Yes
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Pessimism Removal Resolution : Nearest Common Node
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Enable Input Delay Default Clock : No
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Enable Preset / Clear Arcs : No
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Disable Flight Delays : No
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Ignore I/O Paths : No
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Timing Early Launch at Borrowing Latches : No
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Borrow Time for Max Delay Exceptions : Yes
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Merge Timing Exceptions : Yes
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Inter-SLR Compensation : Conservative
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Corner Analyze Analyze
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Name Max Paths Min Paths
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------ --------- ---------
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Slow Yes Yes
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Fast Yes Yes
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------------------------------------------------------------------------------------------------
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| Report Methodology
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| ------------------
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------------------------------------------------------------------------------------------------
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Rule Severity Description Violations
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------ -------- -------------------------------- ----------
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HPDR-1 Warning Port pin direction inconsistency 21
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Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.
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check_timing report
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Table of Contents
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-----------------
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1. checking no_clock (0)
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2. checking constant_clock (0)
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3. checking pulse_width_clock (0)
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4. checking unconstrained_internal_endpoints (0)
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5. checking no_input_delay (0)
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6. checking no_output_delay (3)
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7. checking multiple_clock (0)
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8. checking generated_clocks (0)
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9. checking loops (0)
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10. checking partial_input_delay (0)
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11. checking partial_output_delay (0)
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12. checking latch_loops (0)
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1. checking no_clock (0)
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------------------------
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There are 0 register/latch pins with no clock.
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2. checking constant_clock (0)
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------------------------------
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There are 0 register/latch pins with constant_clock.
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3. checking pulse_width_clock (0)
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---------------------------------
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There are 0 register/latch pins which need pulse_width check
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4. checking unconstrained_internal_endpoints (0)
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------------------------------------------------
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There are 0 pins that are not constrained for maximum delay.
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There are 0 pins that are not constrained for maximum delay due to constant clock.
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5. checking no_input_delay (0)
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------------------------------
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There are 0 input ports with no input delay specified.
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There are 0 input ports with no input delay but user has a false path constraint.
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6. checking no_output_delay (3)
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-------------------------------
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There are 0 ports with no output delay specified.
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There are 3 ports with no output delay but user has a false path constraint (MEDIUM)
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There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
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7. checking multiple_clock (0)
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------------------------------
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There are 0 register/latch pins with multiple clocks.
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8. checking generated_clocks (0)
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--------------------------------
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There are 0 generated clocks that are not connected to a clock source.
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9. checking loops (0)
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---------------------
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There are 0 combinational loops in the design.
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10. checking partial_input_delay (0)
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------------------------------------
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There are 0 input ports with partial input delay specified.
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11. checking partial_output_delay (0)
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-------------------------------------
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There are 0 ports with partial output delay specified.
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12. checking latch_loops (0)
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----------------------------
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There are 0 combinational latch loops in the design through latch input
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------------------------------------------------------------------------------------------------
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| Design Timing Summary
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| ---------------------
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------------------------------------------------------------------------------------------------
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WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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0.059 0.000 0 1034 0.121 0.000 0 995 4.500 0.000 0 367
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All user specified timing constraints are met.
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------------------------------------------------------------------------------------------------
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| Clock Summary
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| -------------
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------------------------------------------------------------------------------------------------
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Clock Waveform(ns) Period(ns) Frequency(MHz)
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----- ------------ ---------- --------------
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ft601_clk_in {0.000 5.000} 10.000 100.000
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------------------------------------------------------------------------------------------------
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| Intra Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
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----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
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ft601_clk_in 0.059 0.000 0 765 0.121 0.000 0 765 4.500 0.000 0 367
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------------------------------------------------------------------------------------------------
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| Inter Clock Table
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| -----------------
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------------------------------------------------------------------------------------------------
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From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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------------------------------------------------------------------------------------------------
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| Other Path Groups Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
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---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
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**async_default** ft601_clk_in ft601_clk_in 2.305 0.000 0 230 0.978 0.000 0 230
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**default** ft601_clk_in 0.470 0.000 0 39
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------------------------------------------------------------------------------------------------
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| User Ignored Path Table
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| -----------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock
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---------- ---------- --------
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(none) ft601_clk_in
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------------------------------------------------------------------------------------------------
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| Unconstrained Path Table
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| ------------------------
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------------------------------------------------------------------------------------------------
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Path Group From Clock To Clock
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---------- ---------- --------
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------------------------------------------------------------------------------------------------
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| Timing Details
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| --------------
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------------------------------------------------------------------------------------------------
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---------------------------------------------------------------------------------------------------
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From Clock: ft601_clk_in
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To Clock: ft601_clk_in
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Setup : 0 Failing Endpoints, Worst Slack 0.059ns, Total Violation 0.000ns
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Hold : 0 Failing Endpoints, Worst Slack 0.121ns, Total Violation 0.000ns
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PW : 0 Failing Endpoints, Worst Slack 4.500ns, Total Violation 0.000ns
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---------------------------------------------------------------------------------------------------
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Max Delay Paths
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--------------------------------------------------------------------------------------
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Slack (MET) : 0.059ns (required time - arrival time)
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Source: ft601_txe
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(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: usb_inst/ft601_be_reg[3]/CE
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(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: ft601_clk_in
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
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Data Path Delay: 7.287ns (logic 1.603ns (21.997%) route 5.684ns (78.003%))
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Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1)
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Input Delay: 7.000ns
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Clock Path Skew: 4.738ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.738ns = ( 14.738 - 10.000 )
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Source Clock Delay (SCD): 0.000ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.100ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock ft601_clk_in rise edge)
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0.000 0.000 r
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input delay 7.000 7.000
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E17 0.000 7.000 f ft601_txe (IN)
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net (fo=0) 0.000 7.000 ft601_txe
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E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
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net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
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SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
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net (fo=4, routed) 0.694 12.230 usb_inst/ft601_be[3]_i_3_n_0
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SLICE_X0Y186 LUT6 (Prop_lut6_I2_O) 0.105 12.335 r usb_inst/ft601_be[3]_i_1/O
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net (fo=5, routed) 1.952 14.287 usb_inst/ft601_be[3]_i_1_n_0
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OLOGIC_X0Y240 FDPE r usb_inst/ft601_be_reg[3]/CE
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------------------------------------------------------------------- -------------------
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(clock ft601_clk_in rise edge)
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10.000 10.000 r
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J20 0.000 10.000 r ft601_clk_in (IN)
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net (fo=0) 0.000 10.000 ft601_clk_in
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J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
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net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
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net (fo=366, routed) 1.593 14.738 usb_inst/ft601_clk_in_IBUF_BUFG
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OLOGIC_X0Y240 FDPE r usb_inst/ft601_be_reg[3]/C
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clock pessimism 0.000 14.738
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clock uncertainty -0.061 14.677
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OLOGIC_X0Y240 FDPE (Setup_fdpe_C_CE) -0.331 14.346 usb_inst/ft601_be_reg[3]
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-------------------------------------------------------------------
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required time 14.346
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arrival time -14.287
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-------------------------------------------------------------------
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slack 0.059
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Slack (MET) : 0.170ns (required time - arrival time)
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Source: ft601_txe
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(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: usb_inst/ft601_be_reg[2]/CE
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(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: ft601_clk_in
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
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Data Path Delay: 7.176ns (logic 1.603ns (22.337%) route 5.573ns (77.663%))
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Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1)
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Input Delay: 7.000ns
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Clock Path Skew: 4.738ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.738ns = ( 14.738 - 10.000 )
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Source Clock Delay (SCD): 0.000ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.100ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock ft601_clk_in rise edge)
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0.000 0.000 r
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input delay 7.000 7.000
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E17 0.000 7.000 f ft601_txe (IN)
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net (fo=0) 0.000 7.000 ft601_txe
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E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
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net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
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SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
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net (fo=4, routed) 0.694 12.230 usb_inst/ft601_be[3]_i_3_n_0
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SLICE_X0Y186 LUT6 (Prop_lut6_I2_O) 0.105 12.335 r usb_inst/ft601_be[3]_i_1/O
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net (fo=5, routed) 1.841 14.176 usb_inst/ft601_be[3]_i_1_n_0
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OLOGIC_X0Y239 FDPE r usb_inst/ft601_be_reg[2]/CE
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------------------------------------------------------------------- -------------------
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(clock ft601_clk_in rise edge)
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10.000 10.000 r
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J20 0.000 10.000 r ft601_clk_in (IN)
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net (fo=0) 0.000 10.000 ft601_clk_in
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J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
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net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
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net (fo=366, routed) 1.593 14.738 usb_inst/ft601_clk_in_IBUF_BUFG
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OLOGIC_X0Y239 FDPE r usb_inst/ft601_be_reg[2]/C
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clock pessimism 0.000 14.738
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clock uncertainty -0.061 14.677
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OLOGIC_X0Y239 FDPE (Setup_fdpe_C_CE) -0.331 14.346 usb_inst/ft601_be_reg[2]
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-------------------------------------------------------------------
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required time 14.346
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arrival time -14.176
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-------------------------------------------------------------------
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slack 0.170
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Slack (MET) : 0.469ns (required time - arrival time)
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Source: ft601_txe
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(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: usb_inst/ft601_data_out_reg[12]/CE
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(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: ft601_clk_in
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
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Data Path Delay: 6.711ns (logic 1.708ns (25.448%) route 5.003ns (74.552%))
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Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
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Input Delay: 7.000ns
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Clock Path Skew: 4.572ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
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Source Clock Delay (SCD): 0.000ns
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Clock Pessimism Removal (CPR): 0.000ns
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Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
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Total System Jitter (TSJ): 0.071ns
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Total Input Jitter (TIJ): 0.100ns
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Discrete Jitter (DJ): 0.000ns
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Phase Error (PE): 0.000ns
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Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
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------------------------------------------------------------------- -------------------
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(clock ft601_clk_in rise edge)
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0.000 0.000 r
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input delay 7.000 7.000
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E17 0.000 7.000 f ft601_txe (IN)
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net (fo=0) 0.000 7.000 ft601_txe
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E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
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net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
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SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
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net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
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SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
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net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
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SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
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net (fo=32, routed) 1.467 13.711 usb_inst/ft601_data_out[31]_i_1_n_0
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OLOGIC_X0Y155 FDCE r usb_inst/ft601_data_out_reg[12]/CE
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------------------------------------------------------------------- -------------------
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(clock ft601_clk_in rise edge)
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10.000 10.000 r
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J20 0.000 10.000 r ft601_clk_in (IN)
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net (fo=0) 0.000 10.000 ft601_clk_in
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J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
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net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
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BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
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net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
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OLOGIC_X0Y155 FDCE r usb_inst/ft601_data_out_reg[12]/C
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clock pessimism 0.000 14.572
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clock uncertainty -0.061 14.511
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OLOGIC_X0Y155 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[12]
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-------------------------------------------------------------------
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required time 14.180
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arrival time -13.711
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-------------------------------------------------------------------
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slack 0.469
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Slack (MET) : 0.479ns (required time - arrival time)
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Source: ft601_txe
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(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
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Destination: usb_inst/ft601_data_out_reg[14]/CE
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(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
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Path Group: ft601_clk_in
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Path Type: Setup (Max at Slow Process Corner)
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Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
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Data Path Delay: 6.701ns (logic 1.708ns (25.487%) route 4.993ns (74.513%))
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Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
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Input Delay: 7.000ns
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Clock Path Skew: 4.572ns (DCD - SCD + CPR)
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Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
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Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.457 13.701 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y156 FDCE r usb_inst/ft601_data_out_reg[14]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y156 FDCE r usb_inst/ft601_data_out_reg[14]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y156 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -13.701
|
|
-------------------------------------------------------------------
|
|
slack 0.479
|
|
|
|
Slack (MET) : 0.488ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[0]/CE
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.851ns (logic 1.603ns (23.397%) route 5.248ns (76.603%))
|
|
Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.731ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.731ns = ( 14.731 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.694 12.230 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X0Y186 LUT6 (Prop_lut6_I2_O) 0.105 12.335 r usb_inst/ft601_be[3]_i_1/O
|
|
net (fo=5, routed) 1.516 13.851 usb_inst/ft601_be[3]_i_1_n_0
|
|
OLOGIC_X0Y218 FDPE r usb_inst/ft601_be_reg[0]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.586 14.731 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y218 FDPE r usb_inst/ft601_be_reg[0]/C
|
|
clock pessimism 0.000 14.731
|
|
clock uncertainty -0.061 14.670
|
|
OLOGIC_X0Y218 FDPE (Setup_fdpe_C_CE) -0.331 14.339 usb_inst/ft601_be_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 14.339
|
|
arrival time -13.851
|
|
-------------------------------------------------------------------
|
|
slack 0.488
|
|
|
|
Slack (MET) : 0.525ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[1]/CE
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.814ns (logic 1.603ns (23.523%) route 5.211ns (76.477%))
|
|
Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.731ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.731ns = ( 14.731 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.694 12.230 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X0Y186 LUT6 (Prop_lut6_I2_O) 0.105 12.335 r usb_inst/ft601_be[3]_i_1/O
|
|
net (fo=5, routed) 1.479 13.814 usb_inst/ft601_be[3]_i_1_n_0
|
|
OLOGIC_X0Y217 FDPE r usb_inst/ft601_be_reg[1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.586 14.731 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y217 FDPE r usb_inst/ft601_be_reg[1]/C
|
|
clock pessimism 0.000 14.731
|
|
clock uncertainty -0.061 14.670
|
|
OLOGIC_X0Y217 FDPE (Setup_fdpe_C_CE) -0.331 14.339 usb_inst/ft601_be_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.339
|
|
arrival time -13.814
|
|
-------------------------------------------------------------------
|
|
slack 0.525
|
|
|
|
Slack (MET) : 0.587ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[11]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.593ns (logic 1.708ns (25.904%) route 4.885ns (74.096%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.349 13.593 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y157 FDCE r usb_inst/ft601_data_out_reg[11]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y157 FDCE r usb_inst/ft601_data_out_reg[11]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y157 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -13.593
|
|
-------------------------------------------------------------------
|
|
slack 0.587
|
|
|
|
Slack (MET) : 0.615ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[9]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.565ns (logic 1.708ns (26.017%) route 4.857ns (73.984%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.321 13.565 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y158 FDCE r usb_inst/ft601_data_out_reg[9]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y158 FDCE r usb_inst/ft601_data_out_reg[9]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y158 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -13.565
|
|
-------------------------------------------------------------------
|
|
slack 0.615
|
|
|
|
Slack (MET) : 0.723ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[6]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.457ns (logic 1.708ns (26.452%) route 4.749ns (73.548%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.213 13.457 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y159 FDCE r usb_inst/ft601_data_out_reg[6]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y159 FDCE r usb_inst/ft601_data_out_reg[6]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y159 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -13.457
|
|
-------------------------------------------------------------------
|
|
slack 0.723
|
|
|
|
Slack (MET) : 0.752ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[4]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.428ns (logic 1.708ns (26.570%) route 4.720ns (73.430%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.184 13.428 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y160 FDCE r usb_inst/ft601_data_out_reg[4]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y160 FDCE r usb_inst/ft601_data_out_reg[4]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y160 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -13.428
|
|
-------------------------------------------------------------------
|
|
slack 0.752
|
|
|
|
Slack (MET) : 0.799ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[1]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.377ns (logic 1.708ns (26.783%) route 4.669ns (73.217%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.568ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.133 13.377 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y164 FDCE r usb_inst/ft601_data_out_reg[1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y164 FDCE r usb_inst/ft601_data_out_reg[1]/C
|
|
clock pessimism 0.000 14.568
|
|
clock uncertainty -0.061 14.507
|
|
OLOGIC_X0Y164 FDCE (Setup_fdce_C_CE) -0.331 14.176 usb_inst/ft601_data_out_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.176
|
|
arrival time -13.377
|
|
-------------------------------------------------------------------
|
|
slack 0.799
|
|
|
|
Slack (MET) : 0.814ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[28]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.364ns (logic 1.708ns (26.837%) route 4.656ns (73.163%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.570ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.120 13.364 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y161 FDCE r usb_inst/ft601_data_out_reg[28]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y161 FDCE r usb_inst/ft601_data_out_reg[28]/C
|
|
clock pessimism 0.000 14.570
|
|
clock uncertainty -0.061 14.509
|
|
OLOGIC_X0Y161 FDCE (Setup_fdce_C_CE) -0.331 14.178 usb_inst/ft601_data_out_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 14.178
|
|
arrival time -13.364
|
|
-------------------------------------------------------------------
|
|
slack 0.814
|
|
|
|
Slack (MET) : 0.895ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[5]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.275ns (logic 1.708ns (27.216%) route 4.567ns (72.784%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.562ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.562ns = ( 14.562 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.031 13.275 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y170 FDCE r usb_inst/ft601_data_out_reg[5]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.417 14.562 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y170 FDCE r usb_inst/ft601_data_out_reg[5]/C
|
|
clock pessimism 0.000 14.562
|
|
clock uncertainty -0.061 14.501
|
|
OLOGIC_X0Y170 FDCE (Setup_fdce_C_CE) -0.331 14.170 usb_inst/ft601_data_out_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 14.170
|
|
arrival time -13.275
|
|
-------------------------------------------------------------------
|
|
slack 0.895
|
|
|
|
Slack (MET) : 0.900ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[29]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.279ns (logic 1.708ns (27.202%) route 4.571ns (72.798%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.570ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.034 13.279 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y162 FDCE r usb_inst/ft601_data_out_reg[29]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y162 FDCE r usb_inst/ft601_data_out_reg[29]/C
|
|
clock pessimism 0.000 14.570
|
|
clock uncertainty -0.061 14.509
|
|
OLOGIC_X0Y162 FDCE (Setup_fdce_C_CE) -0.331 14.178 usb_inst/ft601_data_out_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 14.178
|
|
arrival time -13.279
|
|
-------------------------------------------------------------------
|
|
slack 0.900
|
|
|
|
Slack (MET) : 0.906ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[27]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.270ns (logic 1.708ns (27.238%) route 4.562ns (72.762%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.568ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.026 13.270 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y165 FDCE r usb_inst/ft601_data_out_reg[27]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y165 FDCE r usb_inst/ft601_data_out_reg[27]/C
|
|
clock pessimism 0.000 14.568
|
|
clock uncertainty -0.061 14.507
|
|
OLOGIC_X0Y165 FDCE (Setup_fdce_C_CE) -0.331 14.176 usb_inst/ft601_data_out_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 14.176
|
|
arrival time -13.270
|
|
-------------------------------------------------------------------
|
|
slack 0.906
|
|
|
|
Slack (MET) : 0.908ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[3]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.268ns (logic 1.708ns (27.246%) route 4.560ns (72.754%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.568ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 1.024 13.268 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y163 FDCE r usb_inst/ft601_data_out_reg[3]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y163 FDCE r usb_inst/ft601_data_out_reg[3]/C
|
|
clock pessimism 0.000 14.568
|
|
clock uncertainty -0.061 14.507
|
|
OLOGIC_X0Y163 FDCE (Setup_fdce_C_CE) -0.331 14.176 usb_inst/ft601_data_out_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.176
|
|
arrival time -13.268
|
|
-------------------------------------------------------------------
|
|
slack 0.908
|
|
|
|
Slack (MET) : 0.956ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[23]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.217ns (logic 1.708ns (27.470%) route 4.509ns (72.530%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.565ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.565ns = ( 14.565 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.973 13.217 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y168 FDCE r usb_inst/ft601_data_out_reg[23]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.420 14.565 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y168 FDCE r usb_inst/ft601_data_out_reg[23]/C
|
|
clock pessimism 0.000 14.565
|
|
clock uncertainty -0.061 14.504
|
|
OLOGIC_X0Y168 FDCE (Setup_fdce_C_CE) -0.331 14.173 usb_inst/ft601_data_out_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 14.173
|
|
arrival time -13.217
|
|
-------------------------------------------------------------------
|
|
slack 0.956
|
|
|
|
Slack (MET) : 0.963ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[7]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.207ns (logic 1.708ns (27.515%) route 4.499ns (72.485%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.562ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.562ns = ( 14.562 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.963 13.207 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y169 FDCE r usb_inst/ft601_data_out_reg[7]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.417 14.562 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y169 FDCE r usb_inst/ft601_data_out_reg[7]/C
|
|
clock pessimism 0.000 14.562
|
|
clock uncertainty -0.061 14.501
|
|
OLOGIC_X0Y169 FDCE (Setup_fdce_C_CE) -0.331 14.170 usb_inst/ft601_data_out_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 14.170
|
|
arrival time -13.207
|
|
-------------------------------------------------------------------
|
|
slack 0.963
|
|
|
|
Slack (MET) : 0.990ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[26]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.186ns (logic 1.708ns (27.609%) route 4.478ns (72.391%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.568ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.942 13.186 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y166 FDCE r usb_inst/ft601_data_out_reg[26]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y166 FDCE r usb_inst/ft601_data_out_reg[26]/C
|
|
clock pessimism 0.000 14.568
|
|
clock uncertainty -0.061 14.507
|
|
OLOGIC_X0Y166 FDCE (Setup_fdce_C_CE) -0.331 14.176 usb_inst/ft601_data_out_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time 14.176
|
|
arrival time -13.186
|
|
-------------------------------------------------------------------
|
|
slack 0.990
|
|
|
|
Slack (MET) : 0.992ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[21]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.181ns (logic 1.708ns (27.632%) route 4.473ns (72.368%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.565ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.565ns = ( 14.565 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.937 13.181 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y167 FDCE r usb_inst/ft601_data_out_reg[21]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.420 14.565 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y167 FDCE r usb_inst/ft601_data_out_reg[21]/C
|
|
clock pessimism 0.000 14.565
|
|
clock uncertainty -0.061 14.504
|
|
OLOGIC_X0Y167 FDCE (Setup_fdce_C_CE) -0.331 14.173 usb_inst/ft601_data_out_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 14.173
|
|
arrival time -13.181
|
|
-------------------------------------------------------------------
|
|
slack 0.992
|
|
|
|
Slack (MET) : 1.070ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[6]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.285ns (logic 1.591ns (25.321%) route 4.694ns (74.679%))
|
|
Logic Levels: 3 (IBUF=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.585ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.585ns = ( 14.585 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.995 12.376 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I0_O) 0.105 12.481 r usb_inst/byte_counter[7]_i_4/O
|
|
net (fo=1, routed) 0.240 12.721 usb_inst/byte_counter[7]_i_4_n_0
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.105 12.826 r usb_inst/byte_counter[7]_i_1/O
|
|
net (fo=8, routed) 0.459 13.285 usb_inst/byte_counter[7]_i_1_n_0
|
|
SLICE_X3Y184 FDCE r usb_inst/byte_counter_reg[6]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.439 14.585 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y184 FDCE r usb_inst/byte_counter_reg[6]/C
|
|
clock pessimism 0.000 14.585
|
|
clock uncertainty -0.061 14.523
|
|
SLICE_X3Y184 FDCE (Setup_fdce_C_CE) -0.168 14.355 usb_inst/byte_counter_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 14.355
|
|
arrival time -13.285
|
|
-------------------------------------------------------------------
|
|
slack 1.070
|
|
|
|
Slack (MET) : 1.087ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[18]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.096ns (logic 1.708ns (28.019%) route 4.388ns (71.981%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.574ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.851 13.096 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y198 FDCE r usb_inst/ft601_data_out_reg[18]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.429 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y198 FDCE r usb_inst/ft601_data_out_reg[18]/C
|
|
clock pessimism 0.000 14.574
|
|
clock uncertainty -0.061 14.513
|
|
OLOGIC_X0Y198 FDCE (Setup_fdce_C_CE) -0.331 14.182 usb_inst/ft601_data_out_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 14.182
|
|
arrival time -13.096
|
|
-------------------------------------------------------------------
|
|
slack 1.087
|
|
|
|
Slack (MET) : 1.090ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[31]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.078ns (logic 1.708ns (28.101%) route 4.370ns (71.899%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.560ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.560ns = ( 14.560 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.834 13.078 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y176 FDCE r usb_inst/ft601_data_out_reg[31]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.415 14.560 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y176 FDCE r usb_inst/ft601_data_out_reg[31]/C
|
|
clock pessimism 0.000 14.560
|
|
clock uncertainty -0.061 14.499
|
|
OLOGIC_X0Y176 FDCE (Setup_fdce_C_CE) -0.331 14.168 usb_inst/ft601_data_out_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time 14.168
|
|
arrival time -13.078
|
|
-------------------------------------------------------------------
|
|
slack 1.090
|
|
|
|
Slack (MET) : 1.093ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_wr_n_reg/CE
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.253ns (logic 1.498ns (23.956%) route 4.755ns (76.044%))
|
|
Logic Levels: 2 (IBUF=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.738ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.738ns = ( 14.738 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.082 11.475 usb_inst/ft601_txe_IBUF
|
|
SLICE_X0Y195 LUT6 (Prop_lut6_I4_O) 0.105 11.580 r usb_inst/ft601_wr_n_i_1/O
|
|
net (fo=2, routed) 1.673 13.253 usb_inst/ft601_wr_n_i_1_n_0
|
|
OLOGIC_X0Y242 FDPE r usb_inst/ft601_wr_n_reg/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.593 14.738 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y242 FDPE r usb_inst/ft601_wr_n_reg/C
|
|
clock pessimism 0.000 14.738
|
|
clock uncertainty -0.061 14.677
|
|
OLOGIC_X0Y242 FDPE (Setup_fdpe_C_CE) -0.331 14.346 usb_inst/ft601_wr_n_reg
|
|
-------------------------------------------------------------------
|
|
required time 14.346
|
|
arrival time -13.253
|
|
-------------------------------------------------------------------
|
|
slack 1.093
|
|
|
|
Slack (MET) : 1.101ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[16]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.081ns (logic 1.708ns (28.087%) route 4.373ns (71.913%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.574ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.837 13.081 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y197 FDCE r usb_inst/ft601_data_out_reg[16]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.429 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y197 FDCE r usb_inst/ft601_data_out_reg[16]/C
|
|
clock pessimism 0.000 14.574
|
|
clock uncertainty -0.061 14.513
|
|
OLOGIC_X0Y197 FDCE (Setup_fdce_C_CE) -0.331 14.182 usb_inst/ft601_data_out_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 14.182
|
|
arrival time -13.081
|
|
-------------------------------------------------------------------
|
|
slack 1.101
|
|
|
|
Slack (MET) : 1.135ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[17]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.047ns (logic 1.708ns (28.242%) route 4.339ns (71.758%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.574ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.803 13.047 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y196 FDCE r usb_inst/ft601_data_out_reg[17]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.429 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y196 FDCE r usb_inst/ft601_data_out_reg[17]/C
|
|
clock pessimism 0.000 14.574
|
|
clock uncertainty -0.061 14.513
|
|
OLOGIC_X0Y196 FDCE (Setup_fdce_C_CE) -0.331 14.182 usb_inst/ft601_data_out_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 14.182
|
|
arrival time -13.047
|
|
-------------------------------------------------------------------
|
|
slack 1.135
|
|
|
|
Slack (MET) : 1.172ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[30]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.996ns (logic 1.708ns (28.484%) route 4.288ns (71.516%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.560ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.560ns = ( 14.560 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.752 12.996 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y175 FDCE r usb_inst/ft601_data_out_reg[30]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.415 14.560 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y175 FDCE r usb_inst/ft601_data_out_reg[30]/C
|
|
clock pessimism 0.000 14.560
|
|
clock uncertainty -0.061 14.499
|
|
OLOGIC_X0Y175 FDCE (Setup_fdce_C_CE) -0.331 14.168 usb_inst/ft601_data_out_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 14.168
|
|
arrival time -12.996
|
|
-------------------------------------------------------------------
|
|
slack 1.172
|
|
|
|
Slack (MET) : 1.209ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[19]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.973ns (logic 1.708ns (28.594%) route 4.265ns (71.406%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.574ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.729 12.973 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y195 FDCE r usb_inst/ft601_data_out_reg[19]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.429 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y195 FDCE r usb_inst/ft601_data_out_reg[19]/C
|
|
clock pessimism 0.000 14.574
|
|
clock uncertainty -0.061 14.513
|
|
OLOGIC_X0Y195 FDCE (Setup_fdce_C_CE) -0.331 14.182 usb_inst/ft601_data_out_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 14.182
|
|
arrival time -12.973
|
|
-------------------------------------------------------------------
|
|
slack 1.209
|
|
|
|
Slack (MET) : 1.233ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[0]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.938ns (logic 1.708ns (28.765%) route 4.230ns (71.235%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.562ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.562ns = ( 14.562 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.693 12.938 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y179 FDCE r usb_inst/ft601_data_out_reg[0]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.417 14.562 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y179 FDCE r usb_inst/ft601_data_out_reg[0]/C
|
|
clock pessimism 0.000 14.562
|
|
clock uncertainty -0.061 14.501
|
|
OLOGIC_X0Y179 FDCE (Setup_fdce_C_CE) -0.331 14.170 usb_inst/ft601_data_out_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 14.170
|
|
arrival time -12.938
|
|
-------------------------------------------------------------------
|
|
slack 1.233
|
|
|
|
Slack (MET) : 1.235ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[22]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.945ns (logic 1.708ns (28.727%) route 4.237ns (71.273%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.701 12.945 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y192 FDCE r usb_inst/ft601_data_out_reg[22]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y192 FDCE r usb_inst/ft601_data_out_reg[22]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y192 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -12.945
|
|
-------------------------------------------------------------------
|
|
slack 1.235
|
|
|
|
Slack (MET) : 1.239ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[1]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.113ns (logic 1.591ns (26.031%) route 4.522ns (73.969%))
|
|
Logic Levels: 3 (IBUF=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.582ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.582ns = ( 14.582 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.995 12.376 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I0_O) 0.105 12.481 r usb_inst/byte_counter[7]_i_4/O
|
|
net (fo=1, routed) 0.240 12.721 usb_inst/byte_counter[7]_i_4_n_0
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.105 12.826 r usb_inst/byte_counter[7]_i_1/O
|
|
net (fo=8, routed) 0.288 13.113 usb_inst/byte_counter[7]_i_1_n_0
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.436 14.582 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[1]/C
|
|
clock pessimism 0.000 14.582
|
|
clock uncertainty -0.061 14.520
|
|
SLICE_X4Y184 FDCE (Setup_fdce_C_CE) -0.168 14.352 usb_inst/byte_counter_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.352
|
|
arrival time -13.113
|
|
-------------------------------------------------------------------
|
|
slack 1.239
|
|
|
|
Slack (MET) : 1.239ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[3]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.113ns (logic 1.591ns (26.031%) route 4.522ns (73.969%))
|
|
Logic Levels: 3 (IBUF=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.582ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.582ns = ( 14.582 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.995 12.376 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I0_O) 0.105 12.481 r usb_inst/byte_counter[7]_i_4/O
|
|
net (fo=1, routed) 0.240 12.721 usb_inst/byte_counter[7]_i_4_n_0
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.105 12.826 r usb_inst/byte_counter[7]_i_1/O
|
|
net (fo=8, routed) 0.288 13.113 usb_inst/byte_counter[7]_i_1_n_0
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[3]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.436 14.582 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[3]/C
|
|
clock pessimism 0.000 14.582
|
|
clock uncertainty -0.061 14.520
|
|
SLICE_X4Y184 FDCE (Setup_fdce_C_CE) -0.168 14.352 usb_inst/byte_counter_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.352
|
|
arrival time -13.113
|
|
-------------------------------------------------------------------
|
|
slack 1.239
|
|
|
|
Slack (MET) : 1.239ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[4]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.113ns (logic 1.591ns (26.031%) route 4.522ns (73.969%))
|
|
Logic Levels: 3 (IBUF=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.582ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.582ns = ( 14.582 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.995 12.376 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I0_O) 0.105 12.481 r usb_inst/byte_counter[7]_i_4/O
|
|
net (fo=1, routed) 0.240 12.721 usb_inst/byte_counter[7]_i_4_n_0
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.105 12.826 r usb_inst/byte_counter[7]_i_1/O
|
|
net (fo=8, routed) 0.288 13.113 usb_inst/byte_counter[7]_i_1_n_0
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[4]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.436 14.582 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[4]/C
|
|
clock pessimism 0.000 14.582
|
|
clock uncertainty -0.061 14.520
|
|
SLICE_X4Y184 FDCE (Setup_fdce_C_CE) -0.168 14.352 usb_inst/byte_counter_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 14.352
|
|
arrival time -13.113
|
|
-------------------------------------------------------------------
|
|
slack 1.239
|
|
|
|
Slack (MET) : 1.239ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[5]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.113ns (logic 1.591ns (26.031%) route 4.522ns (73.969%))
|
|
Logic Levels: 3 (IBUF=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.582ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.582ns = ( 14.582 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.995 12.376 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I0_O) 0.105 12.481 r usb_inst/byte_counter[7]_i_4/O
|
|
net (fo=1, routed) 0.240 12.721 usb_inst/byte_counter[7]_i_4_n_0
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.105 12.826 r usb_inst/byte_counter[7]_i_1/O
|
|
net (fo=8, routed) 0.288 13.113 usb_inst/byte_counter[7]_i_1_n_0
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[5]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.436 14.582 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[5]/C
|
|
clock pessimism 0.000 14.582
|
|
clock uncertainty -0.061 14.520
|
|
SLICE_X4Y184 FDCE (Setup_fdce_C_CE) -0.168 14.352 usb_inst/byte_counter_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 14.352
|
|
arrival time -13.113
|
|
-------------------------------------------------------------------
|
|
slack 1.239
|
|
|
|
Slack (MET) : 1.242ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[24]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.938ns (logic 1.708ns (28.762%) route 4.230ns (71.238%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.694 12.938 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y193 FDCE r usb_inst/ft601_data_out_reg[24]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y193 FDCE r usb_inst/ft601_data_out_reg[24]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y193 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -12.938
|
|
-------------------------------------------------------------------
|
|
slack 1.242
|
|
|
|
Slack (MET) : 1.245ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[0]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.142ns (logic 1.591ns (25.909%) route 4.551ns (74.091%))
|
|
Logic Levels: 3 (IBUF=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.585ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.585ns = ( 14.585 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.995 12.376 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I0_O) 0.105 12.481 r usb_inst/byte_counter[7]_i_4/O
|
|
net (fo=1, routed) 0.240 12.721 usb_inst/byte_counter[7]_i_4_n_0
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.105 12.826 r usb_inst/byte_counter[7]_i_1/O
|
|
net (fo=8, routed) 0.317 13.142 usb_inst/byte_counter[7]_i_1_n_0
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.439 14.585 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
clock pessimism 0.000 14.585
|
|
clock uncertainty -0.061 14.523
|
|
SLICE_X2Y184 FDCE (Setup_fdce_C_CE) -0.136 14.387 usb_inst/byte_counter_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 14.387
|
|
arrival time -13.142
|
|
-------------------------------------------------------------------
|
|
slack 1.245
|
|
|
|
Slack (MET) : 1.245ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[7]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.142ns (logic 1.591ns (25.909%) route 4.551ns (74.091%))
|
|
Logic Levels: 3 (IBUF=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.585ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.585ns = ( 14.585 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.995 12.376 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I0_O) 0.105 12.481 r usb_inst/byte_counter[7]_i_4/O
|
|
net (fo=1, routed) 0.240 12.721 usb_inst/byte_counter[7]_i_4_n_0
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.105 12.826 r usb_inst/byte_counter[7]_i_1/O
|
|
net (fo=8, routed) 0.317 13.142 usb_inst/byte_counter[7]_i_1_n_0
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[7]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.439 14.585 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[7]/C
|
|
clock pessimism 0.000 14.585
|
|
clock uncertainty -0.061 14.523
|
|
SLICE_X2Y184 FDCE (Setup_fdce_C_CE) -0.136 14.387 usb_inst/byte_counter_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 14.387
|
|
arrival time -13.142
|
|
-------------------------------------------------------------------
|
|
slack 1.245
|
|
|
|
Slack (MET) : 1.250ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[20]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.930ns (logic 1.708ns (28.801%) route 4.222ns (71.199%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.686 12.930 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y191 FDCE r usb_inst/ft601_data_out_reg[20]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y191 FDCE r usb_inst/ft601_data_out_reg[20]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y191 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -12.930
|
|
-------------------------------------------------------------------
|
|
slack 1.250
|
|
|
|
Slack (MET) : 1.253ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[25]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.927ns (logic 1.708ns (28.815%) route 4.219ns (71.185%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.683 12.927 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y194 FDCE r usb_inst/ft601_data_out_reg[25]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y194 FDCE r usb_inst/ft601_data_out_reg[25]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y194 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -12.927
|
|
-------------------------------------------------------------------
|
|
slack 1.253
|
|
|
|
Slack (MET) : 1.270ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_sequential_current_state_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.327ns (logic 1.696ns (26.811%) route 4.631ns (73.189%))
|
|
Logic Levels: 4 (IBUF=1 LUT3=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.585ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.585ns = ( 14.585 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.671 12.052 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X1Y183 LUT3 (Prop_lut3_I2_O) 0.105 12.157 f usb_inst/FSM_sequential_current_state[2]_i_6/O
|
|
net (fo=4, routed) 0.494 12.652 usb_inst/FSM_sequential_current_state[2]_i_6_n_0
|
|
SLICE_X3Y182 LUT6 (Prop_lut6_I0_O) 0.105 12.757 r usb_inst/FSM_sequential_current_state[1]_i_5/O
|
|
net (fo=2, routed) 0.465 13.222 usb_inst/FSM_sequential_current_state[1]_i_5_n_0
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I4_O) 0.105 13.327 r usb_inst/FSM_sequential_current_state[0]_i_1/O
|
|
net (fo=1, routed) 0.000 13.327 usb_inst/FSM_sequential_current_state[0]_i_1_n_0
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.439 14.585 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
clock pessimism 0.000 14.585
|
|
clock uncertainty -0.061 14.523
|
|
SLICE_X2Y183 FDCE (Setup_fdce_C_D) 0.074 14.597 usb_inst/FSM_sequential_current_state_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 14.597
|
|
arrival time -13.327
|
|
-------------------------------------------------------------------
|
|
slack 1.270
|
|
|
|
Slack (MET) : 1.290ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[2]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.099ns (logic 1.591ns (26.093%) route 4.507ns (73.907%))
|
|
Logic Levels: 3 (IBUF=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.586ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.586ns = ( 14.586 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.995 12.376 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I0_O) 0.105 12.481 r usb_inst/byte_counter[7]_i_4/O
|
|
net (fo=1, routed) 0.240 12.721 usb_inst/byte_counter[7]_i_4_n_0
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.105 12.826 r usb_inst/byte_counter[7]_i_1/O
|
|
net (fo=8, routed) 0.273 13.099 usb_inst/byte_counter[7]_i_1_n_0
|
|
SLICE_X2Y185 FDCE r usb_inst/byte_counter_reg[2]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.440 14.586 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y185 FDCE r usb_inst/byte_counter_reg[2]/C
|
|
clock pessimism 0.000 14.586
|
|
clock uncertainty -0.061 14.524
|
|
SLICE_X2Y185 FDCE (Setup_fdce_C_CE) -0.136 14.388 usb_inst/byte_counter_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 14.388
|
|
arrival time -13.099
|
|
-------------------------------------------------------------------
|
|
slack 1.290
|
|
|
|
Slack (MET) : 1.299ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[13]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.881ns (logic 1.708ns (29.042%) route 4.173ns (70.958%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.572ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.393 8.393 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 3.038 11.431 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.105 11.536 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.387 11.922 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.027 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.112 12.139 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.105 12.244 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.637 12.881 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y190 FDCE r usb_inst/ft601_data_out_reg[13]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y190 FDCE r usb_inst/ft601_data_out_reg[13]/C
|
|
clock pessimism 0.000 14.572
|
|
clock uncertainty -0.061 14.511
|
|
OLOGIC_X0Y190 FDCE (Setup_fdce_C_CE) -0.331 14.180 usb_inst/ft601_data_out_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 14.180
|
|
arrival time -12.881
|
|
-------------------------------------------------------------------
|
|
slack 1.299
|
|
|
|
Slack (MET) : 1.334ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[2]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.136ns (logic 0.586ns (18.676%) route 2.550ns (81.324%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.590ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.590ns = ( 11.590 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.881 9.298 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.056 9.354 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.211 9.565 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.056 9.621 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.057 9.678 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.056 9.734 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.402 10.136 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y180 FDCE r usb_inst/ft601_data_out_reg[2]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 11.590 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y180 FDCE r usb_inst/ft601_data_out_reg[2]/C
|
|
clock pessimism 0.000 11.590
|
|
clock uncertainty -0.061 11.529
|
|
OLOGIC_X0Y180 FDCE (Setup_fdce_C_CE) -0.059 11.470 usb_inst/ft601_data_out_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 11.470
|
|
arrival time -10.136
|
|
-------------------------------------------------------------------
|
|
slack 1.334
|
|
|
|
Slack (MET) : 1.337ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[15]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.138ns (logic 0.586ns (18.663%) route 2.552ns (81.337%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.595ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.595ns = ( 11.595 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.881 9.298 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.056 9.354 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.211 9.565 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.056 9.621 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.057 9.678 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.056 9.734 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.404 10.138 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y189 FDCE r usb_inst/ft601_data_out_reg[15]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 11.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y189 FDCE r usb_inst/ft601_data_out_reg[15]/C
|
|
clock pessimism 0.000 11.595
|
|
clock uncertainty -0.061 11.534
|
|
OLOGIC_X0Y189 FDCE (Setup_fdce_C_CE) -0.059 11.475 usb_inst/ft601_data_out_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 11.475
|
|
arrival time -10.138
|
|
-------------------------------------------------------------------
|
|
slack 1.337
|
|
|
|
Slack (MET) : 1.366ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_sequential_current_state_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.229ns (logic 1.696ns (27.234%) route 4.533ns (72.767%))
|
|
Logic Levels: 4 (IBUF=1 LUT3=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.585ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.585ns = ( 14.585 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.671 12.052 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X1Y183 LUT3 (Prop_lut3_I2_O) 0.105 12.157 f usb_inst/FSM_sequential_current_state[2]_i_6/O
|
|
net (fo=4, routed) 0.494 12.652 usb_inst/FSM_sequential_current_state[2]_i_6_n_0
|
|
SLICE_X3Y182 LUT6 (Prop_lut6_I0_O) 0.105 12.757 r usb_inst/FSM_sequential_current_state[1]_i_5/O
|
|
net (fo=2, routed) 0.367 13.124 usb_inst/FSM_sequential_current_state[1]_i_5_n_0
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I4_O) 0.105 13.229 r usb_inst/FSM_sequential_current_state[1]_i_1/O
|
|
net (fo=1, routed) 0.000 13.229 usb_inst/FSM_sequential_current_state[1]_i_1_n_0
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.439 14.585 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[1]/C
|
|
clock pessimism 0.000 14.585
|
|
clock uncertainty -0.061 14.523
|
|
SLICE_X2Y183 FDCE (Setup_fdce_C_D) 0.072 14.595 usb_inst/FSM_sequential_current_state_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.595
|
|
arrival time -13.229
|
|
-------------------------------------------------------------------
|
|
slack 1.366
|
|
|
|
Slack (MET) : 1.376ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_wr_n_reg/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.842ns (logic 0.474ns (16.663%) route 2.369ns (83.337%))
|
|
Logic Levels: 2 (IBUF=1 LUT4=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.683ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.683ns = ( 11.683 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 r ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 r ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.367 8.784 usb_inst/ft601_txe_IBUF
|
|
SLICE_X0Y195 LUT4 (Prop_lut4_I0_O) 0.056 8.840 r usb_inst/ft601_wr_n_i_2/O
|
|
net (fo=1, routed) 1.002 9.842 usb_inst/ft601_wr_n_i_2_n_0
|
|
OLOGIC_X0Y242 FDPE r usb_inst/ft601_wr_n_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.730 11.683 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y242 FDPE r usb_inst/ft601_wr_n_reg/C
|
|
clock pessimism 0.000 11.683
|
|
clock uncertainty -0.061 11.622
|
|
OLOGIC_X0Y242 FDPE (Setup_fdpe_C_D) -0.404 11.218 usb_inst/ft601_wr_n_reg
|
|
-------------------------------------------------------------------
|
|
required time 11.218
|
|
arrival time -9.842
|
|
-------------------------------------------------------------------
|
|
slack 1.376
|
|
|
|
Slack (MET) : 1.381ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[10]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.093ns (logic 0.586ns (18.932%) route 2.508ns (81.068%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.595ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.595ns = ( 11.595 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.881 9.298 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.056 9.354 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.211 9.565 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.056 9.621 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.057 9.678 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.056 9.734 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.359 10.093 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y188 FDCE r usb_inst/ft601_data_out_reg[10]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 11.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y188 FDCE r usb_inst/ft601_data_out_reg[10]/C
|
|
clock pessimism 0.000 11.595
|
|
clock uncertainty -0.061 11.534
|
|
OLOGIC_X0Y188 FDCE (Setup_fdce_C_CE) -0.059 11.475 usb_inst/ft601_data_out_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 11.475
|
|
arrival time -10.093
|
|
-------------------------------------------------------------------
|
|
slack 1.381
|
|
|
|
Slack (MET) : 1.382ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[3]/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.836ns (logic 0.474ns (16.700%) route 2.362ns (83.300%))
|
|
Logic Levels: 2 (IBUF=1 LUT4=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.683ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.683ns = ( 11.683 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.430 8.847 usb_inst/ft601_txe_IBUF
|
|
SLICE_X0Y194 LUT4 (Prop_lut4_I1_O) 0.056 8.903 r usb_inst/ft601_be[3]_i_2/O
|
|
net (fo=3, routed) 0.933 9.836 usb_inst/ft601_be[3]_i_2_n_0
|
|
OLOGIC_X0Y240 FDPE r usb_inst/ft601_be_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.730 11.683 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y240 FDPE r usb_inst/ft601_be_reg[3]/C
|
|
clock pessimism 0.000 11.683
|
|
clock uncertainty -0.061 11.622
|
|
OLOGIC_X0Y240 FDPE (Setup_fdpe_C_D) -0.404 11.218 usb_inst/ft601_be_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 11.218
|
|
arrival time -9.836
|
|
-------------------------------------------------------------------
|
|
slack 1.382
|
|
|
|
Slack (MET) : 1.384ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_oe_reg/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.172ns (logic 0.586ns (18.462%) route 2.586ns (81.538%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT3=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.604ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.604ns = ( 11.604 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 r ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 r ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.881 9.298 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.056 9.354 r usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.356 9.711 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X0Y186 LUT6 (Prop_lut6_I2_O) 0.056 9.767 f usb_inst/ft601_be[3]_i_1/O
|
|
net (fo=5, routed) 0.349 10.116 usb_inst/ft601_be[3]_i_1_n_0
|
|
SLICE_X0Y195 LUT3 (Prop_lut3_I1_O) 0.056 10.172 r usb_inst/ft601_data_oe_i_1/O
|
|
net (fo=1, routed) 0.000 10.172 usb_inst/ft601_data_oe_i_1_n_0
|
|
SLICE_X0Y195 FDPE r usb_inst/ft601_data_oe_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.651 11.604 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y195 FDPE r usb_inst/ft601_data_oe_reg/C
|
|
clock pessimism 0.000 11.604
|
|
clock uncertainty -0.061 11.543
|
|
SLICE_X0Y195 FDPE (Setup_fdpe_C_D) 0.013 11.556 usb_inst/ft601_data_oe_reg
|
|
-------------------------------------------------------------------
|
|
required time 11.556
|
|
arrival time -10.172
|
|
-------------------------------------------------------------------
|
|
slack 1.384
|
|
|
|
Slack (MET) : 1.387ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[2]/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.831ns (logic 0.474ns (16.728%) route 2.358ns (83.272%))
|
|
Logic Levels: 2 (IBUF=1 LUT4=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.683ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.683ns = ( 11.683 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.430 8.847 usb_inst/ft601_txe_IBUF
|
|
SLICE_X0Y194 LUT4 (Prop_lut4_I1_O) 0.056 8.903 r usb_inst/ft601_be[3]_i_2/O
|
|
net (fo=3, routed) 0.928 9.831 usb_inst/ft601_be[3]_i_2_n_0
|
|
OLOGIC_X0Y239 FDPE r usb_inst/ft601_be_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.730 11.683 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y239 FDPE r usb_inst/ft601_be_reg[2]/C
|
|
clock pessimism 0.000 11.683
|
|
clock uncertainty -0.061 11.622
|
|
OLOGIC_X0Y239 FDPE (Setup_fdpe_C_D) -0.404 11.218 usb_inst/ft601_be_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 11.218
|
|
arrival time -9.831
|
|
-------------------------------------------------------------------
|
|
slack 1.387
|
|
|
|
Slack (MET) : 1.431ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[8]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.043ns (logic 0.586ns (19.243%) route 2.458ns (80.757%))
|
|
Logic Levels: 4 (IBUF=1 LUT2=1 LUT6=2)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.595ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.595ns = ( 11.595 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.881 9.298 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.056 9.354 f usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.211 9.565 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.056 9.621 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.057 9.678 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.056 9.734 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.309 10.043 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y187 FDCE r usb_inst/ft601_data_out_reg[8]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 11.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y187 FDCE r usb_inst/ft601_data_out_reg[8]/C
|
|
clock pessimism 0.000 11.595
|
|
clock uncertainty -0.061 11.534
|
|
OLOGIC_X0Y187 FDCE (Setup_fdce_C_CE) -0.059 11.475 usb_inst/ft601_data_out_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 11.475
|
|
arrival time -10.043
|
|
-------------------------------------------------------------------
|
|
slack 1.431
|
|
|
|
Slack (MET) : 1.439ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_rd_n_reg/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.689ns (logic 0.467ns (17.374%) route 2.221ns (82.626%))
|
|
Logic Levels: 2 (IBUF=1 LUT3=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.676ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.676ns = ( 11.676 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 1.715 9.121 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X0Y209 LUT3 (Prop_lut3_I0_O) 0.061 9.182 r usb_inst/ft601_rd_n_i_2/O
|
|
net (fo=1, routed) 0.506 9.689 usb_inst/ft601_rd_n_i_2_n_0
|
|
OLOGIC_X0Y226 FDPE r usb_inst/ft601_rd_n_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.723 11.676 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y226 FDPE r usb_inst/ft601_rd_n_reg/C
|
|
clock pessimism 0.000 11.676
|
|
clock uncertainty -0.061 11.615
|
|
OLOGIC_X0Y226 FDPE (Setup_fdpe_C_D) -0.488 11.127 usb_inst/ft601_rd_n_reg
|
|
-------------------------------------------------------------------
|
|
required time 11.127
|
|
arrival time -9.689
|
|
-------------------------------------------------------------------
|
|
slack 1.439
|
|
|
|
Slack (MET) : 1.477ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_rd_n_reg/CE
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.857ns (logic 1.486ns (25.379%) route 4.370ns (74.621%))
|
|
Logic Levels: 2 (IBUF=1 LUT3=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.726ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.726ns = ( 14.726 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 f ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 f ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.031 11.413 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X0Y209 LUT3 (Prop_lut3_I0_O) 0.105 11.518 r usb_inst/ft601_rd_n_i_1/O
|
|
net (fo=1, routed) 1.339 12.857 usb_inst/ft601_rd_n_i_1_n_0
|
|
OLOGIC_X0Y226 FDPE r usb_inst/ft601_rd_n_reg/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.581 14.726 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y226 FDPE r usb_inst/ft601_rd_n_reg/C
|
|
clock pessimism 0.000 14.726
|
|
clock uncertainty -0.061 14.665
|
|
OLOGIC_X0Y226 FDPE (Setup_fdpe_C_CE) -0.331 14.334 usb_inst/ft601_rd_n_reg
|
|
-------------------------------------------------------------------
|
|
required time 14.334
|
|
arrival time -12.857
|
|
-------------------------------------------------------------------
|
|
slack 1.477
|
|
|
|
Slack (MET) : 1.480ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_sequential_current_state_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.119ns (logic 1.696ns (27.722%) route 4.423ns (72.278%))
|
|
Logic Levels: 4 (IBUF=1 LUT3=1 LUT5=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 4.585ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.585ns = ( 14.585 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 1.381 8.381 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 3.671 12.052 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X1Y183 LUT3 (Prop_lut3_I2_O) 0.105 12.157 f usb_inst/FSM_sequential_current_state[2]_i_6/O
|
|
net (fo=4, routed) 0.520 12.678 usb_inst/FSM_sequential_current_state[2]_i_6_n_0
|
|
SLICE_X2Y182 LUT5 (Prop_lut5_I0_O) 0.105 12.783 r usb_inst/FSM_sequential_current_state[2]_i_4/O
|
|
net (fo=1, routed) 0.232 13.014 usb_inst/FSM_sequential_current_state[2]_i_4_n_0
|
|
SLICE_X2Y183 LUT6 (Prop_lut6_I4_O) 0.105 13.119 r usb_inst/FSM_sequential_current_state[2]_i_1/O
|
|
net (fo=1, routed) 0.000 13.119 usb_inst/FSM_sequential_current_state[2]_i_1_n_0
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.439 14.585 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[2]/C
|
|
clock pessimism 0.000 14.585
|
|
clock uncertainty -0.061 14.523
|
|
SLICE_X2Y183 FDCE (Setup_fdce_C_D) 0.076 14.599 usb_inst/FSM_sequential_current_state_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 14.599
|
|
arrival time -13.119
|
|
-------------------------------------------------------------------
|
|
slack 1.480
|
|
|
|
Slack (MET) : 1.582ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[0]/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.555ns (logic 0.478ns (18.691%) route 2.078ns (81.309%))
|
|
Logic Levels: 2 (IBUF=1 LUT4=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.680ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.680ns = ( 11.680 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.430 8.847 usb_inst/ft601_txe_IBUF
|
|
SLICE_X0Y194 LUT4 (Prop_lut4_I0_O) 0.060 8.907 r usb_inst/ft601_be[0]_i_1/O
|
|
net (fo=1, routed) 0.648 9.555 usb_inst/ft601_be[0]_i_1_n_0
|
|
OLOGIC_X0Y218 FDPE r usb_inst/ft601_be_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.727 11.680 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y218 FDPE r usb_inst/ft601_be_reg[0]/C
|
|
clock pessimism 0.000 11.680
|
|
clock uncertainty -0.061 11.619
|
|
OLOGIC_X0Y218 FDPE (Setup_fdpe_C_D) -0.482 11.137 usb_inst/ft601_be_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 11.137
|
|
arrival time -9.555
|
|
-------------------------------------------------------------------
|
|
slack 1.582
|
|
|
|
Slack (MET) : 1.602ns (required time - arrival time)
|
|
Source: ft601_data[28]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[28]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.917ns (logic 0.413ns (14.144%) route 2.504ns (85.856%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.591ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.591ns = ( 11.591 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
K14 0.000 7.000 r ft601_data[28] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[28]_inst/IO
|
|
K14 IBUF (Prop_ibuf_I_O) 0.413 7.413 r ft601_data_IOBUF[28]_inst/IBUF/O
|
|
net (fo=1, routed) 2.504 9.917 usb_inst/rx_data_captured_reg[31]_0[7]
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 11.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[28]/C
|
|
clock pessimism 0.000 11.591
|
|
clock uncertainty -0.061 11.530
|
|
SLICE_X0Y174 FDCE (Setup_fdce_C_D) -0.011 11.519 usb_inst/rx_data_captured_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 11.519
|
|
arrival time -9.917
|
|
-------------------------------------------------------------------
|
|
slack 1.602
|
|
|
|
Slack (MET) : 1.656ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[7]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.917ns (logic 0.474ns (16.237%) route 2.443ns (83.763%))
|
|
Logic Levels: 2 (IBUF=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.600ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.600ns = ( 11.600 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 2.443 9.861 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y184 LUT6 (Prop_lut6_I2_O) 0.056 9.917 r usb_inst/byte_counter[7]_i_2/O
|
|
net (fo=1, routed) 0.000 9.917 usb_inst/byte_counter[7]
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 11.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[7]/C
|
|
clock pessimism 0.000 11.600
|
|
clock uncertainty -0.061 11.539
|
|
SLICE_X2Y184 FDCE (Setup_fdce_C_D) 0.034 11.573 usb_inst/byte_counter_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time 11.573
|
|
arrival time -9.917
|
|
-------------------------------------------------------------------
|
|
slack 1.656
|
|
|
|
Slack (MET) : 1.659ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[1]/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.556ns (logic 0.474ns (18.530%) route 2.082ns (81.470%))
|
|
Logic Levels: 2 (IBUF=1 LUT4=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.680ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.680ns = ( 11.680 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.430 8.847 usb_inst/ft601_txe_IBUF
|
|
SLICE_X0Y194 LUT4 (Prop_lut4_I1_O) 0.056 8.903 r usb_inst/ft601_be[3]_i_2/O
|
|
net (fo=3, routed) 0.652 9.556 usb_inst/ft601_be[3]_i_2_n_0
|
|
OLOGIC_X0Y217 FDPE r usb_inst/ft601_be_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.727 11.680 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y217 FDPE r usb_inst/ft601_be_reg[1]/C
|
|
clock pessimism 0.000 11.680
|
|
clock uncertainty -0.061 11.619
|
|
OLOGIC_X0Y217 FDPE (Setup_fdpe_C_D) -0.404 11.215 usb_inst/ft601_be_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 11.215
|
|
arrival time -9.556
|
|
-------------------------------------------------------------------
|
|
slack 1.659
|
|
|
|
Slack (MET) : 1.697ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.877ns (logic 0.474ns (16.461%) route 2.404ns (83.539%))
|
|
Logic Levels: 2 (IBUF=1 LUT5=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.600ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.600ns = ( 11.600 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 2.404 9.821 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y184 LUT5 (Prop_lut5_I1_O) 0.056 9.877 r usb_inst/byte_counter[0]_i_1/O
|
|
net (fo=1, routed) 0.000 9.877 usb_inst/byte_counter[0]
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 11.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
clock pessimism 0.000 11.600
|
|
clock uncertainty -0.061 11.539
|
|
SLICE_X2Y184 FDCE (Setup_fdce_C_D) 0.035 11.574 usb_inst/byte_counter_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 11.574
|
|
arrival time -9.877
|
|
-------------------------------------------------------------------
|
|
slack 1.697
|
|
|
|
Slack (MET) : 1.712ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_data_pending_reg/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.860ns (logic 0.474ns (16.558%) route 2.387ns (83.442%))
|
|
Logic Levels: 2 (IBUF=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.600ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.600ns = ( 11.600 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 r ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 r ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 2.387 9.804 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y186 LUT6 (Prop_lut6_I3_O) 0.056 9.860 r usb_inst/doppler_data_pending_i_1/O
|
|
net (fo=1, routed) 0.000 9.860 usb_inst/doppler_data_pending_i_1_n_0
|
|
SLICE_X2Y186 FDCE r usb_inst/doppler_data_pending_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 11.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y186 FDCE r usb_inst/doppler_data_pending_reg/C
|
|
clock pessimism 0.000 11.600
|
|
clock uncertainty -0.061 11.539
|
|
SLICE_X2Y186 FDCE (Setup_fdce_C_D) 0.034 11.573 usb_inst/doppler_data_pending_reg
|
|
-------------------------------------------------------------------
|
|
required time 11.573
|
|
arrival time -9.860
|
|
-------------------------------------------------------------------
|
|
slack 1.712
|
|
|
|
Slack (MET) : 1.735ns (required time - arrival time)
|
|
Source: ft601_data[1]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.752ns (logic 0.439ns (15.970%) route 2.312ns (84.030%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.591ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.591ns = ( 11.591 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
N20 0.000 7.000 r ft601_data[1] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[1]_inst/IO
|
|
N20 IBUF (Prop_ibuf_I_O) 0.439 7.439 r ft601_data_IOBUF[1]_inst/IBUF/O
|
|
net (fo=1, routed) 2.312 9.752 usb_inst/rx_data_captured_reg[31]_0[1]
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 11.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[1]/C
|
|
clock pessimism 0.000 11.591
|
|
clock uncertainty -0.061 11.530
|
|
SLICE_X0Y174 FDCE (Setup_fdce_C_D) -0.043 11.487 usb_inst/rx_data_captured_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 11.487
|
|
arrival time -9.752
|
|
-------------------------------------------------------------------
|
|
slack 1.735
|
|
|
|
Slack (MET) : 1.745ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.900ns (logic 0.462ns (15.934%) route 2.438ns (84.066%))
|
|
Logic Levels: 2 (IBUF=1 LUT2=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.692ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.692ns = ( 11.692 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 f ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 f ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 2.438 9.844 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X0Y209 LUT2 (Prop_lut2_I1_O) 0.056 9.900 r usb_inst/FSM_onehot_read_state[2]_i_1/O
|
|
net (fo=1, routed) 0.000 9.900 usb_inst/FSM_onehot_read_state[2]_i_1_n_0
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 11.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[2]/C
|
|
clock pessimism 0.000 11.692
|
|
clock uncertainty -0.061 11.631
|
|
SLICE_X0Y209 FDCE (Setup_fdce_C_D) 0.014 11.645 usb_inst/FSM_onehot_read_state_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 11.645
|
|
arrival time -9.900
|
|
-------------------------------------------------------------------
|
|
slack 1.745
|
|
|
|
Slack (MET) : 1.753ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[0]/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.891ns (logic 0.462ns (15.984%) route 2.429ns (84.016%))
|
|
Logic Levels: 2 (IBUF=1 LUT3=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.692ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.692ns = ( 11.692 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 2.429 9.835 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X0Y209 LUT3 (Prop_lut3_I0_O) 0.056 9.891 r usb_inst/FSM_onehot_read_state[0]_i_1/O
|
|
net (fo=1, routed) 0.000 9.891 usb_inst/FSM_onehot_read_state[0]_i_1_n_0
|
|
SLICE_X0Y209 FDPE r usb_inst/FSM_onehot_read_state_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 11.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDPE r usb_inst/FSM_onehot_read_state_reg[0]/C
|
|
clock pessimism 0.000 11.692
|
|
clock uncertainty -0.061 11.631
|
|
SLICE_X0Y209 FDPE (Setup_fdpe_C_D) 0.013 11.644 usb_inst/FSM_onehot_read_state_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 11.644
|
|
arrival time -9.891
|
|
-------------------------------------------------------------------
|
|
slack 1.753
|
|
|
|
Slack (MET) : 1.780ns (required time - arrival time)
|
|
Source: ft601_data[26]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[26]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.707ns (logic 0.447ns (16.522%) route 2.260ns (83.478%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.591ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.591ns = ( 11.591 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
N18 0.000 7.000 r ft601_data[26] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[26]_inst/IO
|
|
N18 IBUF (Prop_ibuf_I_O) 0.447 7.447 r ft601_data_IOBUF[26]_inst/IBUF/O
|
|
net (fo=1, routed) 2.260 9.707 usb_inst/rx_data_captured_reg[31]_0[5]
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[26]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 11.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[26]/C
|
|
clock pessimism 0.000 11.591
|
|
clock uncertainty -0.061 11.530
|
|
SLICE_X0Y174 FDCE (Setup_fdce_C_D) -0.042 11.488 usb_inst/rx_data_captured_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time 11.488
|
|
arrival time -9.707
|
|
-------------------------------------------------------------------
|
|
slack 1.780
|
|
|
|
Slack (MET) : 1.800ns (required time - arrival time)
|
|
Source: ft601_data[27]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[27]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.688ns (logic 0.439ns (16.320%) route 2.249ns (83.680%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.591ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.591ns = ( 11.591 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
N19 0.000 7.000 r ft601_data[27] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[27]_inst/IO
|
|
N19 IBUF (Prop_ibuf_I_O) 0.439 7.439 r ft601_data_IOBUF[27]_inst/IBUF/O
|
|
net (fo=1, routed) 2.249 9.688 usb_inst/rx_data_captured_reg[31]_0[6]
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[27]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 11.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[27]/C
|
|
clock pessimism 0.000 11.591
|
|
clock uncertainty -0.061 11.530
|
|
SLICE_X0Y174 FDCE (Setup_fdce_C_D) -0.042 11.488 usb_inst/rx_data_captured_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 11.488
|
|
arrival time -9.688
|
|
-------------------------------------------------------------------
|
|
slack 1.800
|
|
|
|
Slack (MET) : 1.823ns (required time - arrival time)
|
|
Source: ft601_data[31]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[31]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.703ns (logic 0.415ns (15.339%) route 2.288ns (84.661%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.591ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.591ns = ( 11.591 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
J19 0.000 7.000 r ft601_data[31] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[31]_inst/IO
|
|
J19 IBUF (Prop_ibuf_I_O) 0.415 7.415 r ft601_data_IOBUF[31]_inst/IBUF/O
|
|
net (fo=1, routed) 2.288 9.703 usb_inst/rx_data_captured_reg[31]_0[10]
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 11.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[31]/C
|
|
clock pessimism 0.000 11.591
|
|
clock uncertainty -0.061 11.530
|
|
SLICE_X0Y174 FDCE (Setup_fdce_C_D) -0.004 11.526 usb_inst/rx_data_captured_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time 11.526
|
|
arrival time -9.703
|
|
-------------------------------------------------------------------
|
|
slack 1.823
|
|
|
|
Slack (MET) : 1.842ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_oe_n_reg/CE
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.714ns (logic 0.462ns (17.026%) route 2.252ns (82.974%))
|
|
Logic Levels: 2 (IBUF=1 LUT4=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.676ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.676ns = ( 11.676 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 r ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 r ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 1.753 9.159 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X0Y209 LUT4 (Prop_lut4_I3_O) 0.056 9.215 r usb_inst/ft601_oe_n_i_1/O
|
|
net (fo=1, routed) 0.499 9.714 usb_inst/ft601_oe_n_i_1_n_0
|
|
OLOGIC_X0Y225 FDPE r usb_inst/ft601_oe_n_reg/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.723 11.676 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y225 FDPE r usb_inst/ft601_oe_n_reg/C
|
|
clock pessimism 0.000 11.676
|
|
clock uncertainty -0.061 11.615
|
|
OLOGIC_X0Y225 FDPE (Setup_fdpe_C_CE) -0.059 11.556 usb_inst/ft601_oe_n_reg
|
|
-------------------------------------------------------------------
|
|
required time 11.556
|
|
arrival time -9.714
|
|
-------------------------------------------------------------------
|
|
slack 1.842
|
|
|
|
Slack (MET) : 1.853ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_data_pending_reg/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.698ns (logic 0.530ns (19.630%) route 2.168ns (80.370%))
|
|
Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.599ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.599ns = ( 11.599 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 r ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 r ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.881 9.298 usb_inst/ft601_txe_IBUF
|
|
SLICE_X1Y186 LUT2 (Prop_lut2_I0_O) 0.056 9.354 r usb_inst/ft601_be[3]_i_3/O
|
|
net (fo=4, routed) 0.288 9.642 usb_inst/ft601_be[3]_i_3_n_0
|
|
SLICE_X0Y183 LUT6 (Prop_lut6_I4_O) 0.056 9.698 r usb_inst/cfar_data_pending_i_1/O
|
|
net (fo=1, routed) 0.000 9.698 usb_inst/cfar_data_pending_i_1_n_0
|
|
SLICE_X0Y183 FDCE r usb_inst/cfar_data_pending_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.646 11.599 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y183 FDCE r usb_inst/cfar_data_pending_reg/C
|
|
clock pessimism 0.000 11.599
|
|
clock uncertainty -0.061 11.538
|
|
SLICE_X0Y183 FDCE (Setup_fdce_C_D) 0.013 11.551 usb_inst/cfar_data_pending_reg
|
|
-------------------------------------------------------------------
|
|
required time 11.551
|
|
arrival time -9.698
|
|
-------------------------------------------------------------------
|
|
slack 1.853
|
|
|
|
Slack (MET) : 1.859ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[0]/CE
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.714ns (logic 0.462ns (17.027%) route 2.252ns (82.974%))
|
|
Logic Levels: 2 (IBUF=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.692ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.692ns = ( 11.692 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 f ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 f ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 1.754 9.161 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X1Y202 LUT6 (Prop_lut6_I0_O) 0.056 9.217 r usb_inst/FSM_onehot_read_state[4]_i_1/O
|
|
net (fo=5, routed) 0.497 9.714 usb_inst/FSM_onehot_read_state[4]_i_1_n_0
|
|
SLICE_X0Y209 FDPE r usb_inst/FSM_onehot_read_state_reg[0]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 11.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDPE r usb_inst/FSM_onehot_read_state_reg[0]/C
|
|
clock pessimism 0.000 11.692
|
|
clock uncertainty -0.061 11.631
|
|
SLICE_X0Y209 FDPE (Setup_fdpe_C_CE) -0.058 11.573 usb_inst/FSM_onehot_read_state_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 11.573
|
|
arrival time -9.714
|
|
-------------------------------------------------------------------
|
|
slack 1.859
|
|
|
|
Slack (MET) : 1.859ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[2]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.714ns (logic 0.462ns (17.027%) route 2.252ns (82.974%))
|
|
Logic Levels: 2 (IBUF=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.692ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.692ns = ( 11.692 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 f ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 f ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 1.754 9.161 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X1Y202 LUT6 (Prop_lut6_I0_O) 0.056 9.217 r usb_inst/FSM_onehot_read_state[4]_i_1/O
|
|
net (fo=5, routed) 0.497 9.714 usb_inst/FSM_onehot_read_state[4]_i_1_n_0
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[2]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 11.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[2]/C
|
|
clock pessimism 0.000 11.692
|
|
clock uncertainty -0.061 11.631
|
|
SLICE_X0Y209 FDCE (Setup_fdce_C_CE) -0.058 11.573 usb_inst/FSM_onehot_read_state_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 11.573
|
|
arrival time -9.714
|
|
-------------------------------------------------------------------
|
|
slack 1.859
|
|
|
|
Slack (MET) : 1.859ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[3]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.714ns (logic 0.462ns (17.027%) route 2.252ns (82.974%))
|
|
Logic Levels: 2 (IBUF=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.692ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.692ns = ( 11.692 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 f ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 f ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 1.754 9.161 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X1Y202 LUT6 (Prop_lut6_I0_O) 0.056 9.217 r usb_inst/FSM_onehot_read_state[4]_i_1/O
|
|
net (fo=5, routed) 0.497 9.714 usb_inst/FSM_onehot_read_state[4]_i_1_n_0
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[3]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 11.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[3]/C
|
|
clock pessimism 0.000 11.692
|
|
clock uncertainty -0.061 11.631
|
|
SLICE_X0Y209 FDCE (Setup_fdce_C_CE) -0.058 11.573 usb_inst/FSM_onehot_read_state_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 11.573
|
|
arrival time -9.714
|
|
-------------------------------------------------------------------
|
|
slack 1.859
|
|
|
|
Slack (MET) : 1.859ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[4]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.714ns (logic 0.462ns (17.027%) route 2.252ns (82.974%))
|
|
Logic Levels: 2 (IBUF=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.692ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.692ns = ( 11.692 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 f ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 f ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 1.754 9.161 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X1Y202 LUT6 (Prop_lut6_I0_O) 0.056 9.217 r usb_inst/FSM_onehot_read_state[4]_i_1/O
|
|
net (fo=5, routed) 0.497 9.714 usb_inst/FSM_onehot_read_state[4]_i_1_n_0
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[4]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 11.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[4]/C
|
|
clock pessimism 0.000 11.692
|
|
clock uncertainty -0.061 11.631
|
|
SLICE_X0Y209 FDCE (Setup_fdce_C_CE) -0.058 11.573 usb_inst/FSM_onehot_read_state_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 11.573
|
|
arrival time -9.714
|
|
-------------------------------------------------------------------
|
|
slack 1.859
|
|
|
|
Slack (MET) : 1.875ns (required time - arrival time)
|
|
Source: ft601_data[29]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[29]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.650ns (logic 0.417ns (15.740%) route 2.233ns (84.260%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.591ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.591ns = ( 11.591 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
K13 0.000 7.000 r ft601_data[29] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[29]_inst/IO
|
|
K13 IBUF (Prop_ibuf_I_O) 0.417 7.417 r ft601_data_IOBUF[29]_inst/IBUF/O
|
|
net (fo=1, routed) 2.233 9.650 usb_inst/rx_data_captured_reg[31]_0[8]
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[29]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 11.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[29]/C
|
|
clock pessimism 0.000 11.591
|
|
clock uncertainty -0.061 11.530
|
|
SLICE_X0Y174 FDCE (Setup_fdce_C_D) -0.005 11.525 usb_inst/rx_data_captured_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 11.525
|
|
arrival time -9.650
|
|
-------------------------------------------------------------------
|
|
slack 1.875
|
|
|
|
Slack (MET) : 1.884ns (required time - arrival time)
|
|
Source: ft601_rxf
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[1]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.689ns (logic 0.462ns (17.182%) route 2.227ns (82.818%))
|
|
Logic Levels: 2 (IBUF=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.692ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.692ns = ( 11.692 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
F16 0.000 7.000 f ft601_rxf (IN)
|
|
net (fo=0) 0.000 7.000 ft601_rxf
|
|
F16 IBUF (Prop_ibuf_I_O) 0.406 7.406 f ft601_rxf_IBUF_inst/O
|
|
net (fo=10, routed) 1.754 9.161 usb_inst/ft601_rxf_IBUF
|
|
SLICE_X1Y202 LUT6 (Prop_lut6_I0_O) 0.056 9.217 r usb_inst/FSM_onehot_read_state[4]_i_1/O
|
|
net (fo=5, routed) 0.473 9.689 usb_inst/FSM_onehot_read_state[4]_i_1_n_0
|
|
SLICE_X1Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[1]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 11.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[1]/C
|
|
clock pessimism 0.000 11.692
|
|
clock uncertainty -0.061 11.631
|
|
SLICE_X1Y209 FDCE (Setup_fdce_C_CE) -0.058 11.573 usb_inst/FSM_onehot_read_state_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 11.573
|
|
arrival time -9.689
|
|
-------------------------------------------------------------------
|
|
slack 1.884
|
|
|
|
Slack (MET) : 1.900ns (required time - arrival time)
|
|
Source: ft601_data[25]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[25]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.619ns (logic 0.412ns (15.738%) route 2.207ns (84.262%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.600ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.600ns = ( 11.600 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
J14 0.000 7.000 r ft601_data[25] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[25]_inst/IO
|
|
J14 IBUF (Prop_ibuf_I_O) 0.412 7.412 r ft601_data_IOBUF[25]_inst/IBUF/O
|
|
net (fo=1, routed) 2.207 9.619 usb_inst/rx_data_captured_reg[31]_0[4]
|
|
SLICE_X0Y186 FDCE r usb_inst/rx_data_captured_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 11.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y186 FDCE r usb_inst/rx_data_captured_reg[25]/C
|
|
clock pessimism 0.000 11.600
|
|
clock uncertainty -0.061 11.539
|
|
SLICE_X0Y186 FDCE (Setup_fdce_C_D) -0.019 11.520 usb_inst/rx_data_captured_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 11.520
|
|
arrival time -9.619
|
|
-------------------------------------------------------------------
|
|
slack 1.900
|
|
|
|
Slack (MET) : 1.905ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[4]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.647ns (logic 0.530ns (20.010%) route 2.117ns (79.990%))
|
|
Logic Levels: 3 (IBUF=1 LUT2=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.599ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.599ns = ( 11.599 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.802 9.220 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y184 LUT2 (Prop_lut2_I1_O) 0.056 9.276 r usb_inst/byte_counter[4]_i_2/O
|
|
net (fo=2, routed) 0.315 9.591 usb_inst/byte_counter[4]_i_2_n_0
|
|
SLICE_X4Y184 LUT6 (Prop_lut6_I1_O) 0.056 9.647 r usb_inst/byte_counter[4]_i_1/O
|
|
net (fo=1, routed) 0.000 9.647 usb_inst/byte_counter[4]
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.646 11.599 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[4]/C
|
|
clock pessimism 0.000 11.599
|
|
clock uncertainty -0.061 11.538
|
|
SLICE_X4Y184 FDCE (Setup_fdce_C_D) 0.014 11.552 usb_inst/byte_counter_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 11.552
|
|
arrival time -9.647
|
|
-------------------------------------------------------------------
|
|
slack 1.905
|
|
|
|
Slack (MET) : 1.911ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.641ns (logic 0.620ns (23.463%) route 2.021ns (76.537%))
|
|
Logic Levels: 3 (IBUF=1 LUT4=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.600ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.600ns = ( 11.600 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.802 9.220 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y184 LUT4 (Prop_lut4_I2_O) 0.061 9.281 r usb_inst/byte_counter[6]_i_2/O
|
|
net (fo=4, routed) 0.219 9.500 usb_inst/byte_counter[6]_i_2_n_0
|
|
SLICE_X3Y184 LUT6 (Prop_lut6_I0_O) 0.141 9.641 r usb_inst/byte_counter[6]_i_1/O
|
|
net (fo=1, routed) 0.000 9.641 usb_inst/byte_counter[6]
|
|
SLICE_X3Y184 FDCE r usb_inst/byte_counter_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 11.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y184 FDCE r usb_inst/byte_counter_reg[6]/C
|
|
clock pessimism 0.000 11.600
|
|
clock uncertainty -0.061 11.539
|
|
SLICE_X3Y184 FDCE (Setup_fdce_C_D) 0.013 11.552 usb_inst/byte_counter_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 11.552
|
|
arrival time -9.641
|
|
-------------------------------------------------------------------
|
|
slack 1.911
|
|
|
|
Slack (MET) : 1.940ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.611ns (logic 0.530ns (20.285%) route 2.081ns (79.715%))
|
|
Logic Levels: 3 (IBUF=1 LUT2=1 LUT5=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.599ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.599ns = ( 11.599 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.802 9.220 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y184 LUT2 (Prop_lut2_I1_O) 0.056 9.276 r usb_inst/byte_counter[4]_i_2/O
|
|
net (fo=2, routed) 0.279 9.555 usb_inst/byte_counter[4]_i_2_n_0
|
|
SLICE_X4Y184 LUT5 (Prop_lut5_I1_O) 0.056 9.611 r usb_inst/byte_counter[1]_i_1/O
|
|
net (fo=1, routed) 0.000 9.611 usb_inst/byte_counter[1]
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.646 11.599 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[1]/C
|
|
clock pessimism 0.000 11.599
|
|
clock uncertainty -0.061 11.538
|
|
SLICE_X4Y184 FDCE (Setup_fdce_C_D) 0.013 11.551 usb_inst/byte_counter_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 11.551
|
|
arrival time -9.611
|
|
-------------------------------------------------------------------
|
|
slack 1.940
|
|
|
|
Slack (MET) : 1.942ns (required time - arrival time)
|
|
Source: ft601_data[24]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[24]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.582ns (logic 0.406ns (15.722%) route 2.176ns (84.278%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.600ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.600ns = ( 11.600 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
H14 0.000 7.000 r ft601_data[24] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[24]_inst/IO
|
|
H14 IBUF (Prop_ibuf_I_O) 0.406 7.406 r ft601_data_IOBUF[24]_inst/IBUF/O
|
|
net (fo=1, routed) 2.176 9.582 usb_inst/rx_data_captured_reg[31]_0[3]
|
|
SLICE_X0Y186 FDCE r usb_inst/rx_data_captured_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 11.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y186 FDCE r usb_inst/rx_data_captured_reg[24]/C
|
|
clock pessimism 0.000 11.600
|
|
clock uncertainty -0.061 11.539
|
|
SLICE_X0Y186 FDCE (Setup_fdce_C_D) -0.014 11.525 usb_inst/rx_data_captured_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 11.525
|
|
arrival time -9.582
|
|
-------------------------------------------------------------------
|
|
slack 1.942
|
|
|
|
Slack (MET) : 1.947ns (required time - arrival time)
|
|
Source: ft601_data[30]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[30]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.574ns (logic 0.417ns (16.191%) route 2.157ns (83.809%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.591ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.591ns = ( 11.591 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
H19 0.000 7.000 r ft601_data[30] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[30]_inst/IO
|
|
H19 IBUF (Prop_ibuf_I_O) 0.417 7.417 r ft601_data_IOBUF[30]_inst/IBUF/O
|
|
net (fo=1, routed) 2.157 9.574 usb_inst/rx_data_captured_reg[31]_0[9]
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 11.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[30]/C
|
|
clock pessimism 0.000 11.591
|
|
clock uncertainty -0.061 11.530
|
|
SLICE_X0Y174 FDCE (Setup_fdce_C_D) -0.009 11.521 usb_inst/rx_data_captured_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 11.521
|
|
arrival time -9.574
|
|
-------------------------------------------------------------------
|
|
slack 1.947
|
|
|
|
Slack (MET) : 1.953ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.620ns (logic 0.620ns (23.651%) route 2.000ns (76.349%))
|
|
Logic Levels: 3 (IBUF=1 LUT4=1 LUT5=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.600ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.600ns = ( 11.600 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.802 9.220 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y184 LUT4 (Prop_lut4_I2_O) 0.061 9.281 r usb_inst/byte_counter[6]_i_2/O
|
|
net (fo=4, routed) 0.198 9.479 usb_inst/byte_counter[6]_i_2_n_0
|
|
SLICE_X2Y185 LUT5 (Prop_lut5_I0_O) 0.141 9.620 r usb_inst/byte_counter[2]_i_1/O
|
|
net (fo=1, routed) 0.000 9.620 usb_inst/byte_counter[2]
|
|
SLICE_X2Y185 FDCE r usb_inst/byte_counter_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 11.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y185 FDCE r usb_inst/byte_counter_reg[2]/C
|
|
clock pessimism 0.000 11.600
|
|
clock uncertainty -0.061 11.539
|
|
SLICE_X2Y185 FDCE (Setup_fdce_C_D) 0.034 11.573 usb_inst/byte_counter_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 11.573
|
|
arrival time -9.620
|
|
-------------------------------------------------------------------
|
|
slack 1.953
|
|
|
|
Slack (MET) : 1.955ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.597ns (logic 0.620ns (23.860%) route 1.977ns (76.140%))
|
|
Logic Levels: 3 (IBUF=1 LUT4=1 LUT6=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.599ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.599ns = ( 11.599 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.802 9.220 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y184 LUT4 (Prop_lut4_I2_O) 0.061 9.281 r usb_inst/byte_counter[6]_i_2/O
|
|
net (fo=4, routed) 0.175 9.456 usb_inst/byte_counter[6]_i_2_n_0
|
|
SLICE_X4Y184 LUT6 (Prop_lut6_I0_O) 0.141 9.597 r usb_inst/byte_counter[3]_i_1/O
|
|
net (fo=1, routed) 0.000 9.597 usb_inst/byte_counter[3]
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.646 11.599 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[3]/C
|
|
clock pessimism 0.000 11.599
|
|
clock uncertainty -0.061 11.538
|
|
SLICE_X4Y184 FDCE (Setup_fdce_C_D) 0.014 11.552 usb_inst/byte_counter_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 11.552
|
|
arrival time -9.597
|
|
-------------------------------------------------------------------
|
|
slack 1.955
|
|
|
|
Slack (MET) : 1.959ns (required time - arrival time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.593ns (logic 0.620ns (23.894%) route 1.974ns (76.106%))
|
|
Logic Levels: 3 (IBUF=1 LUT4=1 LUT5=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.599ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.599ns = ( 11.599 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
E17 0.000 7.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 7.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 0.418 7.418 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 1.802 9.220 usb_inst/ft601_txe_IBUF
|
|
SLICE_X2Y184 LUT4 (Prop_lut4_I2_O) 0.061 9.281 r usb_inst/byte_counter[6]_i_2/O
|
|
net (fo=4, routed) 0.171 9.452 usb_inst/byte_counter[6]_i_2_n_0
|
|
SLICE_X4Y184 LUT5 (Prop_lut5_I0_O) 0.141 9.593 r usb_inst/byte_counter[5]_i_1/O
|
|
net (fo=1, routed) 0.000 9.593 usb_inst/byte_counter[5]
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.646 11.599 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[5]/C
|
|
clock pessimism 0.000 11.599
|
|
clock uncertainty -0.061 11.538
|
|
SLICE_X4Y184 FDCE (Setup_fdce_C_D) 0.014 11.552 usb_inst/byte_counter_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 11.552
|
|
arrival time -9.593
|
|
-------------------------------------------------------------------
|
|
slack 1.959
|
|
|
|
Slack (MET) : 2.022ns (required time - arrival time)
|
|
Source: ft601_data[0]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.499ns (logic 0.440ns (17.592%) route 2.059ns (82.408%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.596ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.596ns = ( 11.596 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
L21 0.000 7.000 r ft601_data[0] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[0]_inst/IO
|
|
L21 IBUF (Prop_ibuf_I_O) 0.440 7.440 r ft601_data_IOBUF[0]_inst/IBUF/O
|
|
net (fo=1, routed) 2.059 9.499 usb_inst/rx_data_captured_reg[31]_0[0]
|
|
SLICE_X3Y180 FDCE r usb_inst/rx_data_captured_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 11.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y180 FDCE r usb_inst/rx_data_captured_reg[0]/C
|
|
clock pessimism 0.000 11.596
|
|
clock uncertainty -0.061 11.535
|
|
SLICE_X3Y180 FDCE (Setup_fdce_C_D) -0.014 11.521 usb_inst/rx_data_captured_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 11.521
|
|
arrival time -9.499
|
|
-------------------------------------------------------------------
|
|
slack 2.022
|
|
|
|
Slack (MET) : 2.082ns (required time - arrival time)
|
|
Source: ft601_data[2]
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Fast Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.434ns (logic 0.442ns (18.170%) route 1.992ns (81.830%))
|
|
Logic Levels: 1 (IBUF=1)
|
|
Input Delay: 7.000ns
|
|
Clock Path Skew: 1.596ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 1.596ns = ( 11.596 - 10.000 )
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): 0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 7.000 7.000
|
|
M21 0.000 7.000 r ft601_data[2] (INOUT)
|
|
net (fo=1, unset) 0.000 7.000 ft601_data_IOBUF[2]_inst/IO
|
|
M21 IBUF (Prop_ibuf_I_O) 0.442 7.442 r ft601_data_IOBUF[2]_inst/IBUF/O
|
|
net (fo=1, routed) 1.992 9.434 usb_inst/rx_data_captured_reg[31]_0[2]
|
|
SLICE_X3Y180 FDCE r usb_inst/rx_data_captured_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 10.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 10.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 10.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 11.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y180 FDCE r usb_inst/rx_data_captured_reg[2]/C
|
|
clock pessimism 0.000 11.596
|
|
clock uncertainty -0.061 11.535
|
|
SLICE_X3Y180 FDCE (Setup_fdce_C_D) -0.019 11.516 usb_inst/rx_data_captured_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 11.516
|
|
arrival time -9.434
|
|
-------------------------------------------------------------------
|
|
slack 2.082
|
|
|
|
Slack (MET) : 4.595ns (required time - arrival time)
|
|
Source: usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[15]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.426ns (logic 0.768ns (17.351%) route 3.658ns (82.649%))
|
|
Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.851ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.543 4.851 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y183 FDCE (Prop_fdce_C_Q) 0.433 5.284 r usb_inst/FSM_sequential_current_state_reg[0]/Q
|
|
net (fo=51, routed) 0.938 6.222 usb_inst/current_state__0[0]
|
|
SLICE_X4Y181 LUT5 (Prop_lut5_I3_O) 0.105 6.327 r usb_inst/ft601_data_out[23]_i_5/O
|
|
net (fo=24, routed) 1.195 7.522 usb_inst/ft601_data_out[23]_i_5_n_0
|
|
SLICE_X6Y178 LUT6 (Prop_lut6_I0_O) 0.105 7.627 r usb_inst/ft601_data_out[15]_i_3/O
|
|
net (fo=1, routed) 0.775 8.402 usb_inst/ft601_data_out[15]_i_3_n_0
|
|
SLICE_X2Y178 LUT3 (Prop_lut3_I2_O) 0.125 8.527 r usb_inst/ft601_data_out[15]_i_1/O
|
|
net (fo=1, routed) 0.751 9.278 usb_inst/ft601_data_out__0[15]
|
|
OLOGIC_X0Y189 FDCE r usb_inst/ft601_data_out_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y189 FDCE r usb_inst/ft601_data_out_reg[15]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y189 FDCE (Setup_fdce_C_D) -0.866 13.873 usb_inst/ft601_data_out_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 13.873
|
|
arrival time -9.278
|
|
-------------------------------------------------------------------
|
|
slack 4.595
|
|
|
|
Slack (MET) : 4.661ns (required time - arrival time)
|
|
Source: usb_inst/byte_counter_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[9]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.349ns (logic 0.762ns (17.523%) route 3.587ns (82.477%))
|
|
Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.852ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.544 4.852 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y184 FDCE (Prop_fdce_C_Q) 0.433 5.285 r usb_inst/byte_counter_reg[0]/Q
|
|
net (fo=33, routed) 0.849 6.134 usb_inst/byte_counter_reg_n_0_[0]
|
|
SLICE_X5Y183 LUT5 (Prop_lut5_I1_O) 0.105 6.239 r usb_inst/ft601_data_out[23]_i_4/O
|
|
net (fo=24, routed) 1.046 7.285 usb_inst/ft601_data_out[23]_i_4_n_0
|
|
SLICE_X1Y179 LUT6 (Prop_lut6_I2_O) 0.105 7.390 r usb_inst/ft601_data_out[9]_i_2/O
|
|
net (fo=1, routed) 0.546 7.936 usb_inst/ft601_data_out[9]_i_2_n_0
|
|
SLICE_X1Y179 LUT3 (Prop_lut3_I2_O) 0.119 8.055 r usb_inst/ft601_data_out[9]_i_1/O
|
|
net (fo=1, routed) 1.146 9.201 usb_inst/ft601_data_out__0[9]
|
|
OLOGIC_X0Y158 FDCE r usb_inst/ft601_data_out_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y158 FDCE r usb_inst/ft601_data_out_reg[9]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y158 FDCE (Setup_fdce_C_D) -0.877 13.862 usb_inst/ft601_data_out_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 13.862
|
|
arrival time -9.201
|
|
-------------------------------------------------------------------
|
|
slack 4.661
|
|
|
|
Slack (MET) : 4.807ns (required time - arrival time)
|
|
Source: usb_inst/FSM_sequential_current_state_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[29]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.372ns (logic 0.819ns (18.734%) route 3.553ns (81.266%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 4.851ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.543 4.851 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y183 FDCE (Prop_fdce_C_Q) 0.433 5.284 r usb_inst/FSM_sequential_current_state_reg[2]/Q
|
|
net (fo=45, routed) 1.457 6.741 usb_inst/current_state__0[2]
|
|
SLICE_X3Y178 LUT5 (Prop_lut5_I2_O) 0.119 6.860 r usb_inst/ft601_data_out[31]_i_5/O
|
|
net (fo=8, routed) 1.276 8.136 usb_inst/ft601_data_out[31]_i_5_n_0
|
|
SLICE_X3Y177 LUT6 (Prop_lut6_I2_O) 0.267 8.403 r usb_inst/ft601_data_out[29]_i_1/O
|
|
net (fo=1, routed) 0.820 9.223 usb_inst/ft601_data_out__0[29]
|
|
OLOGIC_X0Y162 FDCE r usb_inst/ft601_data_out_reg[29]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y162 FDCE r usb_inst/ft601_data_out_reg[29]/C
|
|
clock pessimism 0.228 14.798
|
|
clock uncertainty -0.061 14.737
|
|
OLOGIC_X0Y162 FDCE (Setup_fdce_C_D) -0.707 14.030 usb_inst/ft601_data_out_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 14.030
|
|
arrival time -9.223
|
|
-------------------------------------------------------------------
|
|
slack 4.807
|
|
|
|
Slack (MET) : 4.894ns (required time - arrival time)
|
|
Source: usb_inst/byte_counter_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[13]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.124ns (logic 0.767ns (18.599%) route 3.357ns (81.401%))
|
|
Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.852ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.544 4.852 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y184 FDCE (Prop_fdce_C_Q) 0.433 5.285 r usb_inst/byte_counter_reg[0]/Q
|
|
net (fo=33, routed) 0.849 6.134 usb_inst/byte_counter_reg_n_0_[0]
|
|
SLICE_X5Y183 LUT5 (Prop_lut5_I1_O) 0.105 6.239 r usb_inst/ft601_data_out[23]_i_4/O
|
|
net (fo=24, routed) 1.231 7.470 usb_inst/ft601_data_out[23]_i_4_n_0
|
|
SLICE_X4Y177 LUT6 (Prop_lut6_I2_O) 0.105 7.575 r usb_inst/ft601_data_out[13]_i_2/O
|
|
net (fo=1, routed) 0.652 8.228 usb_inst/ft601_data_out[13]_i_2_n_0
|
|
SLICE_X1Y179 LUT3 (Prop_lut3_I2_O) 0.124 8.352 r usb_inst/ft601_data_out[13]_i_1/O
|
|
net (fo=1, routed) 0.624 8.976 usb_inst/ft601_data_out__0[13]
|
|
OLOGIC_X0Y190 FDCE r usb_inst/ft601_data_out_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y190 FDCE r usb_inst/ft601_data_out_reg[13]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y190 FDCE (Setup_fdce_C_D) -0.869 13.870 usb_inst/ft601_data_out_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 13.870
|
|
arrival time -8.976
|
|
-------------------------------------------------------------------
|
|
slack 4.894
|
|
|
|
Slack (MET) : 4.915ns (required time - arrival time)
|
|
Source: usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[25]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.265ns (logic 0.924ns (21.664%) route 3.341ns (78.336%))
|
|
Logic Levels: 3 (LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.851ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.543 4.851 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y183 FDCE (Prop_fdce_C_Q) 0.433 5.284 r usb_inst/FSM_sequential_current_state_reg[0]/Q
|
|
net (fo=51, routed) 0.938 6.222 usb_inst/current_state__0[0]
|
|
SLICE_X4Y181 LUT5 (Prop_lut5_I3_O) 0.119 6.341 r usb_inst/ft601_data_out[31]_i_8/O
|
|
net (fo=8, routed) 1.072 7.413 usb_inst/ft601_data_out[31]_i_8_n_0
|
|
SLICE_X3Y178 LUT6 (Prop_lut6_I5_O) 0.267 7.680 r usb_inst/ft601_data_out[25]_i_2/O
|
|
net (fo=1, routed) 0.453 8.132 usb_inst/ft601_data_out[25]_i_2_n_0
|
|
SLICE_X1Y178 LUT6 (Prop_lut6_I4_O) 0.105 8.237 r usb_inst/ft601_data_out[25]_i_1/O
|
|
net (fo=1, routed) 0.879 9.116 usb_inst/ft601_data_out__0[25]
|
|
OLOGIC_X0Y194 FDCE r usb_inst/ft601_data_out_reg[25]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y194 FDCE r usb_inst/ft601_data_out_reg[25]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y194 FDCE (Setup_fdce_C_D) -0.707 14.032 usb_inst/ft601_data_out_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 14.032
|
|
arrival time -9.116
|
|
-------------------------------------------------------------------
|
|
slack 4.915
|
|
|
|
Slack (MET) : 4.992ns (required time - arrival time)
|
|
Source: usb_inst/byte_counter_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[28]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.186ns (logic 0.748ns (17.870%) route 3.438ns (82.130%))
|
|
Logic Levels: 3 (LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.054ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 4.852ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.544 4.852 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y184 FDCE (Prop_fdce_C_Q) 0.433 5.285 f usb_inst/byte_counter_reg[0]/Q
|
|
net (fo=33, routed) 1.304 6.589 usb_inst/byte_counter_reg_n_0_[0]
|
|
SLICE_X0Y178 LUT5 (Prop_lut5_I1_O) 0.105 6.694 r usb_inst/ft601_data_out[31]_i_10/O
|
|
net (fo=16, routed) 0.834 7.529 usb_inst/ft601_data_out[31]_i_10_n_0
|
|
SLICE_X2Y180 LUT6 (Prop_lut6_I2_O) 0.105 7.634 r usb_inst/ft601_data_out[28]_i_3/O
|
|
net (fo=1, routed) 0.343 7.976 usb_inst/ft601_data_out[28]_i_3_n_0
|
|
SLICE_X2Y178 LUT6 (Prop_lut6_I5_O) 0.105 8.081 r usb_inst/ft601_data_out[28]_i_1/O
|
|
net (fo=1, routed) 0.957 9.038 usb_inst/ft601_data_out__0[28]
|
|
OLOGIC_X0Y161 FDCE r usb_inst/ft601_data_out_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y161 FDCE r usb_inst/ft601_data_out_reg[28]/C
|
|
clock pessimism 0.228 14.798
|
|
clock uncertainty -0.061 14.737
|
|
OLOGIC_X0Y161 FDCE (Setup_fdce_C_D) -0.707 14.030 usb_inst/ft601_data_out_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 14.030
|
|
arrival time -9.038
|
|
-------------------------------------------------------------------
|
|
slack 4.992
|
|
|
|
Slack (MET) : 5.044ns (required time - arrival time)
|
|
Source: usb_inst/byte_counter_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.136ns (logic 0.748ns (18.086%) route 3.388ns (81.914%))
|
|
Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.852ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.544 4.852 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y184 FDCE (Prop_fdce_C_Q) 0.433 5.285 r usb_inst/byte_counter_reg[0]/Q
|
|
net (fo=33, routed) 0.849 6.134 usb_inst/byte_counter_reg_n_0_[0]
|
|
SLICE_X5Y183 LUT5 (Prop_lut5_I1_O) 0.105 6.239 r usb_inst/ft601_data_out[23]_i_4/O
|
|
net (fo=24, routed) 1.078 7.317 usb_inst/ft601_data_out[23]_i_4_n_0
|
|
SLICE_X1Y180 LUT6 (Prop_lut6_I2_O) 0.105 7.422 r usb_inst/ft601_data_out[12]_i_2/O
|
|
net (fo=1, routed) 0.452 7.874 usb_inst/ft601_data_out[12]_i_2_n_0
|
|
SLICE_X1Y179 LUT3 (Prop_lut3_I2_O) 0.105 7.979 r usb_inst/ft601_data_out[12]_i_1/O
|
|
net (fo=1, routed) 1.010 8.988 usb_inst/ft601_data_out__0[12]
|
|
OLOGIC_X0Y155 FDCE r usb_inst/ft601_data_out_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y155 FDCE r usb_inst/ft601_data_out_reg[12]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y155 FDCE (Setup_fdce_C_D) -0.707 14.032 usb_inst/ft601_data_out_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 14.032
|
|
arrival time -8.988
|
|
-------------------------------------------------------------------
|
|
slack 5.044
|
|
|
|
Slack (MET) : 5.080ns (required time - arrival time)
|
|
Source: usb_inst/byte_counter_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[11]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.100ns (logic 0.808ns (19.709%) route 3.292ns (80.291%))
|
|
Logic Levels: 2 (LUT3=1 LUT5=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.852ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.544 4.852 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y184 FDCE (Prop_fdce_C_Q) 0.433 5.285 r usb_inst/byte_counter_reg[0]/Q
|
|
net (fo=33, routed) 1.304 6.589 usb_inst/byte_counter_reg_n_0_[0]
|
|
SLICE_X0Y178 LUT5 (Prop_lut5_I1_O) 0.108 6.697 r usb_inst/ft601_data_out[15]_i_2/O
|
|
net (fo=16, routed) 0.859 7.556 usb_inst/ft601_data_out[15]_i_2_n_0
|
|
SLICE_X2Y179 LUT3 (Prop_lut3_I1_O) 0.267 7.823 r usb_inst/ft601_data_out[11]_i_1/O
|
|
net (fo=1, routed) 1.129 8.952 usb_inst/ft601_data_out__0[11]
|
|
OLOGIC_X0Y157 FDCE r usb_inst/ft601_data_out_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y157 FDCE r usb_inst/ft601_data_out_reg[11]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y157 FDCE (Setup_fdce_C_D) -0.707 14.032 usb_inst/ft601_data_out_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 14.032
|
|
arrival time -8.952
|
|
-------------------------------------------------------------------
|
|
slack 5.080
|
|
|
|
Slack (MET) : 5.090ns (required time - arrival time)
|
|
Source: usb_inst/byte_counter_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[24]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.090ns (logic 0.748ns (18.289%) route 3.342ns (81.711%))
|
|
Logic Levels: 3 (LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.852ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.544 4.852 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y184 FDCE (Prop_fdce_C_Q) 0.433 5.285 r usb_inst/byte_counter_reg[0]/Q
|
|
net (fo=33, routed) 0.849 6.134 usb_inst/byte_counter_reg_n_0_[0]
|
|
SLICE_X5Y183 LUT5 (Prop_lut5_I1_O) 0.105 6.239 r usb_inst/ft601_data_out[23]_i_4/O
|
|
net (fo=24, routed) 0.817 7.056 usb_inst/ft601_data_out[23]_i_4_n_0
|
|
SLICE_X4Y180 LUT6 (Prop_lut6_I2_O) 0.105 7.161 r usb_inst/ft601_data_out[24]_i_2/O
|
|
net (fo=1, routed) 0.926 8.087 usb_inst/ft601_data_out[24]_i_2_n_0
|
|
SLICE_X2Y180 LUT6 (Prop_lut6_I4_O) 0.105 8.192 r usb_inst/ft601_data_out[24]_i_1/O
|
|
net (fo=1, routed) 0.750 8.942 usb_inst/ft601_data_out__0[24]
|
|
OLOGIC_X0Y193 FDCE r usb_inst/ft601_data_out_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y193 FDCE r usb_inst/ft601_data_out_reg[24]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y193 FDCE (Setup_fdce_C_D) -0.707 14.032 usb_inst/ft601_data_out_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 14.032
|
|
arrival time -8.942
|
|
-------------------------------------------------------------------
|
|
slack 5.090
|
|
|
|
Slack (MET) : 5.115ns (required time - arrival time)
|
|
Source: usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[30]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.053ns (logic 0.748ns (18.455%) route 3.305ns (81.545%))
|
|
Logic Levels: 3 (LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.063ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.560ns = ( 14.560 - 10.000 )
|
|
Source Clock Delay (SCD): 4.851ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.543 4.851 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y183 FDCE (Prop_fdce_C_Q) 0.433 5.284 r usb_inst/FSM_sequential_current_state_reg[0]/Q
|
|
net (fo=51, routed) 0.938 6.222 usb_inst/current_state__0[0]
|
|
SLICE_X4Y181 LUT5 (Prop_lut5_I3_O) 0.105 6.327 r usb_inst/ft601_data_out[23]_i_5/O
|
|
net (fo=24, routed) 1.038 7.365 usb_inst/ft601_data_out[23]_i_5_n_0
|
|
SLICE_X6Y178 LUT6 (Prop_lut6_I0_O) 0.105 7.470 r usb_inst/ft601_data_out[30]_i_2/O
|
|
net (fo=1, routed) 0.794 8.264 usb_inst/ft601_data_out[30]_i_2_n_0
|
|
SLICE_X2Y176 LUT6 (Prop_lut6_I4_O) 0.105 8.369 r usb_inst/ft601_data_out[30]_i_1/O
|
|
net (fo=1, routed) 0.535 8.904 usb_inst/ft601_data_out__0[30]
|
|
OLOGIC_X0Y175 FDCE r usb_inst/ft601_data_out_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.415 14.560 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y175 FDCE r usb_inst/ft601_data_out_reg[30]/C
|
|
clock pessimism 0.228 14.788
|
|
clock uncertainty -0.061 14.727
|
|
OLOGIC_X0Y175 FDCE (Setup_fdce_C_D) -0.707 14.020 usb_inst/ft601_data_out_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 14.020
|
|
arrival time -8.904
|
|
-------------------------------------------------------------------
|
|
slack 5.115
|
|
|
|
Slack (MET) : 5.126ns (required time - arrival time)
|
|
Source: usb_inst/byte_counter_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.053ns (logic 0.748ns (18.454%) route 3.305ns (81.546%))
|
|
Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.852ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.544 4.852 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y184 FDCE (Prop_fdce_C_Q) 0.433 5.285 f usb_inst/byte_counter_reg[0]/Q
|
|
net (fo=33, routed) 1.304 6.589 usb_inst/byte_counter_reg_n_0_[0]
|
|
SLICE_X0Y178 LUT5 (Prop_lut5_I1_O) 0.105 6.694 r usb_inst/ft601_data_out[31]_i_10/O
|
|
net (fo=16, routed) 0.564 7.258 usb_inst/ft601_data_out[31]_i_10_n_0
|
|
SLICE_X2Y177 LUT6 (Prop_lut6_I5_O) 0.105 7.363 r usb_inst/ft601_data_out[14]_i_2/O
|
|
net (fo=1, routed) 0.327 7.690 usb_inst/ft601_data_out[14]_i_2_n_0
|
|
SLICE_X2Y178 LUT3 (Prop_lut3_I2_O) 0.105 7.795 r usb_inst/ft601_data_out[14]_i_1/O
|
|
net (fo=1, routed) 1.111 8.906 usb_inst/ft601_data_out__0[14]
|
|
OLOGIC_X0Y156 FDCE r usb_inst/ft601_data_out_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y156 FDCE r usb_inst/ft601_data_out_reg[14]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y156 FDCE (Setup_fdce_C_D) -0.707 14.032 usb_inst/ft601_data_out_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 14.032
|
|
arrival time -8.906
|
|
-------------------------------------------------------------------
|
|
slack 5.126
|
|
|
|
Slack (MET) : 5.152ns (required time - arrival time)
|
|
Source: usb_inst/byte_counter_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[31]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.016ns (logic 0.748ns (18.626%) route 3.268ns (81.374%))
|
|
Logic Levels: 3 (LUT5=1 LUT6=2)
|
|
Clock Path Skew: -0.064ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.560ns = ( 14.560 - 10.000 )
|
|
Source Clock Delay (SCD): 4.852ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.544 4.852 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y184 FDCE r usb_inst/byte_counter_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y184 FDCE (Prop_fdce_C_Q) 0.433 5.285 r usb_inst/byte_counter_reg[0]/Q
|
|
net (fo=33, routed) 0.849 6.134 usb_inst/byte_counter_reg_n_0_[0]
|
|
SLICE_X5Y183 LUT5 (Prop_lut5_I1_O) 0.105 6.239 r usb_inst/ft601_data_out[23]_i_4/O
|
|
net (fo=24, routed) 1.125 7.365 usb_inst/ft601_data_out[23]_i_4_n_0
|
|
SLICE_X6Y178 LUT6 (Prop_lut6_I2_O) 0.105 7.470 r usb_inst/ft601_data_out[31]_i_6/O
|
|
net (fo=1, routed) 0.759 8.228 usb_inst/ft601_data_out[31]_i_6_n_0
|
|
SLICE_X3Y177 LUT6 (Prop_lut6_I4_O) 0.105 8.333 r usb_inst/ft601_data_out[31]_i_2/O
|
|
net (fo=1, routed) 0.535 8.868 usb_inst/ft601_data_out__0[31]
|
|
OLOGIC_X0Y176 FDCE r usb_inst/ft601_data_out_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.415 14.560 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y176 FDCE r usb_inst/ft601_data_out_reg[31]/C
|
|
clock pessimism 0.228 14.788
|
|
clock uncertainty -0.061 14.727
|
|
OLOGIC_X0Y176 FDCE (Setup_fdce_C_D) -0.707 14.020 usb_inst/ft601_data_out_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time 14.020
|
|
arrival time -8.868
|
|
-------------------------------------------------------------------
|
|
slack 5.152
|
|
|
|
Slack (MET) : 5.195ns (required time - arrival time)
|
|
Source: usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[22]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.985ns (logic 0.748ns (18.769%) route 3.237ns (81.231%))
|
|
Logic Levels: 3 (LUT3=1 LUT6=2)
|
|
Clock Path Skew: -0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.851ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.543 4.851 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y183 FDCE (Prop_fdce_C_Q) 0.433 5.284 f usb_inst/FSM_sequential_current_state_reg[0]/Q
|
|
net (fo=51, routed) 0.710 5.995 usb_inst/current_state__0[0]
|
|
SLICE_X1Y183 LUT3 (Prop_lut3_I1_O) 0.105 6.100 f usb_inst/byte_counter[7]_i_5/O
|
|
net (fo=10, routed) 0.996 7.096 usb_inst/byte_counter[7]_i_5_n_0
|
|
SLICE_X4Y177 LUT6 (Prop_lut6_I5_O) 0.105 7.201 r usb_inst/ft601_data_out[22]_i_2/O
|
|
net (fo=1, routed) 0.778 7.979 usb_inst/ft601_data_out[22]_i_2_n_0
|
|
SLICE_X4Y180 LUT6 (Prop_lut6_I0_O) 0.105 8.084 r usb_inst/ft601_data_out[22]_i_1/O
|
|
net (fo=1, routed) 0.753 8.837 usb_inst/ft601_data_out__0[22]
|
|
OLOGIC_X0Y192 FDCE r usb_inst/ft601_data_out_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y192 FDCE r usb_inst/ft601_data_out_reg[22]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y192 FDCE (Setup_fdce_C_D) -0.707 14.032 usb_inst/ft601_data_out_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 14.032
|
|
arrival time -8.837
|
|
-------------------------------------------------------------------
|
|
slack 5.195
|
|
|
|
Slack (MET) : 5.243ns (required time - arrival time)
|
|
Source: usb_inst/FSM_sequential_current_state_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[27]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.933ns (logic 0.819ns (20.822%) route 3.114ns (79.178%))
|
|
Logic Levels: 2 (LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 4.851ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.543 4.851 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y183 FDCE (Prop_fdce_C_Q) 0.433 5.284 r usb_inst/FSM_sequential_current_state_reg[2]/Q
|
|
net (fo=45, routed) 1.457 6.741 usb_inst/current_state__0[2]
|
|
SLICE_X3Y178 LUT5 (Prop_lut5_I2_O) 0.119 6.860 r usb_inst/ft601_data_out[31]_i_5/O
|
|
net (fo=8, routed) 0.860 7.720 usb_inst/ft601_data_out[31]_i_5_n_0
|
|
SLICE_X1Y178 LUT6 (Prop_lut6_I2_O) 0.267 7.987 r usb_inst/ft601_data_out[27]_i_1/O
|
|
net (fo=1, routed) 0.797 8.785 usb_inst/ft601_data_out__0[27]
|
|
OLOGIC_X0Y165 FDCE r usb_inst/ft601_data_out_reg[27]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y165 FDCE r usb_inst/ft601_data_out_reg[27]/C
|
|
clock pessimism 0.228 14.796
|
|
clock uncertainty -0.061 14.735
|
|
OLOGIC_X0Y165 FDCE (Setup_fdce_C_D) -0.707 14.028 usb_inst/ft601_data_out_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 14.028
|
|
arrival time -8.785
|
|
-------------------------------------------------------------------
|
|
slack 5.243
|
|
|
|
Slack (MET) : 5.286ns (required time - arrival time)
|
|
Source: usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Setup (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.893ns (logic 0.748ns (19.216%) route 3.145ns (80.784%))
|
|
Logic Levels: 3 (LUT3=1 LUT5=1 LUT6=1)
|
|
Clock Path Skew: -0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 4.851ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.543 4.851 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/FSM_sequential_current_state_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y183 FDCE (Prop_fdce_C_Q) 0.433 5.284 r usb_inst/FSM_sequential_current_state_reg[0]/Q
|
|
net (fo=51, routed) 0.938 6.222 usb_inst/current_state__0[0]
|
|
SLICE_X4Y181 LUT5 (Prop_lut5_I3_O) 0.105 6.327 r usb_inst/ft601_data_out[23]_i_5/O
|
|
net (fo=24, routed) 1.056 7.383 usb_inst/ft601_data_out[23]_i_5_n_0
|
|
SLICE_X3Y179 LUT6 (Prop_lut6_I0_O) 0.105 7.488 r usb_inst/ft601_data_out[8]_i_2/O
|
|
net (fo=1, routed) 0.566 8.054 usb_inst/ft601_data_out[8]_i_2_n_0
|
|
SLICE_X1Y179 LUT3 (Prop_lut3_I2_O) 0.105 8.159 r usb_inst/ft601_data_out[8]_i_1/O
|
|
net (fo=1, routed) 0.585 8.744 usb_inst/ft601_data_out__0[8]
|
|
OLOGIC_X0Y187 FDCE r usb_inst/ft601_data_out_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y187 FDCE r usb_inst/ft601_data_out_reg[8]/C
|
|
clock pessimism 0.228 14.798
|
|
clock uncertainty -0.061 14.737
|
|
OLOGIC_X0Y187 FDCE (Setup_fdce_C_D) -0.707 14.030 usb_inst/ft601_data_out_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 14.030
|
|
arrival time -8.744
|
|
-------------------------------------------------------------------
|
|
slack 5.286
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.121ns (arrival time - required time)
|
|
Source: usb_inst/range_valid_sync_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_valid_sync_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.598ns
|
|
Clock Pessimism Removal (CPR): 0.522ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.645 1.598 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y182 FDCE r usb_inst/range_valid_sync_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y182 FDCE (Prop_fdce_C_Q) 0.141 1.739 r usb_inst/range_valid_sync_reg[0]/Q
|
|
net (fo=1, routed) 0.055 1.794 usb_inst/range_valid_sync[0]
|
|
SLICE_X3Y182 FDCE r usb_inst/range_valid_sync_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y182 FDCE r usb_inst/range_valid_sync_reg[1]/C
|
|
clock pessimism -0.522 1.598
|
|
SLICE_X3Y182 FDCE (Hold_fdce_C_D) 0.075 1.673 usb_inst/range_valid_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.673
|
|
arrival time 1.794
|
|
-------------------------------------------------------------------
|
|
slack 0.121
|
|
|
|
Slack (MET) : 0.125ns (arrival time - required time)
|
|
Source: usb_inst/stream_ctrl_sync_0_reg[0]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/stream_ctrl_sync_1_reg[0]/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.196ns (logic 0.141ns (71.838%) route 0.055ns (28.162%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.598ns
|
|
Clock Pessimism Removal (CPR): 0.522ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.645 1.598 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y182 FDPE r usb_inst/stream_ctrl_sync_0_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y182 FDPE (Prop_fdpe_C_Q) 0.141 1.739 r usb_inst/stream_ctrl_sync_0_reg[0]/Q
|
|
net (fo=1, routed) 0.055 1.794 usb_inst/stream_ctrl_sync_0[0]
|
|
SLICE_X3Y182 FDPE r usb_inst/stream_ctrl_sync_1_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y182 FDPE r usb_inst/stream_ctrl_sync_1_reg[0]/C
|
|
clock pessimism -0.522 1.598
|
|
SLICE_X3Y182 FDPE (Hold_fdpe_C_D) 0.071 1.669 usb_inst/stream_ctrl_sync_1_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.669
|
|
arrival time 1.794
|
|
-------------------------------------------------------------------
|
|
slack 0.125
|
|
|
|
Slack (MET) : 0.127ns (arrival time - required time)
|
|
Source: usb_inst/stream_ctrl_sync_0_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/stream_ctrl_sync_1_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.198ns (logic 0.141ns (71.201%) route 0.057ns (28.799%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.598ns
|
|
Clock Pessimism Removal (CPR): 0.522ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.645 1.598 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y183 FDCE r usb_inst/stream_ctrl_sync_0_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y183 FDCE (Prop_fdce_C_Q) 0.141 1.739 r usb_inst/stream_ctrl_sync_0_reg[2]/Q
|
|
net (fo=1, routed) 0.057 1.796 usb_inst/stream_ctrl_sync_0[2]
|
|
SLICE_X4Y183 FDCE r usb_inst/stream_ctrl_sync_1_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y183 FDCE r usb_inst/stream_ctrl_sync_1_reg[2]/C
|
|
clock pessimism -0.522 1.598
|
|
SLICE_X4Y183 FDCE (Hold_fdce_C_D) 0.071 1.669 usb_inst/stream_ctrl_sync_1_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.669
|
|
arrival time 1.796
|
|
-------------------------------------------------------------------
|
|
slack 0.127
|
|
|
|
Slack (MET) : 0.130ns (arrival time - required time)
|
|
Source: usb_inst/stream_ctrl_sync_0_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/stream_ctrl_sync_1_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.205ns (logic 0.141ns (68.843%) route 0.064ns (31.157%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.598ns
|
|
Clock Pessimism Removal (CPR): 0.522ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.645 1.598 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y183 FDCE r usb_inst/stream_ctrl_sync_0_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y183 FDCE (Prop_fdce_C_Q) 0.141 1.739 r usb_inst/stream_ctrl_sync_0_reg[1]/Q
|
|
net (fo=1, routed) 0.064 1.803 usb_inst/stream_ctrl_sync_0[1]
|
|
SLICE_X4Y183 FDCE r usb_inst/stream_ctrl_sync_1_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y183 FDCE r usb_inst/stream_ctrl_sync_1_reg[1]/C
|
|
clock pessimism -0.522 1.598
|
|
SLICE_X4Y183 FDCE (Hold_fdce_C_D) 0.075 1.673 usb_inst/stream_ctrl_sync_1_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.673
|
|
arrival time 1.803
|
|
-------------------------------------------------------------------
|
|
slack 0.130
|
|
|
|
Slack (MET) : 0.133ns (arrival time - required time)
|
|
Source: usb_inst/rx_data_captured_reg[27]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.193ns (logic 0.141ns (72.985%) route 0.052ns (27.015%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[27]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y174 FDCE (Prop_fdce_C_Q) 0.141 1.732 r usb_inst/rx_data_captured_reg[27]/Q
|
|
net (fo=1, routed) 0.052 1.784 usb_inst/p_0_in[3]
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[3]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X1Y174 FDCE (Hold_fdce_C_D) 0.047 1.651 usb_inst/cmd_opcode_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.651
|
|
arrival time 1.784
|
|
-------------------------------------------------------------------
|
|
slack 0.133
|
|
|
|
Slack (MET) : 0.150ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[15]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[15]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.260ns (logic 0.141ns (54.152%) route 0.119ns (45.848%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y176 FDCE (Prop_fdce_C_Q) 0.141 1.732 r usb_inst/doppler_imag_hold_reg[15]/Q
|
|
net (fo=1, routed) 0.119 1.851 usb_inst/doppler_imag_hold[15]
|
|
SLICE_X3Y177 FDCE r usb_inst/doppler_imag_cap_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y177 FDCE r usb_inst/doppler_imag_cap_reg[15]/C
|
|
clock pessimism -0.484 1.631
|
|
SLICE_X3Y177 FDCE (Hold_fdce_C_D) 0.070 1.701 usb_inst/doppler_imag_cap_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -1.701
|
|
arrival time 1.851
|
|
-------------------------------------------------------------------
|
|
slack 0.150
|
|
|
|
Slack (MET) : 0.158ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[28]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[28]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.260ns (logic 0.141ns (54.148%) route 0.119ns (45.852%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y181 FDCE r usb_inst/range_profile_hold_reg[28]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y181 FDCE (Prop_fdce_C_Q) 0.141 1.737 r usb_inst/range_profile_hold_reg[28]/Q
|
|
net (fo=1, routed) 0.119 1.856 usb_inst/range_profile_hold[28]
|
|
SLICE_X2Y181 FDCE r usb_inst/range_profile_cap_reg[28]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y181 FDCE r usb_inst/range_profile_cap_reg[28]/C
|
|
clock pessimism -0.484 1.635
|
|
SLICE_X2Y181 FDCE (Hold_fdce_C_D) 0.063 1.698 usb_inst/range_profile_cap_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time -1.698
|
|
arrival time 1.856
|
|
-------------------------------------------------------------------
|
|
slack 0.158
|
|
|
|
Slack (MET) : 0.159ns (arrival time - required time)
|
|
Source: usb_inst/doppler_valid_sync_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_valid_sync_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.219ns (logic 0.164ns (74.792%) route 0.055ns (25.208%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.521ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y175 FDCE r usb_inst/doppler_valid_sync_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y175 FDCE (Prop_fdce_C_Q) 0.164 1.755 r usb_inst/doppler_valid_sync_reg[0]/Q
|
|
net (fo=1, routed) 0.055 1.810 usb_inst/doppler_valid_sync[0]
|
|
SLICE_X2Y175 FDCE r usb_inst/doppler_valid_sync_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y175 FDCE r usb_inst/doppler_valid_sync_reg[1]/C
|
|
clock pessimism -0.521 1.591
|
|
SLICE_X2Y175 FDCE (Hold_fdce_C_D) 0.060 1.651 usb_inst/doppler_valid_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.651
|
|
arrival time 1.810
|
|
-------------------------------------------------------------------
|
|
slack 0.159
|
|
|
|
Slack (MET) : 0.160ns (arrival time - required time)
|
|
Source: hb_counter_reg[16]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[16]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.250ns (logic 0.141ns (56.329%) route 0.109ns (43.671%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y179 FDRE r hb_counter_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y179 FDRE (Prop_fdre_C_Q) 0.141 1.735 r hb_counter_reg[16]/Q
|
|
net (fo=3, routed) 0.109 1.844 p_1_in[0]
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[16]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X7Y180 FDRE (Hold_fdre_C_D) 0.075 1.684 range_profile_reg_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time -1.684
|
|
arrival time 1.844
|
|
-------------------------------------------------------------------
|
|
slack 0.160
|
|
|
|
Slack (MET) : 0.160ns (arrival time - required time)
|
|
Source: hb_counter_reg[17]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_real_reg_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.220ns (logic 0.141ns (63.963%) route 0.079ns (36.037%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.509ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y179 FDRE r hb_counter_reg[17]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y179 FDRE (Prop_fdre_C_Q) 0.141 1.735 r hb_counter_reg[17]/Q
|
|
net (fo=3, routed) 0.079 1.814 p_1_in[1]
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[1]/C
|
|
clock pessimism -0.509 1.607
|
|
SLICE_X4Y179 FDRE (Hold_fdre_C_D) 0.047 1.654 doppler_real_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.654
|
|
arrival time 1.814
|
|
-------------------------------------------------------------------
|
|
slack 0.160
|
|
|
|
Slack (MET) : 0.165ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.251ns (logic 0.141ns (56.078%) route 0.110ns (43.922%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y177 FDCE (Prop_fdce_C_Q) 0.141 1.734 r usb_inst/range_profile_hold_reg[14]/Q
|
|
net (fo=1, routed) 0.110 1.844 usb_inst/range_profile_hold[14]
|
|
SLICE_X7Y178 FDCE r usb_inst/range_profile_cap_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y178 FDCE r usb_inst/range_profile_cap_reg[14]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X7Y178 FDCE (Hold_fdce_C_D) 0.072 1.679 usb_inst/range_profile_cap_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time -1.679
|
|
arrival time 1.844
|
|
-------------------------------------------------------------------
|
|
slack 0.165
|
|
|
|
Slack (MET) : 0.166ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.258ns (logic 0.141ns (54.592%) route 0.117ns (45.408%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y178 FDCE (Prop_fdce_C_Q) 0.141 1.734 r usb_inst/doppler_real_hold_reg[0]/Q
|
|
net (fo=1, routed) 0.117 1.851 usb_inst/doppler_real_hold[0]
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[0]/C
|
|
clock pessimism -0.484 1.633
|
|
SLICE_X2Y179 FDCE (Hold_fdce_C_D) 0.052 1.685 usb_inst/doppler_real_cap_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.685
|
|
arrival time 1.851
|
|
-------------------------------------------------------------------
|
|
slack 0.166
|
|
|
|
Slack (MET) : 0.167ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[4]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.257ns (logic 0.141ns (54.805%) route 0.116ns (45.195%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y176 FDRE (Prop_fdre_C_Q) 0.141 1.733 r doppler_imag_reg_reg[4]/Q
|
|
net (fo=1, routed) 0.116 1.849 usb_inst/doppler_imag_hold_reg[15]_0[4]
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[4]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Hold_fdce_C_D) 0.075 1.682 usb_inst/doppler_imag_hold_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.682
|
|
arrival time 1.849
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[21]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[21]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.252ns (logic 0.141ns (55.856%) route 0.111ns (44.144%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[21]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y180 FDRE (Prop_fdre_C_Q) 0.141 1.736 r range_profile_reg_reg[21]/Q
|
|
net (fo=1, routed) 0.111 1.847 usb_inst/range_profile_hold_reg[31]_0[21]
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[21]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[21]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X7Y179 FDCE (Hold_fdce_C_D) 0.072 1.680 usb_inst/range_profile_hold_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time -1.680
|
|
arrival time 1.847
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.167ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.251ns (logic 0.141ns (56.078%) route 0.110ns (43.922%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y180 FDRE (Prop_fdre_C_Q) 0.141 1.736 r range_profile_reg_reg[8]/Q
|
|
net (fo=1, routed) 0.110 1.846 usb_inst/range_profile_hold_reg[31]_0[8]
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[8]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X7Y179 FDCE (Hold_fdce_C_D) 0.071 1.679 usb_inst/range_profile_hold_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.679
|
|
arrival time 1.846
|
|
-------------------------------------------------------------------
|
|
slack 0.167
|
|
|
|
Slack (MET) : 0.168ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.259ns (logic 0.141ns (54.420%) route 0.118ns (45.580%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y178 FDCE (Prop_fdce_C_Q) 0.141 1.734 r usb_inst/doppler_real_hold_reg[1]/Q
|
|
net (fo=1, routed) 0.118 1.852 usb_inst/doppler_real_hold[1]
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_real_cap_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_real_cap_reg[1]/C
|
|
clock pessimism -0.484 1.632
|
|
SLICE_X2Y178 FDCE (Hold_fdce_C_D) 0.052 1.684 usb_inst/doppler_real_cap_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.684
|
|
arrival time 1.852
|
|
-------------------------------------------------------------------
|
|
slack 0.168
|
|
|
|
Slack (MET) : 0.171ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.252ns (logic 0.141ns (55.912%) route 0.111ns (44.088%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.114ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y176 FDCE (Prop_fdce_C_Q) 0.141 1.732 r usb_inst/doppler_imag_hold_reg[14]/Q
|
|
net (fo=1, routed) 0.111 1.843 usb_inst/doppler_imag_hold[14]
|
|
SLICE_X4Y177 FDCE r usb_inst/doppler_imag_cap_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.911 2.114 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y177 FDCE r usb_inst/doppler_imag_cap_reg[14]/C
|
|
clock pessimism -0.508 1.606
|
|
SLICE_X4Y177 FDCE (Hold_fdce_C_D) 0.066 1.672 usb_inst/doppler_imag_cap_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time -1.672
|
|
arrival time 1.843
|
|
-------------------------------------------------------------------
|
|
slack 0.171
|
|
|
|
Slack (MET) : 0.171ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[24]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[24]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.254ns (logic 0.141ns (55.470%) route 0.113ns (44.530%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y181 FDCE r usb_inst/range_profile_hold_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y181 FDCE (Prop_fdce_C_Q) 0.141 1.737 r usb_inst/range_profile_hold_reg[24]/Q
|
|
net (fo=1, routed) 0.113 1.850 usb_inst/range_profile_hold[24]
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[24]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X4Y180 FDCE (Hold_fdce_C_D) 0.070 1.679 usb_inst/range_profile_cap_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time -1.679
|
|
arrival time 1.850
|
|
-------------------------------------------------------------------
|
|
slack 0.171
|
|
|
|
Slack (MET) : 0.172ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.185ns (logic 0.128ns (69.202%) route 0.057ns (30.798%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y176 FDRE (Prop_fdre_C_Q) 0.128 1.720 r range_profile_reg_reg[6]/Q
|
|
net (fo=1, routed) 0.057 1.777 usb_inst/range_profile_hold_reg[31]_0[6]
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[6]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Hold_fdce_C_D) 0.000 1.605 usb_inst/range_profile_hold_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.605
|
|
arrival time 1.777
|
|
-------------------------------------------------------------------
|
|
slack 0.172
|
|
|
|
Slack (MET) : 0.173ns (arrival time - required time)
|
|
Source: hb_counter_reg[23]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_real_reg_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.264ns (logic 0.141ns (53.495%) route 0.123ns (46.505%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y180 FDRE r hb_counter_reg[23]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y180 FDRE (Prop_fdre_C_Q) 0.141 1.736 r hb_counter_reg[23]/Q
|
|
net (fo=3, routed) 0.123 1.859 p_1_in[7]
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[7]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X4Y179 FDRE (Hold_fdre_C_D) 0.078 1.686 doppler_real_reg_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.686
|
|
arrival time 1.859
|
|
-------------------------------------------------------------------
|
|
slack 0.173
|
|
|
|
Slack (MET) : 0.173ns (arrival time - required time)
|
|
Source: hb_counter_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[24]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.263ns (logic 0.141ns (53.649%) route 0.122ns (46.351%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y181 FDRE r hb_counter_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y181 FDRE (Prop_fdre_C_Q) 0.141 1.737 r hb_counter_reg[24]/Q
|
|
net (fo=4, routed) 0.122 1.859 ft601_gpio0_OBUF
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[24]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[24]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X6Y181 FDRE (Hold_fdre_C_D) 0.076 1.686 range_profile_reg_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time -1.686
|
|
arrival time 1.859
|
|
-------------------------------------------------------------------
|
|
slack 0.173
|
|
|
|
Slack (MET) : 0.174ns (arrival time - required time)
|
|
Source: hb_counter_reg[31]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[31]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.251ns (logic 0.141ns (56.105%) route 0.110ns (43.895%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y182 FDRE r hb_counter_reg[31]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y182 FDRE (Prop_fdre_C_Q) 0.141 1.738 r hb_counter_reg[31]/Q
|
|
net (fo=3, routed) 0.110 1.848 p_1_in[15]
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[31]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[31]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X6Y181 FDRE (Hold_fdre_C_D) 0.064 1.674 range_profile_reg_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time -1.674
|
|
arrival time 1.848
|
|
-------------------------------------------------------------------
|
|
slack 0.174
|
|
|
|
Slack (MET) : 0.174ns (arrival time - required time)
|
|
Source: hb_counter_reg[30]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[30]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.251ns (logic 0.141ns (56.086%) route 0.110ns (43.914%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y182 FDRE r hb_counter_reg[30]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y182 FDRE (Prop_fdre_C_Q) 0.141 1.738 r hb_counter_reg[30]/Q
|
|
net (fo=3, routed) 0.110 1.848 p_1_in[14]
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[30]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[30]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X6Y181 FDRE (Hold_fdre_C_D) 0.064 1.674 range_profile_reg_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time -1.674
|
|
arrival time 1.848
|
|
-------------------------------------------------------------------
|
|
slack 0.174
|
|
|
|
Slack (MET) : 0.176ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[13]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[13]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.249ns (logic 0.141ns (56.528%) route 0.108ns (43.472%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[13]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y177 FDCE (Prop_fdce_C_Q) 0.141 1.734 r usb_inst/range_profile_hold_reg[13]/Q
|
|
net (fo=1, routed) 0.108 1.842 usb_inst/range_profile_hold[13]
|
|
SLICE_X6Y178 FDCE r usb_inst/range_profile_cap_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y178 FDCE r usb_inst/range_profile_cap_reg[13]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X6Y178 FDCE (Hold_fdce_C_D) 0.059 1.666 usb_inst/range_profile_cap_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time -1.666
|
|
arrival time 1.842
|
|
-------------------------------------------------------------------
|
|
slack 0.176
|
|
|
|
Slack (MET) : 0.176ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[11]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[11]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.257ns (logic 0.141ns (54.760%) route 0.116ns (45.240%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y177 FDCE (Prop_fdce_C_Q) 0.141 1.735 r usb_inst/doppler_imag_hold_reg[11]/Q
|
|
net (fo=1, routed) 0.116 1.851 usb_inst/doppler_imag_hold[11]
|
|
SLICE_X0Y179 FDCE r usb_inst/doppler_imag_cap_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y179 FDCE r usb_inst/doppler_imag_cap_reg[11]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X0Y179 FDCE (Hold_fdce_C_D) 0.066 1.675 usb_inst/doppler_imag_cap_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -1.675
|
|
arrival time 1.851
|
|
-------------------------------------------------------------------
|
|
slack 0.176
|
|
|
|
Slack (MET) : 0.178ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[7]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.255ns (logic 0.141ns (55.309%) route 0.114ns (44.691%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y176 FDRE (Prop_fdre_C_Q) 0.141 1.733 r range_profile_reg_reg[7]/Q
|
|
net (fo=1, routed) 0.114 1.847 usb_inst/range_profile_hold_reg[31]_0[7]
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[7]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Hold_fdce_C_D) 0.064 1.669 usb_inst/range_profile_hold_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.669
|
|
arrival time 1.847
|
|
-------------------------------------------------------------------
|
|
slack 0.178
|
|
|
|
Slack (MET) : 0.179ns (arrival time - required time)
|
|
Source: hb_counter_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[22]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.265ns (logic 0.141ns (53.271%) route 0.124ns (46.729%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y180 FDRE r hb_counter_reg[22]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y180 FDRE (Prop_fdre_C_Q) 0.141 1.736 r hb_counter_reg[22]/Q
|
|
net (fo=3, routed) 0.124 1.860 p_1_in[6]
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[22]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[22]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X7Y180 FDRE (Hold_fdre_C_D) 0.072 1.681 range_profile_reg_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time -1.681
|
|
arrival time 1.860
|
|
-------------------------------------------------------------------
|
|
slack 0.179
|
|
|
|
Slack (MET) : 0.180ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.255ns (logic 0.141ns (55.352%) route 0.114ns (44.648%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y181 FDCE (Prop_fdce_C_Q) 0.141 1.738 r usb_inst/doppler_real_hold_reg[12]/Q
|
|
net (fo=1, routed) 0.114 1.852 usb_inst/doppler_real_hold[12]
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[12]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X2Y179 FDCE (Hold_fdce_C_D) 0.063 1.672 usb_inst/doppler_real_cap_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time -1.672
|
|
arrival time 1.852
|
|
-------------------------------------------------------------------
|
|
slack 0.180
|
|
|
|
Slack (MET) : 0.180ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[13]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[13]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.255ns (logic 0.141ns (55.352%) route 0.114ns (44.648%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[13]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y181 FDCE (Prop_fdce_C_Q) 0.141 1.738 r usb_inst/doppler_real_hold_reg[13]/Q
|
|
net (fo=1, routed) 0.114 1.852 usb_inst/doppler_real_hold[13]
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[13]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[13]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X2Y179 FDCE (Hold_fdce_C_D) 0.063 1.672 usb_inst/doppler_real_cap_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time -1.672
|
|
arrival time 1.852
|
|
-------------------------------------------------------------------
|
|
slack 0.180
|
|
|
|
Slack (MET) : 0.180ns (arrival time - required time)
|
|
Source: hb_counter_reg[10]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[10]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.307ns (logic 0.186ns (60.612%) route 0.121ns (39.388%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y177 FDRE r hb_counter_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y177 FDRE (Prop_fdre_C_Q) 0.141 1.734 f hb_counter_reg[10]/Q
|
|
net (fo=4, routed) 0.121 1.855 hb_counter_reg_n_0_[10]
|
|
SLICE_X3Y176 LUT1 (Prop_lut1_I0_O) 0.045 1.900 r range_profile_reg[10]_i_1/O
|
|
net (fo=1, routed) 0.000 1.900 p_2_out[10]
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[10]/C
|
|
clock pessimism -0.484 1.629
|
|
SLICE_X3Y176 FDRE (Hold_fdre_C_D) 0.091 1.720 range_profile_reg_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time -1.720
|
|
arrival time 1.900
|
|
-------------------------------------------------------------------
|
|
slack 0.180
|
|
|
|
Slack (MET) : 0.182ns (arrival time - required time)
|
|
Source: hb_counter_reg[29]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[29]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.248ns (logic 0.141ns (56.895%) route 0.107ns (43.105%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y182 FDRE r hb_counter_reg[29]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y182 FDRE (Prop_fdre_C_Q) 0.141 1.738 r hb_counter_reg[29]/Q
|
|
net (fo=3, routed) 0.107 1.845 p_1_in[13]
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[29]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[29]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X6Y181 FDRE (Hold_fdre_C_D) 0.053 1.663 range_profile_reg_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time -1.663
|
|
arrival time 1.845
|
|
-------------------------------------------------------------------
|
|
slack 0.182
|
|
|
|
Slack (MET) : 0.184ns (arrival time - required time)
|
|
Source: hb_counter_reg[22]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_real_reg_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.273ns (logic 0.141ns (51.708%) route 0.132ns (48.292%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y180 FDRE r hb_counter_reg[22]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y180 FDRE (Prop_fdre_C_Q) 0.141 1.736 r hb_counter_reg[22]/Q
|
|
net (fo=3, routed) 0.132 1.868 p_1_in[6]
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[6]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X4Y179 FDRE (Hold_fdre_C_D) 0.076 1.684 doppler_real_reg_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.684
|
|
arrival time 1.868
|
|
-------------------------------------------------------------------
|
|
slack 0.184
|
|
|
|
Slack (MET) : 0.184ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.263ns (logic 0.164ns (62.254%) route 0.099ns (37.746%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y176 FDCE (Prop_fdce_C_Q) 0.164 1.756 r usb_inst/range_profile_hold_reg[2]/Q
|
|
net (fo=1, routed) 0.099 1.855 usb_inst/range_profile_hold[2]
|
|
SLICE_X1Y176 FDCE r usb_inst/range_profile_cap_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y176 FDCE r usb_inst/range_profile_cap_reg[2]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X1Y176 FDCE (Hold_fdce_C_D) 0.066 1.671 usb_inst/range_profile_cap_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.671
|
|
arrival time 1.855
|
|
-------------------------------------------------------------------
|
|
slack 0.184
|
|
|
|
Slack (MET) : 0.185ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[16]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.269ns (logic 0.164ns (61.073%) route 0.105ns (38.927%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y180 FDCE (Prop_fdce_C_Q) 0.164 1.759 r usb_inst/range_profile_hold_reg[16]/Q
|
|
net (fo=1, routed) 0.105 1.864 usb_inst/range_profile_hold[16]
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[16]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[16]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X4Y180 FDCE (Hold_fdce_C_D) 0.070 1.679 usb_inst/range_profile_cap_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time -1.679
|
|
arrival time 1.864
|
|
-------------------------------------------------------------------
|
|
slack 0.185
|
|
|
|
Slack (MET) : 0.185ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.269ns (logic 0.164ns (61.073%) route 0.105ns (38.927%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y181 FDRE r range_profile_reg_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y181 FDRE (Prop_fdre_C_Q) 0.164 1.760 r range_profile_reg_reg[20]/Q
|
|
net (fo=1, routed) 0.105 1.865 usb_inst/range_profile_hold_reg[31]_0[20]
|
|
SLICE_X4Y181 FDCE r usb_inst/range_profile_hold_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y181 FDCE r usb_inst/range_profile_hold_reg[20]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X4Y181 FDCE (Hold_fdce_C_D) 0.070 1.680 usb_inst/range_profile_hold_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time -1.680
|
|
arrival time 1.865
|
|
-------------------------------------------------------------------
|
|
slack 0.185
|
|
|
|
Slack (MET) : 0.185ns (arrival time - required time)
|
|
Source: hb_counter_reg[18]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[18]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.247ns (logic 0.141ns (57.126%) route 0.106ns (42.874%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y179 FDRE r hb_counter_reg[18]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y179 FDRE (Prop_fdre_C_Q) 0.141 1.735 r hb_counter_reg[18]/Q
|
|
net (fo=3, routed) 0.106 1.841 p_1_in[2]
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[18]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X7Y180 FDRE (Hold_fdre_C_D) 0.047 1.656 range_profile_reg_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time -1.656
|
|
arrival time 1.841
|
|
-------------------------------------------------------------------
|
|
slack 0.185
|
|
|
|
Slack (MET) : 0.187ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[18]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[18]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.247ns (logic 0.141ns (57.185%) route 0.106ns (42.815%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[18]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y180 FDRE (Prop_fdre_C_Q) 0.141 1.736 r range_profile_reg_reg[18]/Q
|
|
net (fo=1, routed) 0.106 1.842 usb_inst/range_profile_hold_reg[31]_0[18]
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[18]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[18]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X7Y179 FDCE (Hold_fdce_C_D) 0.047 1.655 usb_inst/range_profile_hold_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time -1.655
|
|
arrival time 1.842
|
|
-------------------------------------------------------------------
|
|
slack 0.187
|
|
|
|
Slack (MET) : 0.187ns (arrival time - required time)
|
|
Source: hb_counter_reg[31]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_real_reg_reg[15]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.271ns (logic 0.141ns (52.013%) route 0.130ns (47.987%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.509ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y182 FDRE r hb_counter_reg[31]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y182 FDRE (Prop_fdre_C_Q) 0.141 1.738 r hb_counter_reg[31]/Q
|
|
net (fo=3, routed) 0.130 1.868 p_1_in[15]
|
|
SLICE_X4Y182 FDRE r doppler_real_reg_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y182 FDRE r doppler_real_reg_reg[15]/C
|
|
clock pessimism -0.509 1.610
|
|
SLICE_X4Y182 FDRE (Hold_fdre_C_D) 0.071 1.681 doppler_real_reg_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -1.681
|
|
arrival time 1.868
|
|
-------------------------------------------------------------------
|
|
slack 0.187
|
|
|
|
Slack (MET) : 0.187ns (arrival time - required time)
|
|
Source: usb_inst/rx_data_captured_reg[28]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[4]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.247ns (logic 0.141ns (57.018%) route 0.106ns (42.982%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[28]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y174 FDCE (Prop_fdce_C_Q) 0.141 1.732 r usb_inst/rx_data_captured_reg[28]/Q
|
|
net (fo=1, routed) 0.106 1.838 usb_inst/p_0_in[4]
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[4]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X1Y174 FDCE (Hold_fdce_C_D) 0.047 1.651 usb_inst/cmd_opcode_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.651
|
|
arrival time 1.838
|
|
-------------------------------------------------------------------
|
|
slack 0.187
|
|
|
|
Slack (MET) : 0.188ns (arrival time - required time)
|
|
Source: usb_inst/rx_data_captured_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_value_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.256ns (logic 0.141ns (55.136%) route 0.115ns (44.864%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y180 FDCE r usb_inst/rx_data_captured_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y180 FDCE (Prop_fdce_C_Q) 0.141 1.737 r usb_inst/rx_data_captured_reg[2]/Q
|
|
net (fo=1, routed) 0.115 1.852 usb_inst/rx_data_captured_reg_n_0_[2]
|
|
SLICE_X2Y182 FDCE r usb_inst/cmd_value_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y182 FDCE r usb_inst/cmd_value_reg[2]/C
|
|
clock pessimism -0.508 1.612
|
|
SLICE_X2Y182 FDCE (Hold_fdce_C_D) 0.052 1.664 usb_inst/cmd_value_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.664
|
|
arrival time 1.852
|
|
-------------------------------------------------------------------
|
|
slack 0.188
|
|
|
|
Slack (MET) : 0.188ns (arrival time - required time)
|
|
Source: usb_inst/cfar_valid_sync_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_valid_sync_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.263ns (logic 0.141ns (53.659%) route 0.122ns (46.341%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.522ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_valid_sync_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y180 FDCE (Prop_fdce_C_Q) 0.141 1.737 r usb_inst/cfar_valid_sync_reg[0]/Q
|
|
net (fo=1, routed) 0.122 1.859 usb_inst/cfar_valid_sync[0]
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_valid_sync_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_valid_sync_reg[1]/C
|
|
clock pessimism -0.522 1.596
|
|
SLICE_X0Y180 FDCE (Hold_fdce_C_D) 0.075 1.671 usb_inst/cfar_valid_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.671
|
|
arrival time 1.859
|
|
-------------------------------------------------------------------
|
|
slack 0.188
|
|
|
|
Slack (MET) : 0.188ns (arrival time - required time)
|
|
Source: cfar_detection_reg_reg/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_detection_hold_reg/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.293ns (logic 0.186ns (63.410%) route 0.107ns (36.590%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.509ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y180 FDRE r cfar_detection_reg_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y180 FDRE (Prop_fdre_C_Q) 0.141 1.737 r cfar_detection_reg_reg/Q
|
|
net (fo=2, routed) 0.107 1.844 usb_inst/cfar_detection_hold_reg_0
|
|
SLICE_X0Y180 LUT3 (Prop_lut3_I0_O) 0.045 1.889 r usb_inst/cfar_detection_hold_i_1/O
|
|
net (fo=1, routed) 0.000 1.889 usb_inst/cfar_detection_hold_i_1_n_0
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_detection_hold_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_detection_hold_reg/C
|
|
clock pessimism -0.509 1.609
|
|
SLICE_X0Y180 FDCE (Hold_fdce_C_D) 0.092 1.701 usb_inst/cfar_detection_hold_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.701
|
|
arrival time 1.889
|
|
-------------------------------------------------------------------
|
|
slack 0.188
|
|
|
|
Slack (MET) : 0.189ns (arrival time - required time)
|
|
Source: hb_counter_reg[20]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_real_reg_reg[4]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.277ns (logic 0.141ns (50.983%) route 0.136ns (49.017%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y180 FDRE r hb_counter_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y180 FDRE (Prop_fdre_C_Q) 0.141 1.736 r hb_counter_reg[20]/Q
|
|
net (fo=3, routed) 0.136 1.872 p_1_in[4]
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[4]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X4Y179 FDRE (Hold_fdre_C_D) 0.075 1.683 doppler_real_reg_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.683
|
|
arrival time 1.872
|
|
-------------------------------------------------------------------
|
|
slack 0.189
|
|
|
|
Slack (MET) : 0.189ns (arrival time - required time)
|
|
Source: ft601_txe
|
|
(input port clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_oe_reg/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Slow Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.330ns (logic 1.579ns (36.469%) route 2.751ns (63.531%))
|
|
Logic Levels: 4 (IBUF=1 LUT3=1 LUT6=2)
|
|
Input Delay: 1.000ns
|
|
Clock Path Skew: 4.860ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 4.860ns
|
|
Source Clock Delay (SCD): 0.000ns
|
|
Clock Pessimism Removal (CPR): -0.000ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
input delay 1.000 1.000
|
|
E17 0.000 1.000 f ft601_txe (IN)
|
|
net (fo=0) 0.000 1.000 ft601_txe
|
|
E17 IBUF (Prop_ibuf_I_O) 1.327 2.327 f ft601_txe_IBUF_inst/O
|
|
net (fo=13, routed) 2.006 4.333 usb_inst/ft601_txe_IBUF
|
|
SLICE_X0Y194 LUT6 (Prop_lut6_I2_O) 0.084 4.417 r usb_inst/ft601_wr_n_i_3/O
|
|
net (fo=1, routed) 0.273 4.691 usb_inst/ft601_wr_n_i_3_n_0
|
|
SLICE_X0Y195 LUT6 (Prop_lut6_I5_O) 0.084 4.775 r usb_inst/ft601_wr_n_i_1/O
|
|
net (fo=2, routed) 0.472 5.246 usb_inst/ft601_wr_n_i_1_n_0
|
|
SLICE_X0Y195 LUT3 (Prop_lut3_I2_O) 0.084 5.330 r usb_inst/ft601_data_oe_i_1/O
|
|
net (fo=1, routed) 0.000 5.330 usb_inst/ft601_data_oe_i_1_n_0
|
|
SLICE_X0Y195 FDPE r usb_inst/ft601_data_oe_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.552 4.860 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y195 FDPE r usb_inst/ft601_data_oe_reg/C
|
|
clock pessimism 0.000 4.860
|
|
clock uncertainty 0.061 4.922
|
|
SLICE_X0Y195 FDPE (Hold_fdpe_C_D) 0.220 5.142 usb_inst/ft601_data_oe_reg
|
|
-------------------------------------------------------------------
|
|
required time -5.142
|
|
arrival time 5.330
|
|
-------------------------------------------------------------------
|
|
slack 0.189
|
|
|
|
Slack (MET) : 0.190ns (arrival time - required time)
|
|
Source: hb_counter_reg[8]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_imag_reg_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.264ns (logic 0.141ns (53.473%) route 0.123ns (46.527%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y177 FDRE r hb_counter_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y177 FDRE (Prop_fdre_C_Q) 0.141 1.734 r hb_counter_reg[8]/Q
|
|
net (fo=3, routed) 0.123 1.857 hb_counter_reg_n_0_[8]
|
|
SLICE_X6Y176 FDRE r doppler_imag_reg_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y176 FDRE r doppler_imag_reg_reg[8]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X6Y176 FDRE (Hold_fdre_C_D) 0.063 1.667 doppler_imag_reg_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.667
|
|
arrival time 1.857
|
|
-------------------------------------------------------------------
|
|
slack 0.190
|
|
|
|
Slack (MET) : 0.190ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[15]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.278ns (logic 0.164ns (59.007%) route 0.114ns (40.993%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.114ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y177 FDRE r range_profile_reg_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y177 FDRE (Prop_fdre_C_Q) 0.164 1.757 r range_profile_reg_reg[15]/Q
|
|
net (fo=1, routed) 0.114 1.871 usb_inst/range_profile_hold_reg[31]_0[15]
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.911 2.114 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[15]/C
|
|
clock pessimism -0.508 1.606
|
|
SLICE_X7Y177 FDCE (Hold_fdce_C_D) 0.075 1.681 usb_inst/range_profile_hold_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -1.681
|
|
arrival time 1.871
|
|
-------------------------------------------------------------------
|
|
slack 0.190
|
|
|
|
Slack (MET) : 0.195ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[19]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[19]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.299ns (logic 0.141ns (47.082%) route 0.158ns (52.918%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[19]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y179 FDCE (Prop_fdce_C_Q) 0.141 1.735 r usb_inst/range_profile_hold_reg[19]/Q
|
|
net (fo=1, routed) 0.158 1.893 usb_inst/range_profile_hold[19]
|
|
SLICE_X3Y178 FDCE r usb_inst/range_profile_cap_reg[19]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y178 FDCE r usb_inst/range_profile_cap_reg[19]/C
|
|
clock pessimism -0.484 1.632
|
|
SLICE_X3Y178 FDCE (Hold_fdce_C_D) 0.066 1.698 usb_inst/range_profile_cap_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time -1.698
|
|
arrival time 1.893
|
|
-------------------------------------------------------------------
|
|
slack 0.195
|
|
|
|
Slack (MET) : 0.196ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.248ns (logic 0.128ns (51.670%) route 0.120ns (48.330%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y176 FDCE (Prop_fdce_C_Q) 0.128 1.719 r usb_inst/doppler_imag_hold_reg[3]/Q
|
|
net (fo=1, routed) 0.120 1.839 usb_inst/doppler_imag_hold[3]
|
|
SLICE_X3Y177 FDCE r usb_inst/doppler_imag_cap_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y177 FDCE r usb_inst/doppler_imag_cap_reg[3]/C
|
|
clock pessimism -0.484 1.631
|
|
SLICE_X3Y177 FDCE (Hold_fdce_C_D) 0.012 1.643 usb_inst/doppler_imag_cap_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.643
|
|
arrival time 1.839
|
|
-------------------------------------------------------------------
|
|
slack 0.196
|
|
|
|
Slack (MET) : 0.196ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.258ns (logic 0.141ns (54.688%) route 0.117ns (45.312%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y176 FDRE (Prop_fdre_C_Q) 0.141 1.733 r doppler_imag_reg_reg[2]/Q
|
|
net (fo=1, routed) 0.117 1.850 usb_inst/doppler_imag_hold_reg[15]_0[2]
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[2]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Hold_fdce_C_D) 0.047 1.654 usb_inst/doppler_imag_hold_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.654
|
|
arrival time 1.850
|
|
-------------------------------------------------------------------
|
|
slack 0.196
|
|
|
|
Slack (MET) : 0.197ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[12]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.256ns (logic 0.141ns (55.069%) route 0.115ns (44.931%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y179 FDRE r doppler_imag_reg_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y179 FDRE (Prop_fdre_C_Q) 0.141 1.735 r doppler_imag_reg_reg[12]/Q
|
|
net (fo=1, routed) 0.115 1.850 usb_inst/doppler_imag_hold_reg[15]_0[12]
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_imag_hold_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_imag_hold_reg[12]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X4Y178 FDCE (Hold_fdce_C_D) 0.046 1.653 usb_inst/doppler_imag_hold_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time -1.653
|
|
arrival time 1.850
|
|
-------------------------------------------------------------------
|
|
slack 0.197
|
|
|
|
Slack (MET) : 0.198ns (arrival time - required time)
|
|
Source: usb_inst/rx_data_captured_reg[25]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.283ns (logic 0.141ns (49.758%) route 0.142ns (50.242%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.123ns
|
|
Source Clock Delay (SCD): 1.600ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 1.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y186 FDCE r usb_inst/rx_data_captured_reg[25]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y186 FDCE (Prop_fdce_C_Q) 0.141 1.741 r usb_inst/rx_data_captured_reg[25]/Q
|
|
net (fo=1, routed) 0.142 1.883 usb_inst/p_0_in[1]
|
|
SLICE_X1Y185 FDCE r usb_inst/cmd_opcode_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.920 2.123 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y185 FDCE r usb_inst/cmd_opcode_reg[1]/C
|
|
clock pessimism -0.508 1.615
|
|
SLICE_X1Y185 FDCE (Hold_fdce_C_D) 0.070 1.685 usb_inst/cmd_opcode_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.685
|
|
arrival time 1.883
|
|
-------------------------------------------------------------------
|
|
slack 0.198
|
|
|
|
Slack (MET) : 0.199ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.233ns (logic 0.128ns (55.037%) route 0.105ns (44.963%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y179 FDCE (Prop_fdce_C_Q) 0.128 1.722 r usb_inst/range_profile_hold_reg[8]/Q
|
|
net (fo=1, routed) 0.105 1.827 usb_inst/range_profile_hold[8]
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[8]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X4Y180 FDCE (Hold_fdce_C_D) 0.019 1.628 usb_inst/range_profile_cap_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.628
|
|
arrival time 1.827
|
|
-------------------------------------------------------------------
|
|
slack 0.199
|
|
|
|
Slack (MET) : 0.199ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[4]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.247ns (logic 0.128ns (51.856%) route 0.119ns (48.144%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y178 FDCE (Prop_fdce_C_Q) 0.128 1.721 r usb_inst/doppler_real_hold_reg[4]/Q
|
|
net (fo=1, routed) 0.119 1.840 usb_inst/doppler_real_hold[4]
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_real_cap_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_real_cap_reg[4]/C
|
|
clock pessimism -0.484 1.632
|
|
SLICE_X2Y178 FDCE (Hold_fdce_C_D) 0.009 1.641 usb_inst/doppler_real_cap_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.641
|
|
arrival time 1.840
|
|
-------------------------------------------------------------------
|
|
slack 0.199
|
|
|
|
Slack (MET) : 0.199ns (arrival time - required time)
|
|
Source: usb_inst/cmd_opcode_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: stream_control_reg_reg[0]/D
|
|
(rising edge-triggered cell FDSE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.303ns (logic 0.186ns (61.312%) route 0.117ns (38.688%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.598ns
|
|
Clock Pessimism Removal (CPR): 0.509ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.645 1.598 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y182 FDCE r usb_inst/cmd_opcode_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y182 FDCE (Prop_fdce_C_Q) 0.141 1.739 r usb_inst/cmd_opcode_reg[0]/Q
|
|
net (fo=4, routed) 0.117 1.856 usb_inst/cmd_opcode[0]
|
|
SLICE_X1Y182 LUT6 (Prop_lut6_I0_O) 0.045 1.901 r usb_inst/stream_control_reg[0]_i_1/O
|
|
net (fo=1, routed) 0.000 1.901 usb_inst_n_6
|
|
SLICE_X1Y182 FDSE r stream_control_reg_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y182 FDSE r stream_control_reg_reg[0]/C
|
|
clock pessimism -0.509 1.611
|
|
SLICE_X1Y182 FDSE (Hold_fdse_C_D) 0.091 1.702 stream_control_reg_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.702
|
|
arrival time 1.901
|
|
-------------------------------------------------------------------
|
|
slack 0.199
|
|
|
|
Slack (MET) : 0.199ns (arrival time - required time)
|
|
Source: usb_inst/cmd_opcode_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: stream_control_reg_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.304ns (logic 0.186ns (61.111%) route 0.118ns (38.889%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.598ns
|
|
Clock Pessimism Removal (CPR): 0.509ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.645 1.598 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y182 FDCE r usb_inst/cmd_opcode_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y182 FDCE (Prop_fdce_C_Q) 0.141 1.739 r usb_inst/cmd_opcode_reg[0]/Q
|
|
net (fo=4, routed) 0.118 1.857 usb_inst/cmd_opcode[0]
|
|
SLICE_X1Y182 LUT6 (Prop_lut6_I0_O) 0.045 1.902 r usb_inst/stream_control_reg[1]_i_1/O
|
|
net (fo=1, routed) 0.000 1.902 usb_inst_n_7
|
|
SLICE_X1Y182 FDRE r stream_control_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y182 FDRE r stream_control_reg_reg[1]/C
|
|
clock pessimism -0.509 1.611
|
|
SLICE_X1Y182 FDRE (Hold_fdre_C_D) 0.092 1.703 stream_control_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.703
|
|
arrival time 1.902
|
|
-------------------------------------------------------------------
|
|
slack 0.199
|
|
|
|
Slack (MET) : 0.201ns (arrival time - required time)
|
|
Source: usb_inst/doppler_data_pending_reg/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[8]/CE
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.809ns (logic 0.254ns (31.416%) route 0.555ns (68.584%))
|
|
Logic Levels: 2 (LUT6=2)
|
|
Clock Path Skew: 0.036ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.600ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 1.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y186 FDCE r usb_inst/doppler_data_pending_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X2Y186 FDCE (Prop_fdce_C_Q) 0.164 1.764 r usb_inst/doppler_data_pending_reg/Q
|
|
net (fo=12, routed) 0.222 1.986 usb_inst/doppler_data_pending_reg_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I4_O) 0.045 2.031 r usb_inst/ft601_data_out[31]_i_3/O
|
|
net (fo=1, routed) 0.048 2.079 usb_inst/ft601_data_out[31]_i_3_n_0
|
|
SLICE_X1Y186 LUT6 (Prop_lut6_I5_O) 0.045 2.124 r usb_inst/ft601_data_out[31]_i_1/O
|
|
net (fo=32, routed) 0.284 2.408 usb_inst/ft601_data_out[31]_i_1_n_0
|
|
OLOGIC_X0Y187 FDCE r usb_inst/ft601_data_out_reg[8]/CE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y187 FDCE r usb_inst/ft601_data_out_reg[8]/C
|
|
clock pessimism -0.484 1.636
|
|
OLOGIC_X0Y187 FDCE (Hold_fdce_C_CE) 0.572 2.208 usb_inst/ft601_data_out_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -2.208
|
|
arrival time 2.408
|
|
-------------------------------------------------------------------
|
|
slack 0.201
|
|
|
|
Slack (MET) : 0.201ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.286ns (logic 0.141ns (49.243%) route 0.145ns (50.757%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y177 FDCE (Prop_fdce_C_Q) 0.141 1.735 r usb_inst/doppler_imag_hold_reg[2]/Q
|
|
net (fo=1, routed) 0.145 1.880 usb_inst/doppler_imag_hold[2]
|
|
SLICE_X1Y179 FDCE r usb_inst/doppler_imag_cap_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y179 FDCE r usb_inst/doppler_imag_cap_reg[2]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X1Y179 FDCE (Hold_fdce_C_D) 0.070 1.679 usb_inst/doppler_imag_cap_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.679
|
|
arrival time 1.880
|
|
-------------------------------------------------------------------
|
|
slack 0.201
|
|
|
|
Slack (MET) : 0.204ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.241ns (logic 0.128ns (53.196%) route 0.113ns (46.804%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y176 FDRE (Prop_fdre_C_Q) 0.128 1.720 r doppler_imag_reg_reg[6]/Q
|
|
net (fo=1, routed) 0.113 1.833 usb_inst/doppler_imag_hold_reg[15]_0[6]
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[6]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Hold_fdce_C_D) 0.022 1.629 usb_inst/doppler_imag_hold_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.629
|
|
arrival time 1.833
|
|
-------------------------------------------------------------------
|
|
slack 0.204
|
|
|
|
Slack (MET) : 0.204ns (arrival time - required time)
|
|
Source: hb_counter_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_real_reg_reg[8]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.290ns (logic 0.141ns (48.676%) route 0.149ns (51.324%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y181 FDRE r hb_counter_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y181 FDRE (Prop_fdre_C_Q) 0.141 1.737 r hb_counter_reg[24]/Q
|
|
net (fo=4, routed) 0.149 1.886 ft601_gpio0_OBUF
|
|
SLICE_X5Y183 FDRE r doppler_real_reg_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y183 FDRE r doppler_real_reg_reg[8]/C
|
|
clock pessimism -0.508 1.612
|
|
SLICE_X5Y183 FDRE (Hold_fdre_C_D) 0.070 1.682 doppler_real_reg_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.682
|
|
arrival time 1.886
|
|
-------------------------------------------------------------------
|
|
slack 0.204
|
|
|
|
Slack (MET) : 0.204ns (arrival time - required time)
|
|
Source: hb_counter_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.320ns (logic 0.141ns (44.095%) route 0.179ns (55.905%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y176 FDRE r hb_counter_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y176 FDRE (Prop_fdre_C_Q) 0.141 1.732 r hb_counter_reg[6]/Q
|
|
net (fo=3, routed) 0.179 1.911 hb_counter_reg_n_0_[6]
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[6]/C
|
|
clock pessimism -0.484 1.629
|
|
SLICE_X3Y176 FDRE (Hold_fdre_C_D) 0.078 1.707 range_profile_reg_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.707
|
|
arrival time 1.911
|
|
-------------------------------------------------------------------
|
|
slack 0.204
|
|
|
|
Slack (MET) : 0.204ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[14]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.264ns (logic 0.164ns (62.029%) route 0.100ns (37.971%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y176 FDRE r doppler_imag_reg_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y176 FDRE (Prop_fdre_C_Q) 0.164 1.755 r doppler_imag_reg_reg[14]/Q
|
|
net (fo=1, routed) 0.100 1.855 usb_inst/doppler_imag_hold_reg[15]_0[14]
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[14]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X4Y176 FDCE (Hold_fdce_C_D) 0.047 1.651 usb_inst/doppler_imag_hold_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time -1.651
|
|
arrival time 1.855
|
|
-------------------------------------------------------------------
|
|
slack 0.204
|
|
|
|
Slack (MET) : 0.207ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[15]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.267ns (logic 0.164ns (61.407%) route 0.103ns (38.593%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y176 FDRE r doppler_imag_reg_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y176 FDRE (Prop_fdre_C_Q) 0.164 1.755 r doppler_imag_reg_reg[15]/Q
|
|
net (fo=1, routed) 0.103 1.858 usb_inst/doppler_imag_hold_reg[15]_0[15]
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[15]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X4Y176 FDCE (Hold_fdce_C_D) 0.047 1.651 usb_inst/doppler_imag_hold_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -1.651
|
|
arrival time 1.858
|
|
-------------------------------------------------------------------
|
|
slack 0.207
|
|
|
|
Slack (MET) : 0.207ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.319ns (logic 0.141ns (44.184%) route 0.178ns (55.816%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.042ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y176 FDCE (Prop_fdce_C_Q) 0.141 1.732 r usb_inst/doppler_imag_hold_reg[10]/Q
|
|
net (fo=1, routed) 0.178 1.910 usb_inst/doppler_imag_hold[10]
|
|
SLICE_X3Y179 FDCE r usb_inst/doppler_imag_cap_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y179 FDCE r usb_inst/doppler_imag_cap_reg[10]/C
|
|
clock pessimism -0.484 1.633
|
|
SLICE_X3Y179 FDCE (Hold_fdce_C_D) 0.070 1.703 usb_inst/doppler_imag_cap_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time -1.703
|
|
arrival time 1.910
|
|
-------------------------------------------------------------------
|
|
slack 0.207
|
|
|
|
Slack (MET) : 0.207ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[7]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.247ns (logic 0.128ns (51.784%) route 0.119ns (48.216%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y176 FDRE (Prop_fdre_C_Q) 0.128 1.720 r doppler_imag_reg_reg[7]/Q
|
|
net (fo=1, routed) 0.119 1.839 usb_inst/doppler_imag_hold_reg[15]_0[7]
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[7]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Hold_fdce_C_D) 0.025 1.632 usb_inst/doppler_imag_hold_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.632
|
|
arrival time 1.839
|
|
-------------------------------------------------------------------
|
|
slack 0.207
|
|
|
|
Slack (MET) : 0.208ns (arrival time - required time)
|
|
Source: usb_inst/FSM_onehot_read_state_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[0]/D
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.186ns (59.588%) route 0.126ns (40.412%))
|
|
Logic Levels: 1 (LUT3=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.221ns
|
|
Source Clock Delay (SCD): 1.692ns
|
|
Clock Pessimism Removal (CPR): 0.515ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 1.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y209 FDCE (Prop_fdce_C_Q) 0.141 1.833 r usb_inst/FSM_onehot_read_state_reg[1]/Q
|
|
net (fo=7, routed) 0.126 1.960 usb_inst/FSM_onehot_read_state_reg_n_0_[1]
|
|
SLICE_X0Y209 LUT3 (Prop_lut3_I1_O) 0.045 2.005 r usb_inst/FSM_onehot_read_state[0]_i_1/O
|
|
net (fo=1, routed) 0.000 2.005 usb_inst/FSM_onehot_read_state[0]_i_1_n_0
|
|
SLICE_X0Y209 FDPE r usb_inst/FSM_onehot_read_state_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.017 2.221 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDPE r usb_inst/FSM_onehot_read_state_reg[0]/C
|
|
clock pessimism -0.515 1.705
|
|
SLICE_X0Y209 FDPE (Hold_fdpe_C_D) 0.091 1.796 usb_inst/FSM_onehot_read_state_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.796
|
|
arrival time 2.005
|
|
-------------------------------------------------------------------
|
|
slack 0.208
|
|
|
|
Slack (MET) : 0.210ns (arrival time - required time)
|
|
Source: hb_counter_reg[7]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_imag_reg_reg[7]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.319ns (logic 0.141ns (44.143%) route 0.178ns (55.857%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y176 FDRE r hb_counter_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y176 FDRE (Prop_fdre_C_Q) 0.141 1.732 r hb_counter_reg[7]/Q
|
|
net (fo=3, routed) 0.178 1.910 hb_counter_reg_n_0_[7]
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[7]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[7]/C
|
|
clock pessimism -0.484 1.629
|
|
SLICE_X0Y176 FDRE (Hold_fdre_C_D) 0.071 1.700 doppler_imag_reg_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.700
|
|
arrival time 1.910
|
|
-------------------------------------------------------------------
|
|
slack 0.210
|
|
|
|
Slack (MET) : 0.212ns (arrival time - required time)
|
|
Source: usb_inst/FSM_onehot_read_state_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.317ns (logic 0.186ns (58.753%) route 0.131ns (41.247%))
|
|
Logic Levels: 1 (LUT2=1)
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.221ns
|
|
Source Clock Delay (SCD): 1.692ns
|
|
Clock Pessimism Removal (CPR): 0.515ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.739 1.692 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X1Y209 FDCE (Prop_fdce_C_Q) 0.141 1.833 r usb_inst/FSM_onehot_read_state_reg[1]/Q
|
|
net (fo=7, routed) 0.131 1.964 usb_inst/FSM_onehot_read_state_reg_n_0_[1]
|
|
SLICE_X0Y209 LUT2 (Prop_lut2_I0_O) 0.045 2.009 r usb_inst/FSM_onehot_read_state[2]_i_1/O
|
|
net (fo=1, routed) 0.000 2.009 usb_inst/FSM_onehot_read_state[2]_i_1_n_0
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.017 2.221 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[2]/C
|
|
clock pessimism -0.515 1.705
|
|
SLICE_X0Y209 FDCE (Hold_fdce_C_D) 0.092 1.797 usb_inst/FSM_onehot_read_state_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.797
|
|
arrival time 2.009
|
|
-------------------------------------------------------------------
|
|
slack 0.212
|
|
|
|
Slack (MET) : 0.212ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[15]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[15]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.239ns (logic 0.128ns (53.641%) route 0.111ns (46.359%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y177 FDCE (Prop_fdce_C_Q) 0.128 1.721 r usb_inst/range_profile_hold_reg[15]/Q
|
|
net (fo=1, routed) 0.111 1.832 usb_inst/range_profile_hold[15]
|
|
SLICE_X7Y176 FDCE r usb_inst/range_profile_cap_reg[15]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y176 FDCE r usb_inst/range_profile_cap_reg[15]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X7Y176 FDCE (Hold_fdce_C_D) 0.016 1.620 usb_inst/range_profile_cap_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -1.620
|
|
arrival time 1.832
|
|
-------------------------------------------------------------------
|
|
slack 0.212
|
|
|
|
Slack (MET) : 0.212ns (arrival time - required time)
|
|
Source: hb_counter_reg[27]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_real_reg_reg[11]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.274ns (logic 0.141ns (51.469%) route 0.133ns (48.531%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y181 FDRE r hb_counter_reg[27]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y181 FDRE (Prop_fdre_C_Q) 0.141 1.737 r hb_counter_reg[27]/Q
|
|
net (fo=3, routed) 0.133 1.870 p_1_in[11]
|
|
SLICE_X4Y182 FDRE r doppler_real_reg_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y182 FDRE r doppler_real_reg_reg[11]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X4Y182 FDRE (Hold_fdre_C_D) 0.047 1.658 doppler_real_reg_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -1.658
|
|
arrival time 1.870
|
|
-------------------------------------------------------------------
|
|
slack 0.212
|
|
|
|
Slack (MET) : 0.213ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[4]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.242ns (logic 0.128ns (52.975%) route 0.114ns (47.025%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y177 FDCE (Prop_fdce_C_Q) 0.128 1.722 r usb_inst/doppler_imag_hold_reg[4]/Q
|
|
net (fo=1, routed) 0.114 1.836 usb_inst/doppler_imag_hold[4]
|
|
SLICE_X1Y177 FDCE r usb_inst/doppler_imag_cap_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y177 FDCE r usb_inst/doppler_imag_cap_reg[4]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X1Y177 FDCE (Hold_fdce_C_D) 0.016 1.623 usb_inst/doppler_imag_cap_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.623
|
|
arrival time 1.836
|
|
-------------------------------------------------------------------
|
|
slack 0.213
|
|
|
|
Slack (MET) : 0.213ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[9]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[9]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.249ns (logic 0.148ns (59.371%) route 0.101ns (40.629%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y176 FDRE r doppler_imag_reg_reg[9]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y176 FDRE (Prop_fdre_C_Q) 0.148 1.739 r doppler_imag_reg_reg[9]/Q
|
|
net (fo=1, routed) 0.101 1.840 usb_inst/doppler_imag_hold_reg[15]_0[9]
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[9]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X4Y176 FDCE (Hold_fdce_C_D) 0.023 1.627 usb_inst/doppler_imag_hold_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time -1.627
|
|
arrival time 1.840
|
|
-------------------------------------------------------------------
|
|
slack 0.213
|
|
|
|
Slack (MET) : 0.214ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.319ns (logic 0.141ns (44.185%) route 0.178ns (55.815%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y178 FDCE (Prop_fdce_C_Q) 0.141 1.734 r usb_inst/doppler_real_hold_reg[3]/Q
|
|
net (fo=1, routed) 0.178 1.912 usb_inst/doppler_real_hold[3]
|
|
SLICE_X1Y178 FDCE r usb_inst/doppler_real_cap_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y178 FDCE r usb_inst/doppler_real_cap_reg[3]/C
|
|
clock pessimism -0.484 1.632
|
|
SLICE_X1Y178 FDCE (Hold_fdce_C_D) 0.066 1.698 usb_inst/doppler_real_cap_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.698
|
|
arrival time 1.912
|
|
-------------------------------------------------------------------
|
|
slack 0.214
|
|
|
|
Slack (MET) : 0.214ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[6]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.246ns (logic 0.128ns (51.983%) route 0.118ns (48.017%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.114ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y178 FDCE (Prop_fdce_C_Q) 0.128 1.721 r usb_inst/doppler_real_hold_reg[6]/Q
|
|
net (fo=1, routed) 0.118 1.839 usb_inst/doppler_real_hold[6]
|
|
SLICE_X4Y177 FDCE r usb_inst/doppler_real_cap_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.911 2.114 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y177 FDCE r usb_inst/doppler_real_cap_reg[6]/C
|
|
clock pessimism -0.508 1.606
|
|
SLICE_X4Y177 FDCE (Hold_fdce_C_D) 0.019 1.625 usb_inst/doppler_real_cap_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.625
|
|
arrival time 1.839
|
|
-------------------------------------------------------------------
|
|
slack 0.214
|
|
|
|
Slack (MET) : 0.215ns (arrival time - required time)
|
|
Source: usb_inst/byte_counter_reg[6]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[6]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.306ns (logic 0.186ns (60.877%) route 0.120ns (39.123%))
|
|
Logic Levels: 1 (LUT6=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.122ns
|
|
Source Clock Delay (SCD): 1.600ns
|
|
Clock Pessimism Removal (CPR): 0.522ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.647 1.600 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y184 FDCE r usb_inst/byte_counter_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y184 FDCE (Prop_fdce_C_Q) 0.141 1.741 r usb_inst/byte_counter_reg[6]/Q
|
|
net (fo=3, routed) 0.120 1.861 usb_inst/byte_counter_reg_n_0_[6]
|
|
SLICE_X3Y184 LUT6 (Prop_lut6_I2_O) 0.045 1.906 r usb_inst/byte_counter[6]_i_1/O
|
|
net (fo=1, routed) 0.000 1.906 usb_inst/byte_counter[6]
|
|
SLICE_X3Y184 FDCE r usb_inst/byte_counter_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.919 2.122 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y184 FDCE r usb_inst/byte_counter_reg[6]/C
|
|
clock pessimism -0.522 1.600
|
|
SLICE_X3Y184 FDCE (Hold_fdce_C_D) 0.091 1.691 usb_inst/byte_counter_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.691
|
|
arrival time 1.906
|
|
-------------------------------------------------------------------
|
|
slack 0.215
|
|
|
|
Slack (MET) : 0.215ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[5]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.235ns (logic 0.128ns (54.556%) route 0.107ns (45.444%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y177 FDCE (Prop_fdce_C_Q) 0.128 1.722 r usb_inst/doppler_imag_hold_reg[5]/Q
|
|
net (fo=1, routed) 0.107 1.829 usb_inst/doppler_imag_hold[5]
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_imag_cap_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_imag_cap_reg[5]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X2Y178 FDCE (Hold_fdce_C_D) 0.006 1.614 usb_inst/doppler_imag_cap_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -1.614
|
|
arrival time 1.829
|
|
-------------------------------------------------------------------
|
|
slack 0.215
|
|
|
|
Slack (MET) : 0.215ns (arrival time - required time)
|
|
Source: hb_counter_reg[5]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_imag_reg_reg[5]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.325ns (logic 0.141ns (43.417%) route 0.184ns (56.583%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y176 FDRE r hb_counter_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y176 FDRE (Prop_fdre_C_Q) 0.141 1.732 r hb_counter_reg[5]/Q
|
|
net (fo=3, routed) 0.184 1.916 hb_counter_reg_n_0_[5]
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[5]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[5]/C
|
|
clock pessimism -0.484 1.629
|
|
SLICE_X0Y176 FDRE (Hold_fdre_C_D) 0.072 1.701 doppler_imag_reg_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -1.701
|
|
arrival time 1.916
|
|
-------------------------------------------------------------------
|
|
slack 0.215
|
|
|
|
Slack (MET) : 0.215ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[20]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.306ns (logic 0.141ns (46.070%) route 0.165ns (53.930%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y181 FDCE r usb_inst/range_profile_hold_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y181 FDCE (Prop_fdce_C_Q) 0.141 1.737 r usb_inst/range_profile_hold_reg[20]/Q
|
|
net (fo=1, routed) 0.165 1.902 usb_inst/range_profile_hold[20]
|
|
SLICE_X2Y181 FDCE r usb_inst/range_profile_cap_reg[20]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y181 FDCE r usb_inst/range_profile_cap_reg[20]/C
|
|
clock pessimism -0.484 1.635
|
|
SLICE_X2Y181 FDCE (Hold_fdce_C_D) 0.052 1.687 usb_inst/range_profile_cap_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time -1.687
|
|
arrival time 1.902
|
|
-------------------------------------------------------------------
|
|
slack 0.215
|
|
|
|
Slack (MET) : 0.215ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[4]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[4]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.238ns (logic 0.128ns (53.691%) route 0.110ns (46.309%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y176 FDRE (Prop_fdre_C_Q) 0.128 1.720 r range_profile_reg_reg[4]/Q
|
|
net (fo=1, routed) 0.110 1.830 usb_inst/range_profile_hold_reg[31]_0[4]
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[4]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[4]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Hold_fdce_C_D) 0.010 1.615 usb_inst/range_profile_hold_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.615
|
|
arrival time 1.830
|
|
-------------------------------------------------------------------
|
|
slack 0.215
|
|
|
|
Slack (MET) : 0.216ns (arrival time - required time)
|
|
Source: hb_counter_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.330ns (logic 0.141ns (42.682%) route 0.189ns (57.318%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.590ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 1.590 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y175 FDRE r hb_counter_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y175 FDRE (Prop_fdre_C_Q) 0.141 1.731 r hb_counter_reg[1]/Q
|
|
net (fo=3, routed) 0.189 1.920 hb_counter_reg_n_0_[1]
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[1]/C
|
|
clock pessimism -0.484 1.629
|
|
SLICE_X3Y176 FDRE (Hold_fdre_C_D) 0.075 1.704 range_profile_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.704
|
|
arrival time 1.920
|
|
-------------------------------------------------------------------
|
|
slack 0.216
|
|
|
|
Slack (MET) : 0.217ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[12]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.316ns (logic 0.141ns (44.627%) route 0.175ns (55.373%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.040ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_imag_hold_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y178 FDCE (Prop_fdce_C_Q) 0.141 1.734 r usb_inst/doppler_imag_hold_reg[12]/Q
|
|
net (fo=1, routed) 0.175 1.909 usb_inst/doppler_imag_hold[12]
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_imag_cap_reg[12]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_imag_cap_reg[12]/C
|
|
clock pessimism -0.484 1.633
|
|
SLICE_X2Y179 FDCE (Hold_fdce_C_D) 0.059 1.692 usb_inst/doppler_imag_cap_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time -1.692
|
|
arrival time 1.909
|
|
-------------------------------------------------------------------
|
|
slack 0.217
|
|
|
|
Slack (MET) : 0.217ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[2]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[2]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.306ns (logic 0.141ns (46.040%) route 0.165ns (53.960%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.592ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y176 FDRE (Prop_fdre_C_Q) 0.141 1.733 r range_profile_reg_reg[2]/Q
|
|
net (fo=1, routed) 0.165 1.898 usb_inst/range_profile_hold_reg[31]_0[2]
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[2]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[2]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Hold_fdce_C_D) 0.076 1.681 usb_inst/range_profile_hold_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.681
|
|
arrival time 1.898
|
|
-------------------------------------------------------------------
|
|
slack 0.217
|
|
|
|
Slack (MET) : 0.218ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[8]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.241ns (logic 0.128ns (53.037%) route 0.113ns (46.963%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y181 FDCE (Prop_fdce_C_Q) 0.128 1.725 r usb_inst/doppler_real_hold_reg[8]/Q
|
|
net (fo=1, routed) 0.113 1.838 usb_inst/doppler_real_hold[8]
|
|
SLICE_X2Y180 FDCE r usb_inst/doppler_real_cap_reg[8]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y180 FDCE r usb_inst/doppler_real_cap_reg[8]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X2Y180 FDCE (Hold_fdce_C_D) 0.010 1.620 usb_inst/doppler_real_cap_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.620
|
|
arrival time 1.838
|
|
-------------------------------------------------------------------
|
|
slack 0.218
|
|
|
|
Slack (MET) : 0.220ns (arrival time - required time)
|
|
Source: usb_inst/cfar_valid_sync_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_detection_cap_reg/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.311ns (logic 0.227ns (72.889%) route 0.084ns (27.111%))
|
|
Logic Levels: 1 (LUT4=1)
|
|
Clock Path Skew: 0.000ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.522ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_valid_sync_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y180 FDCE (Prop_fdce_C_Q) 0.128 1.724 r usb_inst/cfar_valid_sync_reg[1]/Q
|
|
net (fo=3, routed) 0.084 1.808 usb_inst/cfar_valid_sync[1]
|
|
SLICE_X0Y180 LUT4 (Prop_lut4_I1_O) 0.099 1.907 r usb_inst/cfar_detection_cap_i_1/O
|
|
net (fo=1, routed) 0.000 1.907 usb_inst/cfar_detection_cap_i_1_n_0
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_detection_cap_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_detection_cap_reg/C
|
|
clock pessimism -0.522 1.596
|
|
SLICE_X0Y180 FDCE (Hold_fdce_C_D) 0.091 1.687 usb_inst/cfar_detection_cap_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.687
|
|
arrival time 1.907
|
|
-------------------------------------------------------------------
|
|
slack 0.220
|
|
|
|
Slack (MET) : 0.220ns (arrival time - required time)
|
|
Source: range_profile_reg_reg[9]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[9]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.258ns (logic 0.148ns (57.257%) route 0.110ns (42.743%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.114ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y177 FDRE r range_profile_reg_reg[9]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X6Y177 FDRE (Prop_fdre_C_Q) 0.148 1.741 r range_profile_reg_reg[9]/Q
|
|
net (fo=1, routed) 0.110 1.851 usb_inst/range_profile_hold_reg[31]_0[9]
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[9]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.911 2.114 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[9]/C
|
|
clock pessimism -0.508 1.606
|
|
SLICE_X7Y177 FDCE (Hold_fdce_C_D) 0.025 1.631 usb_inst/range_profile_hold_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time -1.631
|
|
arrival time 1.851
|
|
-------------------------------------------------------------------
|
|
slack 0.220
|
|
|
|
Slack (MET) : 0.222ns (arrival time - required time)
|
|
Source: hb_counter_reg[17]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[17]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.310ns (logic 0.141ns (45.524%) route 0.169ns (54.476%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.114ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y179 FDRE r hb_counter_reg[17]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y179 FDRE (Prop_fdre_C_Q) 0.141 1.735 r hb_counter_reg[17]/Q
|
|
net (fo=3, routed) 0.169 1.904 p_1_in[1]
|
|
SLICE_X6Y177 FDRE r range_profile_reg_reg[17]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.911 2.114 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y177 FDRE r range_profile_reg_reg[17]/C
|
|
clock pessimism -0.508 1.606
|
|
SLICE_X6Y177 FDRE (Hold_fdre_C_D) 0.076 1.682 range_profile_reg_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time -1.682
|
|
arrival time 1.904
|
|
-------------------------------------------------------------------
|
|
slack 0.222
|
|
|
|
Slack (MET) : 0.222ns (arrival time - required time)
|
|
Source: usb_inst/status_req_sync_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/status_req_sync_prev_reg/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.242ns (logic 0.128ns (52.929%) route 0.114ns (47.071%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.121ns
|
|
Source Clock Delay (SCD): 1.599ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.646 1.599 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y183 FDCE r usb_inst/status_req_sync_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y183 FDCE (Prop_fdce_C_Q) 0.128 1.727 r usb_inst/status_req_sync_reg[1]/Q
|
|
net (fo=3, routed) 0.114 1.841 usb_inst/status_req_sync[1]
|
|
SLICE_X2Y183 FDCE r usb_inst/status_req_sync_prev_reg/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.918 2.121 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y183 FDCE r usb_inst/status_req_sync_prev_reg/C
|
|
clock pessimism -0.508 1.613
|
|
SLICE_X2Y183 FDCE (Hold_fdce_C_D) 0.006 1.619 usb_inst/status_req_sync_prev_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.619
|
|
arrival time 1.841
|
|
-------------------------------------------------------------------
|
|
slack 0.222
|
|
|
|
Slack (MET) : 0.222ns (arrival time - required time)
|
|
Source: usb_inst/doppler_real_hold_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.304ns (logic 0.141ns (46.338%) route 0.163ns (53.662%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.012ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y181 FDCE (Prop_fdce_C_Q) 0.141 1.738 r usb_inst/doppler_real_hold_reg[10]/Q
|
|
net (fo=1, routed) 0.163 1.901 usb_inst/doppler_real_hold[10]
|
|
SLICE_X3Y179 FDCE r usb_inst/doppler_real_cap_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y179 FDCE r usb_inst/doppler_real_cap_reg[10]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X3Y179 FDCE (Hold_fdce_C_D) 0.070 1.679 usb_inst/doppler_real_cap_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time -1.679
|
|
arrival time 1.901
|
|
-------------------------------------------------------------------
|
|
slack 0.222
|
|
|
|
Slack (MET) : 0.223ns (arrival time - required time)
|
|
Source: hb_counter_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[3]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.333ns (logic 0.141ns (42.403%) route 0.192ns (57.597%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.590ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 1.590 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y175 FDRE r hb_counter_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y175 FDRE (Prop_fdre_C_Q) 0.141 1.731 r hb_counter_reg[3]/Q
|
|
net (fo=3, routed) 0.192 1.923 hb_counter_reg_n_0_[3]
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y176 FDRE r range_profile_reg_reg[3]/C
|
|
clock pessimism -0.484 1.629
|
|
SLICE_X3Y176 FDRE (Hold_fdre_C_D) 0.071 1.700 range_profile_reg_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.700
|
|
arrival time 1.923
|
|
-------------------------------------------------------------------
|
|
slack 0.223
|
|
|
|
Slack (MET) : 0.223ns (arrival time - required time)
|
|
Source: hb_counter_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[14]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.312ns (logic 0.141ns (45.192%) route 0.171ns (54.808%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.114ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y178 FDRE r hb_counter_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y178 FDRE (Prop_fdre_C_Q) 0.141 1.734 r hb_counter_reg[14]/Q
|
|
net (fo=3, routed) 0.171 1.905 hb_counter_reg_n_0_[14]
|
|
SLICE_X6Y177 FDRE r range_profile_reg_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.911 2.114 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y177 FDRE r range_profile_reg_reg[14]/C
|
|
clock pessimism -0.508 1.606
|
|
SLICE_X6Y177 FDRE (Hold_fdre_C_D) 0.076 1.682 range_profile_reg_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time -1.682
|
|
arrival time 1.905
|
|
-------------------------------------------------------------------
|
|
slack 0.223
|
|
|
|
Slack (MET) : 0.225ns (arrival time - required time)
|
|
Source: doppler_real_reg_reg[11]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[11]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.310ns (logic 0.141ns (45.556%) route 0.169ns (54.444%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.597ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y182 FDRE r doppler_real_reg_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y182 FDRE (Prop_fdre_C_Q) 0.141 1.738 r doppler_real_reg_reg[11]/Q
|
|
net (fo=1, routed) 0.169 1.906 usb_inst/doppler_real_hold_reg[15]_0[11]
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[11]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[11]/C
|
|
clock pessimism -0.484 1.635
|
|
SLICE_X3Y181 FDCE (Hold_fdce_C_D) 0.047 1.682 usb_inst/doppler_real_hold_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -1.682
|
|
arrival time 1.906
|
|
-------------------------------------------------------------------
|
|
slack 0.225
|
|
|
|
Slack (MET) : 0.226ns (arrival time - required time)
|
|
Source: doppler_real_reg_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.286ns (logic 0.141ns (49.247%) route 0.145ns (50.753%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.013ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y179 FDRE r doppler_real_reg_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y179 FDRE (Prop_fdre_C_Q) 0.141 1.735 r doppler_real_reg_reg[1]/Q
|
|
net (fo=1, routed) 0.145 1.880 usb_inst/doppler_real_hold_reg[15]_0[1]
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[1]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X4Y178 FDCE (Hold_fdce_C_D) 0.047 1.654 usb_inst/doppler_real_hold_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.654
|
|
arrival time 1.880
|
|
-------------------------------------------------------------------
|
|
slack 0.226
|
|
|
|
Slack (MET) : 0.227ns (arrival time - required time)
|
|
Source: hb_counter_reg[6]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_imag_reg_reg[6]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.340ns (logic 0.141ns (41.511%) route 0.199ns (58.489%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.038ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.591ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.638 1.591 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y176 FDRE r hb_counter_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y176 FDRE (Prop_fdre_C_Q) 0.141 1.732 r hb_counter_reg[6]/Q
|
|
net (fo=3, routed) 0.199 1.931 hb_counter_reg_n_0_[6]
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[6]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[6]/C
|
|
clock pessimism -0.484 1.629
|
|
SLICE_X0Y176 FDRE (Hold_fdre_C_D) 0.075 1.704 doppler_imag_reg_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.704
|
|
arrival time 1.931
|
|
-------------------------------------------------------------------
|
|
slack 0.227
|
|
|
|
Slack (MET) : 0.227ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[1]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.311ns (logic 0.141ns (45.362%) route 0.170ns (54.638%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y177 FDCE (Prop_fdce_C_Q) 0.141 1.735 r usb_inst/doppler_imag_hold_reg[1]/Q
|
|
net (fo=1, routed) 0.170 1.905 usb_inst/doppler_imag_hold[1]
|
|
SLICE_X1Y178 FDCE r usb_inst/doppler_imag_cap_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y178 FDCE r usb_inst/doppler_imag_cap_reg[1]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X1Y178 FDCE (Hold_fdce_C_D) 0.070 1.678 usb_inst/doppler_imag_cap_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.678
|
|
arrival time 1.905
|
|
-------------------------------------------------------------------
|
|
slack 0.227
|
|
|
|
Slack (MET) : 0.227ns (arrival time - required time)
|
|
Source: doppler_imag_reg_reg[3]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[3]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.316ns (logic 0.141ns (44.633%) route 0.175ns (55.367%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.590ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 1.590 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y175 FDRE r doppler_imag_reg_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X4Y175 FDRE (Prop_fdre_C_Q) 0.141 1.731 r doppler_imag_reg_reg[3]/Q
|
|
net (fo=1, routed) 0.175 1.906 usb_inst/doppler_imag_hold_reg[15]_0[3]
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[3]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[3]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X4Y176 FDCE (Hold_fdce_C_D) 0.075 1.679 usb_inst/doppler_imag_hold_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.679
|
|
arrival time 1.906
|
|
-------------------------------------------------------------------
|
|
slack 0.227
|
|
|
|
Slack (MET) : 0.230ns (arrival time - required time)
|
|
Source: usb_inst/range_profile_hold_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[10]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.311ns (logic 0.141ns (45.394%) route 0.170ns (54.606%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X7Y177 FDCE (Prop_fdce_C_Q) 0.141 1.734 r usb_inst/range_profile_hold_reg[10]/Q
|
|
net (fo=1, routed) 0.170 1.904 usb_inst/range_profile_hold[10]
|
|
SLICE_X7Y176 FDCE r usb_inst/range_profile_cap_reg[10]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y176 FDCE r usb_inst/range_profile_cap_reg[10]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X7Y176 FDCE (Hold_fdce_C_D) 0.070 1.674 usb_inst/range_profile_cap_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time -1.674
|
|
arrival time 1.904
|
|
-------------------------------------------------------------------
|
|
slack 0.230
|
|
|
|
Slack (MET) : 0.230ns (arrival time - required time)
|
|
Source: hb_counter_reg[1]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_imag_reg_reg[1]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.315ns (logic 0.141ns (44.811%) route 0.174ns (55.189%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.039ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.590ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 1.590 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y175 FDRE r hb_counter_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y175 FDRE (Prop_fdre_C_Q) 0.141 1.731 r hb_counter_reg[1]/Q
|
|
net (fo=3, routed) 0.174 1.905 hb_counter_reg_n_0_[1]
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[1]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y176 FDRE r doppler_imag_reg_reg[1]/C
|
|
clock pessimism -0.484 1.629
|
|
SLICE_X0Y176 FDRE (Hold_fdre_C_D) 0.046 1.675 doppler_imag_reg_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.675
|
|
arrival time 1.905
|
|
-------------------------------------------------------------------
|
|
slack 0.230
|
|
|
|
Slack (MET) : 0.230ns (arrival time - required time)
|
|
Source: usb_inst/doppler_imag_hold_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.315ns (logic 0.141ns (44.786%) route 0.174ns (55.214%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.015ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.594ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.641 1.594 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y177 FDCE (Prop_fdce_C_Q) 0.141 1.735 r usb_inst/doppler_imag_hold_reg[0]/Q
|
|
net (fo=1, routed) 0.174 1.909 usb_inst/doppler_imag_hold[0]
|
|
SLICE_X0Y179 FDCE r usb_inst/doppler_imag_cap_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y179 FDCE r usb_inst/doppler_imag_cap_reg[0]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X0Y179 FDCE (Hold_fdce_C_D) 0.070 1.679 usb_inst/doppler_imag_cap_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.679
|
|
arrival time 1.909
|
|
-------------------------------------------------------------------
|
|
slack 0.230
|
|
|
|
Slack (MET) : 0.231ns (arrival time - required time)
|
|
Source: hb_counter_reg[23]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: range_profile_reg_reg[23]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.316ns (logic 0.141ns (44.641%) route 0.175ns (55.359%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.014ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.595ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y180 FDRE r hb_counter_reg[23]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y180 FDRE (Prop_fdre_C_Q) 0.141 1.736 r hb_counter_reg[23]/Q
|
|
net (fo=3, routed) 0.175 1.911 p_1_in[7]
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[23]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y180 FDRE r range_profile_reg_reg[23]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X7Y180 FDRE (Hold_fdre_C_D) 0.071 1.680 range_profile_reg_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time -1.680
|
|
arrival time 1.911
|
|
-------------------------------------------------------------------
|
|
slack 0.231
|
|
|
|
Slack (MET) : 0.231ns (arrival time - required time)
|
|
Source: hb_counter_reg[14]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: doppler_imag_reg_reg[14]/D
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.318ns (logic 0.141ns (44.309%) route 0.177ns (55.691%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.011ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.593ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y178 FDRE r hb_counter_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y178 FDRE (Prop_fdre_C_Q) 0.141 1.734 r hb_counter_reg[14]/Q
|
|
net (fo=3, routed) 0.177 1.911 hb_counter_reg_n_0_[14]
|
|
SLICE_X6Y176 FDRE r doppler_imag_reg_reg[14]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y176 FDRE r doppler_imag_reg_reg[14]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X6Y176 FDRE (Hold_fdre_C_D) 0.076 1.680 doppler_imag_reg_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time -1.680
|
|
arrival time 1.911
|
|
-------------------------------------------------------------------
|
|
slack 0.231
|
|
|
|
Slack (MET) : 0.231ns (arrival time - required time)
|
|
Source: usb_inst/rx_data_captured_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_value_reg[0]/D
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: ft601_clk_in
|
|
Path Type: Hold (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 0.306ns (logic 0.141ns (46.035%) route 0.165ns (53.965%))
|
|
Logic Levels: 0
|
|
Clock Path Skew: 0.016ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.596ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y180 FDCE r usb_inst/rx_data_captured_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X3Y180 FDCE (Prop_fdce_C_Q) 0.141 1.737 r usb_inst/rx_data_captured_reg[0]/Q
|
|
net (fo=1, routed) 0.165 1.902 usb_inst/rx_data_captured_reg_n_0_[0]
|
|
SLICE_X2Y182 FDCE r usb_inst/cmd_value_reg[0]/D
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y182 FDCE r usb_inst/cmd_value_reg[0]/C
|
|
clock pessimism -0.508 1.612
|
|
SLICE_X2Y182 FDCE (Hold_fdce_C_D) 0.059 1.671 usb_inst/cmd_value_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.671
|
|
arrival time 1.902
|
|
-------------------------------------------------------------------
|
|
slack 0.231
|
|
|
|
|
|
|
|
|
|
|
|
Pulse Width Checks
|
|
--------------------------------------------------------------------------------------
|
|
Clock Name: ft601_clk_in
|
|
Waveform(ns): { 0.000 5.000 }
|
|
Period(ns): 10.000
|
|
Sources: { ft601_clk_in }
|
|
|
|
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
|
|
Min Period n/a BUFG/I n/a 1.592 10.000 8.408 BUFGCTRL_X0Y16 ft601_clk_in_IBUF_BUFG_inst/I
|
|
Min Period n/a FDPE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y218 usb_inst/ft601_be_reg[0]/C
|
|
Min Period n/a FDPE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y217 usb_inst/ft601_be_reg[1]/C
|
|
Min Period n/a FDPE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y239 usb_inst/ft601_be_reg[2]/C
|
|
Min Period n/a FDPE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y240 usb_inst/ft601_be_reg[3]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y179 usb_inst/ft601_data_out_reg[0]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y188 usb_inst/ft601_data_out_reg[10]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y157 usb_inst/ft601_data_out_reg[11]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y155 usb_inst/ft601_data_out_reg[12]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y190 usb_inst/ft601_data_out_reg[13]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y156 usb_inst/ft601_data_out_reg[14]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y189 usb_inst/ft601_data_out_reg[15]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y197 usb_inst/ft601_data_out_reg[16]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y196 usb_inst/ft601_data_out_reg[17]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y198 usb_inst/ft601_data_out_reg[18]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y195 usb_inst/ft601_data_out_reg[19]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y164 usb_inst/ft601_data_out_reg[1]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y191 usb_inst/ft601_data_out_reg[20]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y167 usb_inst/ft601_data_out_reg[21]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y192 usb_inst/ft601_data_out_reg[22]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y168 usb_inst/ft601_data_out_reg[23]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y193 usb_inst/ft601_data_out_reg[24]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y194 usb_inst/ft601_data_out_reg[25]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y166 usb_inst/ft601_data_out_reg[26]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y165 usb_inst/ft601_data_out_reg[27]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y161 usb_inst/ft601_data_out_reg[28]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y162 usb_inst/ft601_data_out_reg[29]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y180 usb_inst/ft601_data_out_reg[2]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y175 usb_inst/ft601_data_out_reg[30]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y176 usb_inst/ft601_data_out_reg[31]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y163 usb_inst/ft601_data_out_reg[3]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y160 usb_inst/ft601_data_out_reg[4]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y170 usb_inst/ft601_data_out_reg[5]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y159 usb_inst/ft601_data_out_reg[6]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y169 usb_inst/ft601_data_out_reg[7]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y187 usb_inst/ft601_data_out_reg[8]/C
|
|
Min Period n/a FDCE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y158 usb_inst/ft601_data_out_reg[9]/C
|
|
Min Period n/a FDPE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y225 usb_inst/ft601_oe_n_reg/C
|
|
Min Period n/a FDPE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y226 usb_inst/ft601_rd_n_reg/C
|
|
Min Period n/a FDPE/C n/a 1.474 10.000 8.526 OLOGIC_X0Y242 usb_inst/ft601_wr_n_reg/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X1Y180 cfar_detection_reg_reg/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X1Y181 cfar_valid_reg_reg/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y175 doppler_imag_reg_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y175 doppler_imag_reg_reg[10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y175 doppler_imag_reg_reg[11]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y179 doppler_imag_reg_reg[12]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X6Y176 doppler_imag_reg_reg[13]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X6Y176 doppler_imag_reg_reg[14]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X6Y176 doppler_imag_reg_reg[15]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X0Y176 doppler_imag_reg_reg[1]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X0Y176 doppler_imag_reg_reg[2]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y175 doppler_imag_reg_reg[3]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X0Y176 doppler_imag_reg_reg[4]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X0Y176 doppler_imag_reg_reg[5]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X0Y176 doppler_imag_reg_reg[6]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X0Y176 doppler_imag_reg_reg[7]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X6Y176 doppler_imag_reg_reg[8]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X6Y176 doppler_imag_reg_reg[9]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y179 doppler_real_reg_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y182 doppler_real_reg_reg[10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y182 doppler_real_reg_reg[11]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y182 doppler_real_reg_reg[12]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y182 doppler_real_reg_reg[13]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y182 doppler_real_reg_reg[14]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y182 doppler_real_reg_reg[15]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y179 doppler_real_reg_reg[1]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X6Y176 doppler_real_reg_reg[2]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y179 doppler_real_reg_reg[3]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y179 doppler_real_reg_reg[4]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y179 doppler_real_reg_reg[5]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y179 doppler_real_reg_reg[6]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y179 doppler_real_reg_reg[7]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y183 doppler_real_reg_reg[8]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X4Y182 doppler_real_reg_reg[9]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X1Y181 doppler_valid_reg_reg/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y175 hb_counter_reg[0]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y177 hb_counter_reg[10]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y177 hb_counter_reg[11]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y178 hb_counter_reg[12]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y178 hb_counter_reg[13]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y178 hb_counter_reg[14]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y178 hb_counter_reg[15]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y179 hb_counter_reg[16]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y179 hb_counter_reg[17]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y179 hb_counter_reg[18]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y179 hb_counter_reg[19]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y175 hb_counter_reg[1]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y180 hb_counter_reg[20]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y180 hb_counter_reg[21]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y180 hb_counter_reg[22]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y180 hb_counter_reg[23]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y181 hb_counter_reg[24]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y181 hb_counter_reg[25]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y181 hb_counter_reg[26]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y181 hb_counter_reg[27]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y182 hb_counter_reg[28]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y182 hb_counter_reg[29]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y175 hb_counter_reg[2]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y182 hb_counter_reg[30]/C
|
|
Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X5Y182 hb_counter_reg[31]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y180 cfar_detection_reg_reg/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y180 cfar_detection_reg_reg/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y181 cfar_valid_reg_reg/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y181 cfar_valid_reg_reg/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[0]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[10]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[10]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[11]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[11]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_imag_reg_reg[12]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_imag_reg_reg[12]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[13]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[13]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[14]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[14]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[15]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[15]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[1]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[1]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[2]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[2]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[3]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[3]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[4]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[4]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[5]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[5]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[6]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[6]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[7]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[7]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[8]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[8]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[9]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[9]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[0]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[10]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[10]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[11]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[11]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[12]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[12]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[13]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[13]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[14]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[14]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[15]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[15]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[1]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[1]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_real_reg_reg[2]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_real_reg_reg[2]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[3]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[3]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[4]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[4]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[5]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[5]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[6]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[6]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[7]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[7]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y183 doppler_real_reg_reg[8]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y183 doppler_real_reg_reg[8]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[9]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[9]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y181 doppler_valid_reg_reg/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y181 doppler_valid_reg_reg/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y175 hb_counter_reg[0]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y175 hb_counter_reg[0]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y177 hb_counter_reg[10]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y177 hb_counter_reg[10]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y177 hb_counter_reg[11]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y177 hb_counter_reg[11]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[12]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[12]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[13]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[13]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[14]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[14]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[15]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[15]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[16]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[16]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[17]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[17]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[18]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[18]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[19]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[19]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y175 hb_counter_reg[1]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y175 hb_counter_reg[1]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[20]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[20]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[21]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[21]/C
|
|
Low Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[22]/C
|
|
Low Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[22]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y180 cfar_detection_reg_reg/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y180 cfar_detection_reg_reg/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y181 cfar_valid_reg_reg/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y181 cfar_valid_reg_reg/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[0]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[10]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[10]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[11]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[11]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_imag_reg_reg[12]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_imag_reg_reg[12]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[13]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[13]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[14]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[14]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[15]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[15]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[1]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[2]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[2]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[3]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y175 doppler_imag_reg_reg[3]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[4]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[4]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[5]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[5]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[6]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[6]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[7]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X0Y176 doppler_imag_reg_reg[7]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[8]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[8]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[9]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_imag_reg_reg[9]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[0]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[10]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[10]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[11]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[11]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[12]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[12]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[13]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[13]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[14]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[14]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[15]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[15]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[1]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_real_reg_reg[2]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X6Y176 doppler_real_reg_reg[2]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[3]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[3]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[4]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[4]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[5]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[5]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[6]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[6]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[7]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y179 doppler_real_reg_reg[7]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y183 doppler_real_reg_reg[8]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y183 doppler_real_reg_reg[8]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[9]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X4Y182 doppler_real_reg_reg[9]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y181 doppler_valid_reg_reg/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X1Y181 doppler_valid_reg_reg/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y175 hb_counter_reg[0]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y175 hb_counter_reg[0]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y177 hb_counter_reg[10]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y177 hb_counter_reg[10]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y177 hb_counter_reg[11]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y177 hb_counter_reg[11]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[12]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[12]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[13]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[13]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[14]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[14]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[15]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y178 hb_counter_reg[15]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[16]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[16]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[17]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[17]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[18]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[18]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[19]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y179 hb_counter_reg[19]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y175 hb_counter_reg[1]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y175 hb_counter_reg[1]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[20]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[20]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[21]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[21]/C
|
|
High Pulse Width Slow FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[22]/C
|
|
High Pulse Width Fast FDRE/C n/a 0.500 5.000 4.500 SLICE_X5Y180 hb_counter_reg[22]/C
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **async_default**
|
|
From Clock: ft601_clk_in
|
|
To Clock: ft601_clk_in
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 2.305ns, Total Violation 0.000ns
|
|
Hold : 0 Failing Endpoints, Worst Slack 0.978ns, Total Violation 0.000ns
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 2.305ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_wr_n_reg/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 7.437ns (logic 0.484ns (6.508%) route 6.953ns (93.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.738ns = ( 14.738 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 5.962 12.295 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y242 FDPE f usb_inst/ft601_wr_n_reg/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.593 14.738 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y242 FDPE r usb_inst/ft601_wr_n_reg/C
|
|
clock pessimism 0.168 14.907
|
|
clock uncertainty -0.061 14.845
|
|
OLOGIC_X0Y242 FDPE (Recov_fdpe_C_PRE) -0.245 14.600 usb_inst/ft601_wr_n_reg
|
|
-------------------------------------------------------------------
|
|
required time 14.600
|
|
arrival time -12.295
|
|
-------------------------------------------------------------------
|
|
slack 2.305
|
|
|
|
Slack (MET) : 2.524ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[3]/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 7.218ns (logic 0.484ns (6.706%) route 6.734ns (93.294%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.738ns = ( 14.738 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 5.742 12.076 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y240 FDPE f usb_inst/ft601_be_reg[3]/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.593 14.738 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y240 FDPE r usb_inst/ft601_be_reg[3]/C
|
|
clock pessimism 0.168 14.907
|
|
clock uncertainty -0.061 14.845
|
|
OLOGIC_X0Y240 FDPE (Recov_fdpe_C_PRE) -0.245 14.600 usb_inst/ft601_be_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.600
|
|
arrival time -12.076
|
|
-------------------------------------------------------------------
|
|
slack 2.524
|
|
|
|
Slack (MET) : 2.642ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[2]/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 7.101ns (logic 0.484ns (6.816%) route 6.617ns (93.184%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.048ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.738ns = ( 14.738 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 5.625 11.959 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y239 FDPE f usb_inst/ft601_be_reg[2]/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.593 14.738 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y239 FDPE r usb_inst/ft601_be_reg[2]/C
|
|
clock pessimism 0.168 14.907
|
|
clock uncertainty -0.061 14.845
|
|
OLOGIC_X0Y239 FDPE (Recov_fdpe_C_PRE) -0.245 14.600 usb_inst/ft601_be_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 14.600
|
|
arrival time -11.959
|
|
-------------------------------------------------------------------
|
|
slack 2.642
|
|
|
|
Slack (MET) : 3.085ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_rd_n_reg/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.645ns (logic 0.484ns (7.283%) route 6.161ns (92.717%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.726ns = ( 14.726 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 5.170 11.504 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y226 FDPE f usb_inst/ft601_rd_n_reg/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.581 14.726 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y226 FDPE r usb_inst/ft601_rd_n_reg/C
|
|
clock pessimism 0.168 14.895
|
|
clock uncertainty -0.061 14.833
|
|
OLOGIC_X0Y226 FDPE (Recov_fdpe_C_PRE) -0.245 14.588 usb_inst/ft601_rd_n_reg
|
|
-------------------------------------------------------------------
|
|
required time 14.588
|
|
arrival time -11.504
|
|
-------------------------------------------------------------------
|
|
slack 3.085
|
|
|
|
Slack (MET) : 3.193ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_oe_n_reg/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.537ns (logic 0.484ns (7.404%) route 6.053ns (92.596%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.036ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.726ns = ( 14.726 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 5.062 11.395 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y225 FDPE f usb_inst/ft601_oe_n_reg/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.581 14.726 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y225 FDPE r usb_inst/ft601_oe_n_reg/C
|
|
clock pessimism 0.168 14.895
|
|
clock uncertainty -0.061 14.833
|
|
OLOGIC_X0Y225 FDPE (Recov_fdpe_C_PRE) -0.245 14.588 usb_inst/ft601_oe_n_reg
|
|
-------------------------------------------------------------------
|
|
required time 14.588
|
|
arrival time -11.395
|
|
-------------------------------------------------------------------
|
|
slack 3.193
|
|
|
|
Slack (MET) : 3.432ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[0]/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.303ns (logic 0.484ns (7.678%) route 5.819ns (92.322%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.041ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.731ns = ( 14.731 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 4.828 11.162 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y218 FDPE f usb_inst/ft601_be_reg[0]/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.586 14.731 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y218 FDPE r usb_inst/ft601_be_reg[0]/C
|
|
clock pessimism 0.168 14.900
|
|
clock uncertainty -0.061 14.838
|
|
OLOGIC_X0Y218 FDPE (Recov_fdpe_C_PRE) -0.245 14.593 usb_inst/ft601_be_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 14.593
|
|
arrival time -11.162
|
|
-------------------------------------------------------------------
|
|
slack 3.432
|
|
|
|
Slack (MET) : 3.540ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_be_reg[1]/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 6.195ns (logic 0.484ns (7.813%) route 5.711ns (92.187%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.041ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.731ns = ( 14.731 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 4.720 11.053 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y217 FDPE f usb_inst/ft601_be_reg[1]/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.586 14.731 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y217 FDPE r usb_inst/ft601_be_reg[1]/C
|
|
clock pessimism 0.168 14.900
|
|
clock uncertainty -0.061 14.838
|
|
OLOGIC_X0Y217 FDPE (Recov_fdpe_C_PRE) -0.245 14.593 usb_inst/ft601_be_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.593
|
|
arrival time -11.053
|
|
-------------------------------------------------------------------
|
|
slack 3.540
|
|
|
|
Slack (MET) : 3.839ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[2]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.835ns (logic 0.484ns (8.295%) route 5.351ns (91.705%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.067ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.756ns = ( 14.756 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 4.359 10.693 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y209 FDCE f usb_inst/FSM_onehot_read_state_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.611 14.756 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[2]/C
|
|
clock pessimism 0.168 14.925
|
|
clock uncertainty -0.061 14.864
|
|
SLICE_X0Y209 FDCE (Recov_fdce_C_CLR) -0.331 14.533 usb_inst/FSM_onehot_read_state_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 14.533
|
|
arrival time -10.693
|
|
-------------------------------------------------------------------
|
|
slack 3.839
|
|
|
|
Slack (MET) : 3.839ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[3]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.835ns (logic 0.484ns (8.295%) route 5.351ns (91.705%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.067ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.756ns = ( 14.756 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 4.359 10.693 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y209 FDCE f usb_inst/FSM_onehot_read_state_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.611 14.756 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[3]/C
|
|
clock pessimism 0.168 14.925
|
|
clock uncertainty -0.061 14.864
|
|
SLICE_X0Y209 FDCE (Recov_fdce_C_CLR) -0.331 14.533 usb_inst/FSM_onehot_read_state_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.533
|
|
arrival time -10.693
|
|
-------------------------------------------------------------------
|
|
slack 3.839
|
|
|
|
Slack (MET) : 3.839ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[4]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.835ns (logic 0.484ns (8.295%) route 5.351ns (91.705%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.067ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.756ns = ( 14.756 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 4.359 10.693 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y209 FDCE f usb_inst/FSM_onehot_read_state_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.611 14.756 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[4]/C
|
|
clock pessimism 0.168 14.925
|
|
clock uncertainty -0.061 14.864
|
|
SLICE_X0Y209 FDCE (Recov_fdce_C_CLR) -0.331 14.533 usb_inst/FSM_onehot_read_state_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 14.533
|
|
arrival time -10.693
|
|
-------------------------------------------------------------------
|
|
slack 3.839
|
|
|
|
Slack (MET) : 3.843ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[1]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.831ns (logic 0.484ns (8.300%) route 5.347ns (91.700%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.067ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.756ns = ( 14.756 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 4.356 10.690 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y209 FDCE f usb_inst/FSM_onehot_read_state_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.611 14.756 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y209 FDCE r usb_inst/FSM_onehot_read_state_reg[1]/C
|
|
clock pessimism 0.168 14.925
|
|
clock uncertainty -0.061 14.864
|
|
SLICE_X1Y209 FDCE (Recov_fdce_C_CLR) -0.331 14.533 usb_inst/FSM_onehot_read_state_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.533
|
|
arrival time -10.690
|
|
-------------------------------------------------------------------
|
|
slack 3.843
|
|
|
|
Slack (MET) : 3.878ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/FSM_onehot_read_state_reg[0]/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.835ns (logic 0.484ns (8.295%) route 5.351ns (91.705%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.067ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.756ns = ( 14.756 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.168ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 4.359 10.693 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y209 FDPE f usb_inst/FSM_onehot_read_state_reg[0]/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.611 14.756 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y209 FDPE r usb_inst/FSM_onehot_read_state_reg[0]/C
|
|
clock pessimism 0.168 14.925
|
|
clock uncertainty -0.061 14.864
|
|
SLICE_X0Y209 FDPE (Recov_fdpe_C_PRE) -0.292 14.572 usb_inst/FSM_onehot_read_state_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 14.572
|
|
arrival time -10.693
|
|
-------------------------------------------------------------------
|
|
slack 3.878
|
|
|
|
Slack (MET) : 4.460ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[18]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.178ns (logic 0.484ns (9.348%) route 4.694ns (90.652%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.056ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.702 10.036 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y198 FDCE f usb_inst/ft601_data_out_reg[18]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.429 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y198 FDCE r usb_inst/ft601_data_out_reg[18]/C
|
|
clock pessimism 0.228 14.802
|
|
clock uncertainty -0.061 14.741
|
|
OLOGIC_X0Y198 FDCE (Recov_fdce_C_CLR) -0.245 14.496 usb_inst/ft601_data_out_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 14.496
|
|
arrival time -10.036
|
|
-------------------------------------------------------------------
|
|
slack 4.460
|
|
|
|
Slack (MET) : 4.488ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_oe_reg/PRE
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.132ns (logic 0.484ns (9.430%) route 4.648ns (90.570%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.026ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.591ns = ( 14.591 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.242ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.657 9.991 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y195 FDPE f usb_inst/ft601_data_oe_reg/PRE
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.445 14.591 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y195 FDPE r usb_inst/ft601_data_oe_reg/C
|
|
clock pessimism 0.242 14.832
|
|
clock uncertainty -0.061 14.771
|
|
SLICE_X0Y195 FDPE (Recov_fdpe_C_PRE) -0.292 14.479 usb_inst/ft601_data_oe_reg
|
|
-------------------------------------------------------------------
|
|
required time 14.479
|
|
arrival time -9.991
|
|
-------------------------------------------------------------------
|
|
slack 4.488
|
|
|
|
Slack (MET) : 4.577ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[16]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 5.060ns (logic 0.484ns (9.565%) route 4.576ns (90.435%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.056ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.585 9.919 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y197 FDCE f usb_inst/ft601_data_out_reg[16]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.429 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y197 FDCE r usb_inst/ft601_data_out_reg[16]/C
|
|
clock pessimism 0.228 14.802
|
|
clock uncertainty -0.061 14.741
|
|
OLOGIC_X0Y197 FDCE (Recov_fdce_C_CLR) -0.245 14.496 usb_inst/ft601_data_out_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 14.496
|
|
arrival time -9.919
|
|
-------------------------------------------------------------------
|
|
slack 4.577
|
|
|
|
Slack (MET) : 4.695ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[17]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.943ns (logic 0.484ns (9.792%) route 4.459ns (90.208%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.056ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.467 9.801 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y196 FDCE f usb_inst/ft601_data_out_reg[17]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.429 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y196 FDCE r usb_inst/ft601_data_out_reg[17]/C
|
|
clock pessimism 0.228 14.802
|
|
clock uncertainty -0.061 14.741
|
|
OLOGIC_X0Y196 FDCE (Recov_fdce_C_CLR) -0.245 14.496 usb_inst/ft601_data_out_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 14.496
|
|
arrival time -9.801
|
|
-------------------------------------------------------------------
|
|
slack 4.695
|
|
|
|
Slack (MET) : 4.812ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[19]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.826ns (logic 0.484ns (10.030%) route 4.342ns (89.970%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.056ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.350 9.684 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y195 FDCE f usb_inst/ft601_data_out_reg[19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.429 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y195 FDCE r usb_inst/ft601_data_out_reg[19]/C
|
|
clock pessimism 0.228 14.802
|
|
clock uncertainty -0.061 14.741
|
|
OLOGIC_X0Y195 FDCE (Recov_fdce_C_CLR) -0.245 14.496 usb_inst/ft601_data_out_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 14.496
|
|
arrival time -9.684
|
|
-------------------------------------------------------------------
|
|
slack 4.812
|
|
|
|
Slack (MET) : 4.936ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[25]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.700ns (logic 0.484ns (10.299%) route 4.216ns (89.701%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.224 9.558 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y194 FDCE f usb_inst/ft601_data_out_reg[25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y194 FDCE r usb_inst/ft601_data_out_reg[25]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y194 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.558
|
|
-------------------------------------------------------------------
|
|
slack 4.936
|
|
|
|
Slack (MET) : 5.053ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[24]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.582ns (logic 0.484ns (10.562%) route 4.098ns (89.438%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.107 9.441 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y193 FDCE f usb_inst/ft601_data_out_reg[24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y193 FDCE r usb_inst/ft601_data_out_reg[24]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y193 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.441
|
|
-------------------------------------------------------------------
|
|
slack 5.053
|
|
|
|
Slack (MET) : 5.085ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[14]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.550ns (logic 0.484ns (10.636%) route 4.066ns (89.364%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.075 9.409 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y156 FDCE f usb_inst/ft601_data_out_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y156 FDCE r usb_inst/ft601_data_out_reg[14]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y156 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.409
|
|
-------------------------------------------------------------------
|
|
slack 5.085
|
|
|
|
Slack (MET) : 5.092ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[12]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.543ns (logic 0.484ns (10.653%) route 4.059ns (89.347%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 3.068 9.402 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y155 FDCE f usb_inst/ft601_data_out_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y155 FDCE r usb_inst/ft601_data_out_reg[12]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y155 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.402
|
|
-------------------------------------------------------------------
|
|
slack 5.092
|
|
|
|
Slack (MET) : 5.174ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[22]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.461ns (logic 0.484ns (10.849%) route 3.977ns (89.151%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.986 9.319 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y192 FDCE f usb_inst/ft601_data_out_reg[22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y192 FDCE r usb_inst/ft601_data_out_reg[22]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y192 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.319
|
|
-------------------------------------------------------------------
|
|
slack 5.174
|
|
|
|
Slack (MET) : 5.211ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[11]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.424ns (logic 0.484ns (10.940%) route 3.940ns (89.060%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.949 9.282 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y157 FDCE f usb_inst/ft601_data_out_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y157 FDCE r usb_inst/ft601_data_out_reg[11]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y157 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.282
|
|
-------------------------------------------------------------------
|
|
slack 5.211
|
|
|
|
Slack (MET) : 5.404ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[20]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.231ns (logic 0.484ns (11.439%) route 3.747ns (88.561%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.755 9.089 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y191 FDCE f usb_inst/ft601_data_out_reg[20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y191 FDCE r usb_inst/ft601_data_out_reg[20]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y191 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.089
|
|
-------------------------------------------------------------------
|
|
slack 5.404
|
|
|
|
Slack (MET) : 5.433ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[9]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.202ns (logic 0.484ns (11.518%) route 3.718ns (88.482%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.727 9.060 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y158 FDCE f usb_inst/ft601_data_out_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y158 FDCE r usb_inst/ft601_data_out_reg[9]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y158 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.060
|
|
-------------------------------------------------------------------
|
|
slack 5.433
|
|
|
|
Slack (MET) : 5.466ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[6]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.170ns (logic 0.484ns (11.608%) route 3.686ns (88.392%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.694 9.028 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y159 FDCE f usb_inst/ft601_data_out_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y159 FDCE r usb_inst/ft601_data_out_reg[6]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y159 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -9.028
|
|
-------------------------------------------------------------------
|
|
slack 5.466
|
|
|
|
Slack (MET) : 5.522ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[13]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.114ns (logic 0.484ns (11.765%) route 3.630ns (88.235%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.638 8.972 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y190 FDCE f usb_inst/ft601_data_out_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y190 FDCE r usb_inst/ft601_data_out_reg[13]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y190 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -8.972
|
|
-------------------------------------------------------------------
|
|
slack 5.522
|
|
|
|
Slack (MET) : 5.570ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[4]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.066ns (logic 0.484ns (11.904%) route 3.582ns (88.096%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.590 8.924 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y160 FDCE f usb_inst/ft601_data_out_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y160 FDCE r usb_inst/ft601_data_out_reg[4]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y160 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -8.924
|
|
-------------------------------------------------------------------
|
|
slack 5.570
|
|
|
|
Slack (MET) : 5.600ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[28]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 4.033ns (logic 0.484ns (12.000%) route 3.549ns (88.000%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.558 8.892 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y161 FDCE f usb_inst/ft601_data_out_reg[28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y161 FDCE r usb_inst/ft601_data_out_reg[28]/C
|
|
clock pessimism 0.228 14.798
|
|
clock uncertainty -0.061 14.737
|
|
OLOGIC_X0Y161 FDCE (Recov_fdce_C_CLR) -0.245 14.492 usb_inst/ft601_data_out_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 14.492
|
|
arrival time -8.892
|
|
-------------------------------------------------------------------
|
|
slack 5.600
|
|
|
|
Slack (MET) : 5.639ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[15]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.996ns (logic 0.484ns (12.111%) route 3.512ns (87.889%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.058ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.572ns = ( 14.572 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.521 8.855 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y189 FDCE f usb_inst/ft601_data_out_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.427 14.572 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y189 FDCE r usb_inst/ft601_data_out_reg[15]/C
|
|
clock pessimism 0.228 14.800
|
|
clock uncertainty -0.061 14.739
|
|
OLOGIC_X0Y189 FDCE (Recov_fdce_C_CLR) -0.245 14.494 usb_inst/ft601_data_out_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 14.494
|
|
arrival time -8.855
|
|
-------------------------------------------------------------------
|
|
slack 5.639
|
|
|
|
Slack (MET) : 5.754ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[10]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.879ns (logic 0.484ns (12.477%) route 3.395ns (87.523%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.404 8.738 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y188 FDCE f usb_inst/ft601_data_out_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y188 FDCE r usb_inst/ft601_data_out_reg[10]/C
|
|
clock pessimism 0.228 14.798
|
|
clock uncertainty -0.061 14.737
|
|
OLOGIC_X0Y188 FDCE (Recov_fdce_C_CLR) -0.245 14.492 usb_inst/ft601_data_out_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 14.492
|
|
arrival time -8.738
|
|
-------------------------------------------------------------------
|
|
slack 5.754
|
|
|
|
Slack (MET) : 5.854ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[29]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.780ns (logic 0.484ns (12.805%) route 3.296ns (87.195%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.304 8.638 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y162 FDCE f usb_inst/ft601_data_out_reg[29]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y162 FDCE r usb_inst/ft601_data_out_reg[29]/C
|
|
clock pessimism 0.228 14.798
|
|
clock uncertainty -0.061 14.737
|
|
OLOGIC_X0Y162 FDCE (Recov_fdce_C_CLR) -0.245 14.492 usb_inst/ft601_data_out_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 14.492
|
|
arrival time -8.638
|
|
-------------------------------------------------------------------
|
|
slack 5.854
|
|
|
|
Slack (MET) : 5.872ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[8]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.762ns (logic 0.484ns (12.866%) route 3.278ns (87.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.060ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.570ns = ( 14.570 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.286 8.620 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y187 FDCE f usb_inst/ft601_data_out_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.425 14.570 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y187 FDCE r usb_inst/ft601_data_out_reg[8]/C
|
|
clock pessimism 0.228 14.798
|
|
clock uncertainty -0.061 14.737
|
|
OLOGIC_X0Y187 FDCE (Recov_fdce_C_CLR) -0.245 14.492 usb_inst/ft601_data_out_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 14.492
|
|
arrival time -8.620
|
|
-------------------------------------------------------------------
|
|
slack 5.872
|
|
|
|
Slack (MET) : 5.919ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[13]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.634ns (logic 0.484ns (13.319%) route 3.150ns (86.681%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.159 8.492 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y177 FDCE f usb_inst/doppler_imag_cap_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y177 FDCE r usb_inst/doppler_imag_cap_reg[13]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_imag_cap_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.492
|
|
-------------------------------------------------------------------
|
|
slack 5.919
|
|
|
|
Slack (MET) : 5.919ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[14]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.634ns (logic 0.484ns (13.319%) route 3.150ns (86.681%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.159 8.492 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y177 FDCE f usb_inst/doppler_imag_cap_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y177 FDCE r usb_inst/doppler_imag_cap_reg[14]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_imag_cap_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.492
|
|
-------------------------------------------------------------------
|
|
slack 5.919
|
|
|
|
Slack (MET) : 5.919ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[2]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.634ns (logic 0.484ns (13.319%) route 3.150ns (86.681%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.159 8.492 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y177 FDCE f usb_inst/doppler_real_cap_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y177 FDCE r usb_inst/doppler_real_cap_reg[2]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_cap_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.492
|
|
-------------------------------------------------------------------
|
|
slack 5.919
|
|
|
|
Slack (MET) : 5.919ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[6]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.634ns (logic 0.484ns (13.319%) route 3.150ns (86.681%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.159 8.492 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y177 FDCE f usb_inst/doppler_real_cap_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y177 FDCE r usb_inst/doppler_real_cap_reg[6]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_cap_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.492
|
|
-------------------------------------------------------------------
|
|
slack 5.919
|
|
|
|
Slack (MET) : 5.952ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[3]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.680ns (logic 0.484ns (13.153%) route 3.196ns (86.847%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.062ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.204 8.538 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y163 FDCE f usb_inst/ft601_data_out_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y163 FDCE r usb_inst/ft601_data_out_reg[3]/C
|
|
clock pessimism 0.228 14.796
|
|
clock uncertainty -0.061 14.735
|
|
OLOGIC_X0Y163 FDCE (Recov_fdce_C_CLR) -0.245 14.490 usb_inst/ft601_data_out_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.490
|
|
arrival time -8.538
|
|
-------------------------------------------------------------------
|
|
slack 5.952
|
|
|
|
Slack (MET) : 6.078ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[1]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.553ns (logic 0.484ns (13.622%) route 3.069ns (86.378%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.062ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 2.078 8.411 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y164 FDCE f usb_inst/ft601_data_out_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y164 FDCE r usb_inst/ft601_data_out_reg[1]/C
|
|
clock pessimism 0.228 14.796
|
|
clock uncertainty -0.061 14.735
|
|
OLOGIC_X0Y164 FDCE (Recov_fdce_C_CLR) -0.245 14.490 usb_inst/ft601_data_out_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.490
|
|
arrival time -8.411
|
|
-------------------------------------------------------------------
|
|
slack 6.078
|
|
|
|
Slack (MET) : 6.143ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[14]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.410ns (logic 0.484ns (14.193%) route 2.926ns (85.807%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.935 8.268 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y178 FDCE f usb_inst/range_profile_cap_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y178 FDCE r usb_inst/range_profile_cap_reg[14]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_cap_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.268
|
|
-------------------------------------------------------------------
|
|
slack 6.143
|
|
|
|
Slack (MET) : 6.143ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[17]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.410ns (logic 0.484ns (14.193%) route 2.926ns (85.807%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.935 8.268 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y178 FDCE f usb_inst/range_profile_cap_reg[17]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y178 FDCE r usb_inst/range_profile_cap_reg[17]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_cap_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.268
|
|
-------------------------------------------------------------------
|
|
slack 6.143
|
|
|
|
Slack (MET) : 6.143ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[23]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.410ns (logic 0.484ns (14.193%) route 2.926ns (85.807%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.935 8.268 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y178 FDCE f usb_inst/range_profile_cap_reg[23]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y178 FDCE r usb_inst/range_profile_cap_reg[23]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_cap_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.268
|
|
-------------------------------------------------------------------
|
|
slack 6.143
|
|
|
|
Slack (MET) : 6.143ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[9]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.410ns (logic 0.484ns (14.193%) route 2.926ns (85.807%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.935 8.268 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y178 FDCE f usb_inst/range_profile_cap_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y178 FDCE r usb_inst/range_profile_cap_reg[9]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_cap_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.268
|
|
-------------------------------------------------------------------
|
|
slack 6.143
|
|
|
|
Slack (MET) : 6.196ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[27]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.435ns (logic 0.484ns (14.089%) route 2.951ns (85.911%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.062ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.960 8.294 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y165 FDCE f usb_inst/ft601_data_out_reg[27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y165 FDCE r usb_inst/ft601_data_out_reg[27]/C
|
|
clock pessimism 0.228 14.796
|
|
clock uncertainty -0.061 14.735
|
|
OLOGIC_X0Y165 FDCE (Recov_fdce_C_CLR) -0.245 14.490 usb_inst/ft601_data_out_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 14.490
|
|
arrival time -8.294
|
|
-------------------------------------------------------------------
|
|
slack 6.196
|
|
|
|
Slack (MET) : 6.216ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[13]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.410ns (logic 0.484ns (14.193%) route 2.926ns (85.807%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.935 8.268 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y178 FDCE f usb_inst/range_profile_cap_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y178 FDCE r usb_inst/range_profile_cap_reg[13]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X6Y178 FDCE (Recov_fdce_C_CLR) -0.258 14.484 usb_inst/range_profile_cap_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 14.484
|
|
arrival time -8.268
|
|
-------------------------------------------------------------------
|
|
slack 6.216
|
|
|
|
Slack (MET) : 6.216ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[21]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.410ns (logic 0.484ns (14.193%) route 2.926ns (85.807%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.935 8.268 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y178 FDCE f usb_inst/range_profile_cap_reg[21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y178 FDCE r usb_inst/range_profile_cap_reg[21]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X6Y178 FDCE (Recov_fdce_C_CLR) -0.258 14.484 usb_inst/range_profile_cap_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 14.484
|
|
arrival time -8.268
|
|
-------------------------------------------------------------------
|
|
slack 6.216
|
|
|
|
Slack (MET) : 6.216ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[29]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.410ns (logic 0.484ns (14.193%) route 2.926ns (85.807%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.935 8.268 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y178 FDCE f usb_inst/range_profile_cap_reg[29]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y178 FDCE r usb_inst/range_profile_cap_reg[29]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X6Y178 FDCE (Recov_fdce_C_CLR) -0.258 14.484 usb_inst/range_profile_cap_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 14.484
|
|
arrival time -8.268
|
|
-------------------------------------------------------------------
|
|
slack 6.216
|
|
|
|
Slack (MET) : 6.216ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[30]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.410ns (logic 0.484ns (14.193%) route 2.926ns (85.807%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.935 8.268 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y178 FDCE f usb_inst/range_profile_cap_reg[30]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y178 FDCE r usb_inst/range_profile_cap_reg[30]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X6Y178 FDCE (Recov_fdce_C_CLR) -0.258 14.484 usb_inst/range_profile_cap_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 14.484
|
|
arrival time -8.268
|
|
-------------------------------------------------------------------
|
|
slack 6.216
|
|
|
|
Slack (MET) : 6.245ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[27]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.350ns (logic 0.484ns (14.450%) route 2.866ns (85.550%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.579ns = ( 14.579 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.874 8.208 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y180 FDCE f usb_inst/range_profile_hold_reg[27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.433 14.579 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[27]/C
|
|
clock pessimism 0.228 14.806
|
|
clock uncertainty -0.061 14.745
|
|
SLICE_X6Y180 FDCE (Recov_fdce_C_CLR) -0.292 14.453 usb_inst/range_profile_hold_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time 14.453
|
|
arrival time -8.208
|
|
-------------------------------------------------------------------
|
|
slack 6.245
|
|
|
|
Slack (MET) : 6.245ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[29]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.350ns (logic 0.484ns (14.450%) route 2.866ns (85.550%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.579ns = ( 14.579 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.874 8.208 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y180 FDCE f usb_inst/range_profile_hold_reg[29]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.433 14.579 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[29]/C
|
|
clock pessimism 0.228 14.806
|
|
clock uncertainty -0.061 14.745
|
|
SLICE_X6Y180 FDCE (Recov_fdce_C_CLR) -0.292 14.453 usb_inst/range_profile_hold_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time 14.453
|
|
arrival time -8.208
|
|
-------------------------------------------------------------------
|
|
slack 6.245
|
|
|
|
Slack (MET) : 6.245ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[30]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.350ns (logic 0.484ns (14.450%) route 2.866ns (85.550%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.579ns = ( 14.579 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.874 8.208 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y180 FDCE f usb_inst/range_profile_hold_reg[30]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.433 14.579 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[30]/C
|
|
clock pessimism 0.228 14.806
|
|
clock uncertainty -0.061 14.745
|
|
SLICE_X6Y180 FDCE (Recov_fdce_C_CLR) -0.292 14.453 usb_inst/range_profile_hold_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time 14.453
|
|
arrival time -8.208
|
|
-------------------------------------------------------------------
|
|
slack 6.245
|
|
|
|
Slack (MET) : 6.245ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[31]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.350ns (logic 0.484ns (14.450%) route 2.866ns (85.550%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.579ns = ( 14.579 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.874 8.208 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y180 FDCE f usb_inst/range_profile_hold_reg[31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.433 14.579 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[31]/C
|
|
clock pessimism 0.228 14.806
|
|
clock uncertainty -0.061 14.745
|
|
SLICE_X6Y180 FDCE (Recov_fdce_C_CLR) -0.292 14.453 usb_inst/range_profile_hold_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time 14.453
|
|
arrival time -8.208
|
|
-------------------------------------------------------------------
|
|
slack 6.245
|
|
|
|
Slack (MET) : 6.248ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[24]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.330ns (logic 0.484ns (14.533%) route 2.846ns (85.467%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.030ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.587ns = ( 14.587 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.242ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.855 8.189 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y186 FDCE f usb_inst/rx_data_captured_reg[24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.441 14.587 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y186 FDCE r usb_inst/rx_data_captured_reg[24]/C
|
|
clock pessimism 0.242 14.828
|
|
clock uncertainty -0.061 14.767
|
|
SLICE_X0Y186 FDCE (Recov_fdce_C_CLR) -0.331 14.436 usb_inst/rx_data_captured_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 14.436
|
|
arrival time -8.189
|
|
-------------------------------------------------------------------
|
|
slack 6.248
|
|
|
|
Slack (MET) : 6.248ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[25]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.330ns (logic 0.484ns (14.533%) route 2.846ns (85.467%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.030ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.587ns = ( 14.587 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.242ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.855 8.189 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y186 FDCE f usb_inst/rx_data_captured_reg[25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.441 14.587 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y186 FDCE r usb_inst/rx_data_captured_reg[25]/C
|
|
clock pessimism 0.242 14.828
|
|
clock uncertainty -0.061 14.767
|
|
SLICE_X0Y186 FDCE (Recov_fdce_C_CLR) -0.331 14.436 usb_inst/rx_data_captured_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 14.436
|
|
arrival time -8.189
|
|
-------------------------------------------------------------------
|
|
slack 6.248
|
|
|
|
Slack (MET) : 6.256ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[10]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.689%) route 2.811ns (85.311%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.057ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.153 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y176 FDCE f usb_inst/doppler_imag_hold_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.428 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[10]/C
|
|
clock pessimism 0.228 14.801
|
|
clock uncertainty -0.061 14.740
|
|
SLICE_X4Y176 FDCE (Recov_fdce_C_CLR) -0.331 14.409 usb_inst/doppler_imag_hold_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 14.409
|
|
arrival time -8.153
|
|
-------------------------------------------------------------------
|
|
slack 6.256
|
|
|
|
Slack (MET) : 6.256ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[13]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.689%) route 2.811ns (85.311%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.057ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.153 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y176 FDCE f usb_inst/doppler_imag_hold_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.428 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[13]/C
|
|
clock pessimism 0.228 14.801
|
|
clock uncertainty -0.061 14.740
|
|
SLICE_X4Y176 FDCE (Recov_fdce_C_CLR) -0.331 14.409 usb_inst/doppler_imag_hold_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 14.409
|
|
arrival time -8.153
|
|
-------------------------------------------------------------------
|
|
slack 6.256
|
|
|
|
Slack (MET) : 6.256ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[14]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.689%) route 2.811ns (85.311%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.057ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.153 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y176 FDCE f usb_inst/doppler_imag_hold_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.428 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[14]/C
|
|
clock pessimism 0.228 14.801
|
|
clock uncertainty -0.061 14.740
|
|
SLICE_X4Y176 FDCE (Recov_fdce_C_CLR) -0.331 14.409 usb_inst/doppler_imag_hold_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 14.409
|
|
arrival time -8.153
|
|
-------------------------------------------------------------------
|
|
slack 6.256
|
|
|
|
Slack (MET) : 6.256ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[15]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.689%) route 2.811ns (85.311%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.057ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.153 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y176 FDCE f usb_inst/doppler_imag_hold_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.428 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[15]/C
|
|
clock pessimism 0.228 14.801
|
|
clock uncertainty -0.061 14.740
|
|
SLICE_X4Y176 FDCE (Recov_fdce_C_CLR) -0.331 14.409 usb_inst/doppler_imag_hold_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 14.409
|
|
arrival time -8.153
|
|
-------------------------------------------------------------------
|
|
slack 6.256
|
|
|
|
Slack (MET) : 6.256ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[3]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.689%) route 2.811ns (85.311%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.057ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.153 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y176 FDCE f usb_inst/doppler_imag_hold_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.428 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[3]/C
|
|
clock pessimism 0.228 14.801
|
|
clock uncertainty -0.061 14.740
|
|
SLICE_X4Y176 FDCE (Recov_fdce_C_CLR) -0.331 14.409 usb_inst/doppler_imag_hold_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.409
|
|
arrival time -8.153
|
|
-------------------------------------------------------------------
|
|
slack 6.256
|
|
|
|
Slack (MET) : 6.256ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[8]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.689%) route 2.811ns (85.311%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.057ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.153 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y176 FDCE f usb_inst/doppler_imag_hold_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.428 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[8]/C
|
|
clock pessimism 0.228 14.801
|
|
clock uncertainty -0.061 14.740
|
|
SLICE_X4Y176 FDCE (Recov_fdce_C_CLR) -0.331 14.409 usb_inst/doppler_imag_hold_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 14.409
|
|
arrival time -8.153
|
|
-------------------------------------------------------------------
|
|
slack 6.256
|
|
|
|
Slack (MET) : 6.256ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[9]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.689%) route 2.811ns (85.311%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.057ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.153 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y176 FDCE f usb_inst/doppler_imag_hold_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.428 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_imag_hold_reg[9]/C
|
|
clock pessimism 0.228 14.801
|
|
clock uncertainty -0.061 14.740
|
|
SLICE_X4Y176 FDCE (Recov_fdce_C_CLR) -0.331 14.409 usb_inst/doppler_imag_hold_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 14.409
|
|
arrival time -8.153
|
|
-------------------------------------------------------------------
|
|
slack 6.256
|
|
|
|
Slack (MET) : 6.256ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[2]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.689%) route 2.811ns (85.311%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.057ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.574ns = ( 14.574 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.153 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y176 FDCE f usb_inst/doppler_real_hold_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.428 14.574 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y176 FDCE r usb_inst/doppler_real_hold_reg[2]/C
|
|
clock pessimism 0.228 14.801
|
|
clock uncertainty -0.061 14.740
|
|
SLICE_X4Y176 FDCE (Recov_fdce_C_CLR) -0.331 14.409 usb_inst/doppler_real_hold_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 14.409
|
|
arrival time -8.153
|
|
-------------------------------------------------------------------
|
|
slack 6.256
|
|
|
|
Slack (MET) : 6.258ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[10]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.688%) route 2.811ns (85.312%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.154 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y177 FDCE f usb_inst/range_profile_hold_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[10]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_hold_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.154
|
|
-------------------------------------------------------------------
|
|
slack 6.258
|
|
|
|
Slack (MET) : 6.258ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[11]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.688%) route 2.811ns (85.312%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.154 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y177 FDCE f usb_inst/range_profile_hold_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[11]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_hold_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.154
|
|
-------------------------------------------------------------------
|
|
slack 6.258
|
|
|
|
Slack (MET) : 6.258ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[13]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.688%) route 2.811ns (85.312%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.154 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y177 FDCE f usb_inst/range_profile_hold_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[13]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_hold_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.154
|
|
-------------------------------------------------------------------
|
|
slack 6.258
|
|
|
|
Slack (MET) : 6.258ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[14]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.688%) route 2.811ns (85.312%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.154 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y177 FDCE f usb_inst/range_profile_hold_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[14]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_hold_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.154
|
|
-------------------------------------------------------------------
|
|
slack 6.258
|
|
|
|
Slack (MET) : 6.258ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[15]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.688%) route 2.811ns (85.312%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.154 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y177 FDCE f usb_inst/range_profile_hold_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[15]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_hold_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.154
|
|
-------------------------------------------------------------------
|
|
slack 6.258
|
|
|
|
Slack (MET) : 6.258ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[17]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.688%) route 2.811ns (85.312%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.154 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y177 FDCE f usb_inst/range_profile_hold_reg[17]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[17]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_hold_reg[17]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.154
|
|
-------------------------------------------------------------------
|
|
slack 6.258
|
|
|
|
Slack (MET) : 6.258ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[1]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.688%) route 2.811ns (85.312%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.154 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y177 FDCE f usb_inst/range_profile_hold_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[1]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_hold_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.154
|
|
-------------------------------------------------------------------
|
|
slack 6.258
|
|
|
|
Slack (MET) : 6.258ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[9]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.295ns (logic 0.484ns (14.688%) route 2.811ns (85.312%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.820 8.154 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y177 FDCE f usb_inst/range_profile_hold_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y177 FDCE r usb_inst/range_profile_hold_reg[9]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X7Y177 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/range_profile_hold_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -8.154
|
|
-------------------------------------------------------------------
|
|
slack 6.258
|
|
|
|
Slack (MET) : 6.279ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[16]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.350ns (logic 0.484ns (14.450%) route 2.866ns (85.550%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.579ns = ( 14.579 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.874 8.208 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y180 FDCE f usb_inst/range_profile_hold_reg[16]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.433 14.579 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[16]/C
|
|
clock pessimism 0.228 14.806
|
|
clock uncertainty -0.061 14.745
|
|
SLICE_X6Y180 FDCE (Recov_fdce_C_CLR) -0.258 14.487 usb_inst/range_profile_hold_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time 14.487
|
|
arrival time -8.208
|
|
-------------------------------------------------------------------
|
|
slack 6.279
|
|
|
|
Slack (MET) : 6.279ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[22]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.350ns (logic 0.484ns (14.450%) route 2.866ns (85.550%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.579ns = ( 14.579 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.874 8.208 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y180 FDCE f usb_inst/range_profile_hold_reg[22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.433 14.579 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[22]/C
|
|
clock pessimism 0.228 14.806
|
|
clock uncertainty -0.061 14.745
|
|
SLICE_X6Y180 FDCE (Recov_fdce_C_CLR) -0.258 14.487 usb_inst/range_profile_hold_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time 14.487
|
|
arrival time -8.208
|
|
-------------------------------------------------------------------
|
|
slack 6.279
|
|
|
|
Slack (MET) : 6.279ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[25]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.350ns (logic 0.484ns (14.450%) route 2.866ns (85.550%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.579ns = ( 14.579 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.874 8.208 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y180 FDCE f usb_inst/range_profile_hold_reg[25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.433 14.579 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[25]/C
|
|
clock pessimism 0.228 14.806
|
|
clock uncertainty -0.061 14.745
|
|
SLICE_X6Y180 FDCE (Recov_fdce_C_CLR) -0.258 14.487 usb_inst/range_profile_hold_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time 14.487
|
|
arrival time -8.208
|
|
-------------------------------------------------------------------
|
|
slack 6.279
|
|
|
|
Slack (MET) : 6.279ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[26]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.350ns (logic 0.484ns (14.450%) route 2.866ns (85.550%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.052ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.579ns = ( 14.579 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.874 8.208 usb_inst/por_counter_reg[15]
|
|
SLICE_X6Y180 FDCE f usb_inst/range_profile_hold_reg[26]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.433 14.579 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X6Y180 FDCE r usb_inst/range_profile_hold_reg[26]/C
|
|
clock pessimism 0.228 14.806
|
|
clock uncertainty -0.061 14.745
|
|
SLICE_X6Y180 FDCE (Recov_fdce_C_CLR) -0.258 14.487 usb_inst/range_profile_hold_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time 14.487
|
|
arrival time -8.208
|
|
-------------------------------------------------------------------
|
|
slack 6.279
|
|
|
|
Slack (MET) : 6.314ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[26]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.318ns (logic 0.484ns (14.588%) route 2.834ns (85.412%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.062ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.568ns = ( 14.568 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.842 8.176 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y166 FDCE f usb_inst/ft601_data_out_reg[26]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.423 14.568 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y166 FDCE r usb_inst/ft601_data_out_reg[26]/C
|
|
clock pessimism 0.228 14.796
|
|
clock uncertainty -0.061 14.735
|
|
OLOGIC_X0Y166 FDCE (Recov_fdce_C_CLR) -0.245 14.490 usb_inst/ft601_data_out_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time 14.490
|
|
arrival time -8.176
|
|
-------------------------------------------------------------------
|
|
slack 6.314
|
|
|
|
Slack (MET) : 6.329ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[20]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.228ns (logic 0.484ns (14.993%) route 2.744ns (85.007%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.580ns = ( 14.580 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.753 8.086 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y181 FDCE f usb_inst/range_profile_hold_reg[20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.434 14.580 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y181 FDCE r usb_inst/range_profile_hold_reg[20]/C
|
|
clock pessimism 0.228 14.807
|
|
clock uncertainty -0.061 14.746
|
|
SLICE_X4Y181 FDCE (Recov_fdce_C_CLR) -0.331 14.415 usb_inst/range_profile_hold_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time 14.415
|
|
arrival time -8.086
|
|
-------------------------------------------------------------------
|
|
slack 6.329
|
|
|
|
Slack (MET) : 6.329ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[24]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.228ns (logic 0.484ns (14.993%) route 2.744ns (85.007%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.580ns = ( 14.580 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.753 8.086 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y181 FDCE f usb_inst/range_profile_hold_reg[24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.434 14.580 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y181 FDCE r usb_inst/range_profile_hold_reg[24]/C
|
|
clock pessimism 0.228 14.807
|
|
clock uncertainty -0.061 14.746
|
|
SLICE_X4Y181 FDCE (Recov_fdce_C_CLR) -0.331 14.415 usb_inst/range_profile_hold_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time 14.415
|
|
arrival time -8.086
|
|
-------------------------------------------------------------------
|
|
slack 6.329
|
|
|
|
Slack (MET) : 6.329ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[28]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.228ns (logic 0.484ns (14.993%) route 2.744ns (85.007%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.051ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.580ns = ( 14.580 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.753 8.086 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y181 FDCE f usb_inst/range_profile_hold_reg[28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.434 14.580 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y181 FDCE r usb_inst/range_profile_hold_reg[28]/C
|
|
clock pessimism 0.228 14.807
|
|
clock uncertainty -0.061 14.746
|
|
SLICE_X4Y181 FDCE (Recov_fdce_C_CLR) -0.331 14.415 usb_inst/range_profile_hold_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time 14.415
|
|
arrival time -8.086
|
|
-------------------------------------------------------------------
|
|
slack 6.329
|
|
|
|
Slack (MET) : 6.428ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[21]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.200ns (logic 0.484ns (15.125%) route 2.716ns (84.875%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.065ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.565ns = ( 14.565 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.724 8.058 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y167 FDCE f usb_inst/ft601_data_out_reg[21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.420 14.565 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y167 FDCE r usb_inst/ft601_data_out_reg[21]/C
|
|
clock pessimism 0.228 14.793
|
|
clock uncertainty -0.061 14.732
|
|
OLOGIC_X0Y167 FDCE (Recov_fdce_C_CLR) -0.245 14.487 usb_inst/ft601_data_out_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 14.487
|
|
arrival time -8.058
|
|
-------------------------------------------------------------------
|
|
slack 6.428
|
|
|
|
Slack (MET) : 6.447ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_data_pending_reg/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.203ns (logic 0.484ns (15.109%) route 2.719ns (84.891%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.030ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.587ns = ( 14.587 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.242ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.728 8.062 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y186 FDCE f usb_inst/doppler_data_pending_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.441 14.587 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y186 FDCE r usb_inst/doppler_data_pending_reg/C
|
|
clock pessimism 0.242 14.828
|
|
clock uncertainty -0.061 14.767
|
|
SLICE_X2Y186 FDCE (Recov_fdce_C_CLR) -0.258 14.509 usb_inst/doppler_data_pending_reg
|
|
-------------------------------------------------------------------
|
|
required time 14.509
|
|
arrival time -8.062
|
|
-------------------------------------------------------------------
|
|
slack 6.447
|
|
|
|
Slack (MET) : 6.546ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[23]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.082ns (logic 0.484ns (15.703%) route 2.598ns (84.297%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.065ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.565ns = ( 14.565 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.607 7.941 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y168 FDCE f usb_inst/ft601_data_out_reg[23]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.420 14.565 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y168 FDCE r usb_inst/ft601_data_out_reg[23]/C
|
|
clock pessimism 0.228 14.793
|
|
clock uncertainty -0.061 14.732
|
|
OLOGIC_X0Y168 FDCE (Recov_fdce_C_CLR) -0.245 14.487 usb_inst/ft601_data_out_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 14.487
|
|
arrival time -7.941
|
|
-------------------------------------------------------------------
|
|
slack 6.546
|
|
|
|
Slack (MET) : 6.548ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[2]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 3.101ns (logic 0.484ns (15.606%) route 2.617ns (84.394%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.031ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.586ns = ( 14.586 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.242ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.626 7.960 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y185 FDCE f usb_inst/byte_counter_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.440 14.586 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y185 FDCE r usb_inst/byte_counter_reg[2]/C
|
|
clock pessimism 0.242 14.827
|
|
clock uncertainty -0.061 14.766
|
|
SLICE_X2Y185 FDCE (Recov_fdce_C_CLR) -0.258 14.508 usb_inst/byte_counter_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time 14.508
|
|
arrival time -7.960
|
|
-------------------------------------------------------------------
|
|
slack 6.548
|
|
|
|
Slack (MET) : 6.586ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[12]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.967ns (logic 0.484ns (16.315%) route 2.483ns (83.685%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.491 7.825 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y178 FDCE f usb_inst/doppler_imag_hold_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_imag_hold_reg[12]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_imag_hold_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -7.825
|
|
-------------------------------------------------------------------
|
|
slack 6.586
|
|
|
|
Slack (MET) : 6.586ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[0]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.967ns (logic 0.484ns (16.315%) route 2.483ns (83.685%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.491 7.825 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y178 FDCE f usb_inst/doppler_real_hold_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[0]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_hold_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -7.825
|
|
-------------------------------------------------------------------
|
|
slack 6.586
|
|
|
|
Slack (MET) : 6.586ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[1]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.967ns (logic 0.484ns (16.315%) route 2.483ns (83.685%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.491 7.825 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y178 FDCE f usb_inst/doppler_real_hold_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[1]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_hold_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -7.825
|
|
-------------------------------------------------------------------
|
|
slack 6.586
|
|
|
|
Slack (MET) : 6.586ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[3]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.967ns (logic 0.484ns (16.315%) route 2.483ns (83.685%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.491 7.825 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y178 FDCE f usb_inst/doppler_real_hold_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[3]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_hold_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -7.825
|
|
-------------------------------------------------------------------
|
|
slack 6.586
|
|
|
|
Slack (MET) : 6.586ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[4]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.967ns (logic 0.484ns (16.315%) route 2.483ns (83.685%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.491 7.825 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y178 FDCE f usb_inst/doppler_real_hold_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[4]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_hold_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -7.825
|
|
-------------------------------------------------------------------
|
|
slack 6.586
|
|
|
|
Slack (MET) : 6.586ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[5]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.967ns (logic 0.484ns (16.315%) route 2.483ns (83.685%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.491 7.825 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y178 FDCE f usb_inst/doppler_real_hold_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[5]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_hold_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -7.825
|
|
-------------------------------------------------------------------
|
|
slack 6.586
|
|
|
|
Slack (MET) : 6.586ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[6]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.967ns (logic 0.484ns (16.315%) route 2.483ns (83.685%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.491 7.825 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y178 FDCE f usb_inst/doppler_real_hold_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[6]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_hold_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -7.825
|
|
-------------------------------------------------------------------
|
|
slack 6.586
|
|
|
|
Slack (MET) : 6.586ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[9]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.967ns (logic 0.484ns (16.315%) route 2.483ns (83.685%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.055ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.576ns = ( 14.576 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.491 7.825 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y178 FDCE f usb_inst/doppler_real_hold_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.430 14.576 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y178 FDCE r usb_inst/doppler_real_hold_reg[9]/C
|
|
clock pessimism 0.228 14.803
|
|
clock uncertainty -0.061 14.742
|
|
SLICE_X4Y178 FDCE (Recov_fdce_C_CLR) -0.331 14.411 usb_inst/doppler_real_hold_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time 14.411
|
|
arrival time -7.825
|
|
-------------------------------------------------------------------
|
|
slack 6.586
|
|
|
|
Slack (MET) : 6.597ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[12]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.958ns (logic 0.484ns (16.363%) route 2.474ns (83.637%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.578ns = ( 14.578 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.482 7.816 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y179 FDCE f usb_inst/range_profile_hold_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.432 14.578 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[12]/C
|
|
clock pessimism 0.228 14.805
|
|
clock uncertainty -0.061 14.744
|
|
SLICE_X7Y179 FDCE (Recov_fdce_C_CLR) -0.331 14.413 usb_inst/range_profile_hold_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time 14.413
|
|
arrival time -7.816
|
|
-------------------------------------------------------------------
|
|
slack 6.597
|
|
|
|
Slack (MET) : 6.597ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[18]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.958ns (logic 0.484ns (16.363%) route 2.474ns (83.637%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.578ns = ( 14.578 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.482 7.816 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y179 FDCE f usb_inst/range_profile_hold_reg[18]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.432 14.578 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[18]/C
|
|
clock pessimism 0.228 14.805
|
|
clock uncertainty -0.061 14.744
|
|
SLICE_X7Y179 FDCE (Recov_fdce_C_CLR) -0.331 14.413 usb_inst/range_profile_hold_reg[18]
|
|
-------------------------------------------------------------------
|
|
required time 14.413
|
|
arrival time -7.816
|
|
-------------------------------------------------------------------
|
|
slack 6.597
|
|
|
|
Slack (MET) : 6.597ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[19]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.958ns (logic 0.484ns (16.363%) route 2.474ns (83.637%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.578ns = ( 14.578 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.482 7.816 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y179 FDCE f usb_inst/range_profile_hold_reg[19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.432 14.578 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[19]/C
|
|
clock pessimism 0.228 14.805
|
|
clock uncertainty -0.061 14.744
|
|
SLICE_X7Y179 FDCE (Recov_fdce_C_CLR) -0.331 14.413 usb_inst/range_profile_hold_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time 14.413
|
|
arrival time -7.816
|
|
-------------------------------------------------------------------
|
|
slack 6.597
|
|
|
|
Slack (MET) : 6.597ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[21]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.958ns (logic 0.484ns (16.363%) route 2.474ns (83.637%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.578ns = ( 14.578 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.482 7.816 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y179 FDCE f usb_inst/range_profile_hold_reg[21]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.432 14.578 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[21]/C
|
|
clock pessimism 0.228 14.805
|
|
clock uncertainty -0.061 14.744
|
|
SLICE_X7Y179 FDCE (Recov_fdce_C_CLR) -0.331 14.413 usb_inst/range_profile_hold_reg[21]
|
|
-------------------------------------------------------------------
|
|
required time 14.413
|
|
arrival time -7.816
|
|
-------------------------------------------------------------------
|
|
slack 6.597
|
|
|
|
Slack (MET) : 6.597ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[23]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.958ns (logic 0.484ns (16.363%) route 2.474ns (83.637%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.578ns = ( 14.578 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.482 7.816 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y179 FDCE f usb_inst/range_profile_hold_reg[23]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.432 14.578 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[23]/C
|
|
clock pessimism 0.228 14.805
|
|
clock uncertainty -0.061 14.744
|
|
SLICE_X7Y179 FDCE (Recov_fdce_C_CLR) -0.331 14.413 usb_inst/range_profile_hold_reg[23]
|
|
-------------------------------------------------------------------
|
|
required time 14.413
|
|
arrival time -7.816
|
|
-------------------------------------------------------------------
|
|
slack 6.597
|
|
|
|
Slack (MET) : 6.597ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[8]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.958ns (logic 0.484ns (16.363%) route 2.474ns (83.637%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.053ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.578ns = ( 14.578 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.482 7.816 usb_inst/por_counter_reg[15]
|
|
SLICE_X7Y179 FDCE f usb_inst/range_profile_hold_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.432 14.578 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X7Y179 FDCE r usb_inst/range_profile_hold_reg[8]/C
|
|
clock pessimism 0.228 14.805
|
|
clock uncertainty -0.061 14.744
|
|
SLICE_X7Y179 FDCE (Recov_fdce_C_CLR) -0.331 14.413 usb_inst/range_profile_hold_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time 14.413
|
|
arrival time -7.816
|
|
-------------------------------------------------------------------
|
|
slack 6.597
|
|
|
|
Slack (MET) : 6.602ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[1]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.957ns (logic 0.484ns (16.368%) route 2.473ns (83.632%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.582ns = ( 14.582 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.481 7.815 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y184 FDCE f usb_inst/byte_counter_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.436 14.582 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[1]/C
|
|
clock pessimism 0.228 14.809
|
|
clock uncertainty -0.061 14.748
|
|
SLICE_X4Y184 FDCE (Recov_fdce_C_CLR) -0.331 14.417 usb_inst/byte_counter_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time 14.417
|
|
arrival time -7.815
|
|
-------------------------------------------------------------------
|
|
slack 6.602
|
|
|
|
Slack (MET) : 6.602ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[3]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.957ns (logic 0.484ns (16.368%) route 2.473ns (83.632%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.582ns = ( 14.582 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.481 7.815 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y184 FDCE f usb_inst/byte_counter_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.436 14.582 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[3]/C
|
|
clock pessimism 0.228 14.809
|
|
clock uncertainty -0.061 14.748
|
|
SLICE_X4Y184 FDCE (Recov_fdce_C_CLR) -0.331 14.417 usb_inst/byte_counter_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time 14.417
|
|
arrival time -7.815
|
|
-------------------------------------------------------------------
|
|
slack 6.602
|
|
|
|
Slack (MET) : 6.602ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[4]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.957ns (logic 0.484ns (16.368%) route 2.473ns (83.632%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.582ns = ( 14.582 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.481 7.815 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y184 FDCE f usb_inst/byte_counter_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.436 14.582 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[4]/C
|
|
clock pessimism 0.228 14.809
|
|
clock uncertainty -0.061 14.748
|
|
SLICE_X4Y184 FDCE (Recov_fdce_C_CLR) -0.331 14.417 usb_inst/byte_counter_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time 14.417
|
|
arrival time -7.815
|
|
-------------------------------------------------------------------
|
|
slack 6.602
|
|
|
|
Slack (MET) : 6.602ns (required time - arrival time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/byte_counter_reg[5]/CLR
|
|
(recovery check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Recovery (Max at Slow Process Corner)
|
|
Requirement: 10.000ns (ft601_clk_in rise@10.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 2.957ns (logic 0.484ns (16.368%) route 2.473ns (83.632%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: -0.049ns (DCD - SCD + CPR)
|
|
Destination Clock Delay (DCD): 4.582ns = ( 14.582 - 10.000 )
|
|
Source Clock Delay (SCD): 4.858ns
|
|
Clock Pessimism Removal (CPR): 0.228ns
|
|
Clock Uncertainty: 0.061ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.071ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.992 6.229 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.105 6.334 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 1.481 7.815 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y184 FDCE f usb_inst/byte_counter_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
10.000 10.000 r
|
|
J20 0.000 10.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 10.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.334 11.334 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.734 13.069 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.077 13.146 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.436 14.582 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y184 FDCE r usb_inst/byte_counter_reg[5]/C
|
|
clock pessimism 0.228 14.809
|
|
clock uncertainty -0.061 14.748
|
|
SLICE_X4Y184 FDCE (Recov_fdce_C_CLR) -0.331 14.417 usb_inst/byte_counter_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time 14.417
|
|
arrival time -7.815
|
|
-------------------------------------------------------------------
|
|
slack 6.602
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.978ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[2]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.005ns (logic 0.186ns (18.508%) route 0.819ns (81.492%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.027ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.114ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.358 2.608 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y180 FDCE f usb_inst/ft601_data_out_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.911 2.114 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y180 FDCE r usb_inst/ft601_data_out_reg[2]/C
|
|
clock pessimism -0.484 1.630
|
|
OLOGIC_X0Y180 FDCE (Remov_fdce_C_CLR) 0.000 1.630 usb_inst/ft601_data_out_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.630
|
|
arrival time 2.608
|
|
-------------------------------------------------------------------
|
|
slack 0.978
|
|
|
|
Slack (MET) : 1.040ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.067ns (logic 0.186ns (17.438%) route 0.881ns (82.562%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.027ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.114ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.420 2.670 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y179 FDCE f usb_inst/ft601_data_out_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.911 2.114 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y179 FDCE r usb_inst/ft601_data_out_reg[0]/C
|
|
clock pessimism -0.484 1.630
|
|
OLOGIC_X0Y179 FDCE (Remov_fdce_C_CLR) 0.000 1.630 usb_inst/ft601_data_out_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.630
|
|
arrival time 2.670
|
|
-------------------------------------------------------------------
|
|
slack 1.040
|
|
|
|
Slack (MET) : 1.158ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[12]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.097ns (logic 0.186ns (16.955%) route 0.911ns (83.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.451 2.700 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y179 FDCE f usb_inst/doppler_imag_cap_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_imag_cap_reg[12]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X2Y179 FDCE (Remov_fdce_C_CLR) -0.067 1.542 usb_inst/doppler_imag_cap_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time -1.542
|
|
arrival time 2.700
|
|
-------------------------------------------------------------------
|
|
slack 1.158
|
|
|
|
Slack (MET) : 1.158ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.097ns (logic 0.186ns (16.955%) route 0.911ns (83.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.451 2.700 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y179 FDCE f usb_inst/doppler_real_cap_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[0]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X2Y179 FDCE (Remov_fdce_C_CLR) -0.067 1.542 usb_inst/doppler_real_cap_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.542
|
|
arrival time 2.700
|
|
-------------------------------------------------------------------
|
|
slack 1.158
|
|
|
|
Slack (MET) : 1.158ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[12]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.097ns (logic 0.186ns (16.955%) route 0.911ns (83.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.451 2.700 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y179 FDCE f usb_inst/doppler_real_cap_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[12]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X2Y179 FDCE (Remov_fdce_C_CLR) -0.067 1.542 usb_inst/doppler_real_cap_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time -1.542
|
|
arrival time 2.700
|
|
-------------------------------------------------------------------
|
|
slack 1.158
|
|
|
|
Slack (MET) : 1.158ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[13]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.097ns (logic 0.186ns (16.955%) route 0.911ns (83.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.451 2.700 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y179 FDCE f usb_inst/doppler_real_cap_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y179 FDCE r usb_inst/doppler_real_cap_reg[13]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X2Y179 FDCE (Remov_fdce_C_CLR) -0.067 1.542 usb_inst/doppler_real_cap_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time -1.542
|
|
arrival time 2.700
|
|
-------------------------------------------------------------------
|
|
slack 1.158
|
|
|
|
Slack (MET) : 1.178ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_detection_cap_reg/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.093ns (logic 0.186ns (17.013%) route 0.907ns (82.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.447 2.696 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y180 FDCE f usb_inst/cfar_detection_cap_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_detection_cap_reg/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X0Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.518 usb_inst/cfar_detection_cap_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.518
|
|
arrival time 2.696
|
|
-------------------------------------------------------------------
|
|
slack 1.178
|
|
|
|
Slack (MET) : 1.178ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_detection_hold_reg/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.093ns (logic 0.186ns (17.013%) route 0.907ns (82.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.447 2.696 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y180 FDCE f usb_inst/cfar_detection_hold_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_detection_hold_reg/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X0Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.518 usb_inst/cfar_detection_hold_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.518
|
|
arrival time 2.696
|
|
-------------------------------------------------------------------
|
|
slack 1.178
|
|
|
|
Slack (MET) : 1.178ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_valid_sync_d_reg/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.093ns (logic 0.186ns (17.013%) route 0.907ns (82.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.447 2.696 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y180 FDCE f usb_inst/cfar_valid_sync_d_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_valid_sync_d_reg/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X0Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.518 usb_inst/cfar_valid_sync_d_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.518
|
|
arrival time 2.696
|
|
-------------------------------------------------------------------
|
|
slack 1.178
|
|
|
|
Slack (MET) : 1.178ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_valid_sync_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.093ns (logic 0.186ns (17.013%) route 0.907ns (82.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.447 2.696 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y180 FDCE f usb_inst/cfar_valid_sync_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_valid_sync_reg[0]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X0Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.518 usb_inst/cfar_valid_sync_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.518
|
|
arrival time 2.696
|
|
-------------------------------------------------------------------
|
|
slack 1.178
|
|
|
|
Slack (MET) : 1.178ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_valid_sync_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.093ns (logic 0.186ns (17.013%) route 0.907ns (82.987%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.447 2.696 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y180 FDCE f usb_inst/cfar_valid_sync_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y180 FDCE r usb_inst/cfar_valid_sync_reg[1]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X0Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.518 usb_inst/cfar_valid_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.518
|
|
arrival time 2.696
|
|
-------------------------------------------------------------------
|
|
slack 1.178
|
|
|
|
Slack (MET) : 1.183ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[10]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.097ns (logic 0.186ns (16.955%) route 0.911ns (83.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.451 2.700 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y179 FDCE f usb_inst/doppler_imag_cap_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y179 FDCE r usb_inst/doppler_imag_cap_reg[10]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X3Y179 FDCE (Remov_fdce_C_CLR) -0.092 1.517 usb_inst/doppler_imag_cap_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 2.700
|
|
-------------------------------------------------------------------
|
|
slack 1.183
|
|
|
|
Slack (MET) : 1.183ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[8]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.097ns (logic 0.186ns (16.955%) route 0.911ns (83.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.451 2.700 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y179 FDCE f usb_inst/doppler_imag_cap_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y179 FDCE r usb_inst/doppler_imag_cap_reg[8]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X3Y179 FDCE (Remov_fdce_C_CLR) -0.092 1.517 usb_inst/doppler_imag_cap_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 2.700
|
|
-------------------------------------------------------------------
|
|
slack 1.183
|
|
|
|
Slack (MET) : 1.183ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[10]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.097ns (logic 0.186ns (16.955%) route 0.911ns (83.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.451 2.700 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y179 FDCE f usb_inst/doppler_real_cap_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y179 FDCE r usb_inst/doppler_real_cap_reg[10]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X3Y179 FDCE (Remov_fdce_C_CLR) -0.092 1.517 usb_inst/doppler_real_cap_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 2.700
|
|
-------------------------------------------------------------------
|
|
slack 1.183
|
|
|
|
Slack (MET) : 1.183ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[7]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.097ns (logic 0.186ns (16.955%) route 0.911ns (83.045%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.451 2.700 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y179 FDCE f usb_inst/doppler_real_cap_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y179 FDCE r usb_inst/doppler_real_cap_reg[7]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X3Y179 FDCE (Remov_fdce_C_CLR) -0.092 1.517 usb_inst/doppler_real_cap_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 2.700
|
|
-------------------------------------------------------------------
|
|
slack 1.183
|
|
|
|
Slack (MET) : 1.211ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[2]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.125ns (logic 0.186ns (16.531%) route 0.939ns (83.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.479 2.728 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y179 FDCE f usb_inst/doppler_imag_cap_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y179 FDCE r usb_inst/doppler_imag_cap_reg[2]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X1Y179 FDCE (Remov_fdce_C_CLR) -0.092 1.517 usb_inst/doppler_imag_cap_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 2.728
|
|
-------------------------------------------------------------------
|
|
slack 1.211
|
|
|
|
Slack (MET) : 1.211ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[9]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.125ns (logic 0.186ns (16.531%) route 0.939ns (83.469%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.479 2.728 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y179 FDCE f usb_inst/doppler_real_cap_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y179 FDCE r usb_inst/doppler_real_cap_reg[9]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X1Y179 FDCE (Remov_fdce_C_CLR) -0.092 1.517 usb_inst/doppler_real_cap_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 2.728
|
|
-------------------------------------------------------------------
|
|
slack 1.211
|
|
|
|
Slack (MET) : 1.215ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.129ns (logic 0.186ns (16.477%) route 0.943ns (83.523%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.482 2.732 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y179 FDCE f usb_inst/doppler_imag_cap_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y179 FDCE r usb_inst/doppler_imag_cap_reg[0]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X0Y179 FDCE (Remov_fdce_C_CLR) -0.092 1.517 usb_inst/doppler_imag_cap_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 2.732
|
|
-------------------------------------------------------------------
|
|
slack 1.215
|
|
|
|
Slack (MET) : 1.215ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[11]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.129ns (logic 0.186ns (16.477%) route 0.943ns (83.523%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.006ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.482 2.732 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y179 FDCE f usb_inst/doppler_imag_cap_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y179 FDCE r usb_inst/doppler_imag_cap_reg[11]/C
|
|
clock pessimism -0.508 1.609
|
|
SLICE_X0Y179 FDCE (Remov_fdce_C_CLR) -0.092 1.517 usb_inst/doppler_imag_cap_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -1.517
|
|
arrival time 2.732
|
|
-------------------------------------------------------------------
|
|
slack 1.215
|
|
|
|
Slack (MET) : 1.255ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[3]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.192ns (logic 0.186ns (15.599%) route 1.006ns (84.401%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.546 2.795 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y177 FDCE f usb_inst/range_profile_cap_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y177 FDCE r usb_inst/range_profile_cap_reg[3]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X2Y177 FDCE (Remov_fdce_C_CLR) -0.067 1.540 usb_inst/range_profile_cap_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.540
|
|
arrival time 2.795
|
|
-------------------------------------------------------------------
|
|
slack 1.255
|
|
|
|
Slack (MET) : 1.255ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[5]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.192ns (logic 0.186ns (15.599%) route 1.006ns (84.401%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.546 2.795 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y177 FDCE f usb_inst/range_profile_cap_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y177 FDCE r usb_inst/range_profile_cap_reg[5]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X2Y177 FDCE (Remov_fdce_C_CLR) -0.067 1.540 usb_inst/range_profile_cap_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -1.540
|
|
arrival time 2.795
|
|
-------------------------------------------------------------------
|
|
slack 1.255
|
|
|
|
Slack (MET) : 1.255ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[6]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.192ns (logic 0.186ns (15.599%) route 1.006ns (84.401%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.546 2.795 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y177 FDCE f usb_inst/range_profile_cap_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y177 FDCE r usb_inst/range_profile_cap_reg[6]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X2Y177 FDCE (Remov_fdce_C_CLR) -0.067 1.540 usb_inst/range_profile_cap_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.540
|
|
arrival time 2.795
|
|
-------------------------------------------------------------------
|
|
slack 1.255
|
|
|
|
Slack (MET) : 1.255ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[7]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.192ns (logic 0.186ns (15.599%) route 1.006ns (84.401%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.546 2.795 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y177 FDCE f usb_inst/range_profile_cap_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y177 FDCE r usb_inst/range_profile_cap_reg[7]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X2Y177 FDCE (Remov_fdce_C_CLR) -0.067 1.540 usb_inst/range_profile_cap_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.540
|
|
arrival time 2.795
|
|
-------------------------------------------------------------------
|
|
slack 1.255
|
|
|
|
Slack (MET) : 1.260ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[11]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.200ns (logic 0.186ns (15.496%) route 1.014ns (84.504%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.554 2.803 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y180 FDCE f usb_inst/doppler_real_cap_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y180 FDCE r usb_inst/doppler_real_cap_reg[11]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X2Y180 FDCE (Remov_fdce_C_CLR) -0.067 1.543 usb_inst/doppler_real_cap_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -1.543
|
|
arrival time 2.803
|
|
-------------------------------------------------------------------
|
|
slack 1.260
|
|
|
|
Slack (MET) : 1.260ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[14]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.200ns (logic 0.186ns (15.496%) route 1.014ns (84.504%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.554 2.803 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y180 FDCE f usb_inst/doppler_real_cap_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y180 FDCE r usb_inst/doppler_real_cap_reg[14]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X2Y180 FDCE (Remov_fdce_C_CLR) -0.067 1.543 usb_inst/doppler_real_cap_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time -1.543
|
|
arrival time 2.803
|
|
-------------------------------------------------------------------
|
|
slack 1.260
|
|
|
|
Slack (MET) : 1.260ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[15]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.200ns (logic 0.186ns (15.496%) route 1.014ns (84.504%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.554 2.803 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y180 FDCE f usb_inst/doppler_real_cap_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y180 FDCE r usb_inst/doppler_real_cap_reg[15]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X2Y180 FDCE (Remov_fdce_C_CLR) -0.067 1.543 usb_inst/doppler_real_cap_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -1.543
|
|
arrival time 2.803
|
|
-------------------------------------------------------------------
|
|
slack 1.260
|
|
|
|
Slack (MET) : 1.260ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[8]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.200ns (logic 0.186ns (15.496%) route 1.014ns (84.504%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.554 2.803 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y180 FDCE f usb_inst/doppler_real_cap_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y180 FDCE r usb_inst/doppler_real_cap_reg[8]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X2Y180 FDCE (Remov_fdce_C_CLR) -0.067 1.543 usb_inst/doppler_real_cap_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.543
|
|
arrival time 2.803
|
|
-------------------------------------------------------------------
|
|
slack 1.260
|
|
|
|
Slack (MET) : 1.265ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[16]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.203ns (logic 0.186ns (15.459%) route 1.017ns (84.541%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.030ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.557 2.806 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y180 FDCE f usb_inst/range_profile_cap_reg[16]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[16]/C
|
|
clock pessimism -0.484 1.633
|
|
SLICE_X4Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.541 usb_inst/range_profile_cap_reg[16]
|
|
-------------------------------------------------------------------
|
|
required time -1.541
|
|
arrival time 2.806
|
|
-------------------------------------------------------------------
|
|
slack 1.265
|
|
|
|
Slack (MET) : 1.265ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[22]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.203ns (logic 0.186ns (15.459%) route 1.017ns (84.541%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.030ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.557 2.806 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y180 FDCE f usb_inst/range_profile_cap_reg[22]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[22]/C
|
|
clock pessimism -0.484 1.633
|
|
SLICE_X4Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.541 usb_inst/range_profile_cap_reg[22]
|
|
-------------------------------------------------------------------
|
|
required time -1.541
|
|
arrival time 2.806
|
|
-------------------------------------------------------------------
|
|
slack 1.265
|
|
|
|
Slack (MET) : 1.265ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[24]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.203ns (logic 0.186ns (15.459%) route 1.017ns (84.541%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.030ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.557 2.806 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y180 FDCE f usb_inst/range_profile_cap_reg[24]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[24]/C
|
|
clock pessimism -0.484 1.633
|
|
SLICE_X4Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.541 usb_inst/range_profile_cap_reg[24]
|
|
-------------------------------------------------------------------
|
|
required time -1.541
|
|
arrival time 2.806
|
|
-------------------------------------------------------------------
|
|
slack 1.265
|
|
|
|
Slack (MET) : 1.265ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[8]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.203ns (logic 0.186ns (15.459%) route 1.017ns (84.541%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.030ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.117ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.557 2.806 usb_inst/por_counter_reg[15]
|
|
SLICE_X4Y180 FDCE f usb_inst/range_profile_cap_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.914 2.117 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X4Y180 FDCE r usb_inst/range_profile_cap_reg[8]/C
|
|
clock pessimism -0.484 1.633
|
|
SLICE_X4Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.541 usb_inst/range_profile_cap_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.541
|
|
arrival time 2.806
|
|
-------------------------------------------------------------------
|
|
slack 1.265
|
|
|
|
Slack (MET) : 1.280ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[15]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.192ns (logic 0.186ns (15.599%) route 1.006ns (84.401%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.546 2.795 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y177 FDCE f usb_inst/doppler_imag_cap_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y177 FDCE r usb_inst/doppler_imag_cap_reg[15]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X3Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_cap_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.795
|
|
-------------------------------------------------------------------
|
|
slack 1.280
|
|
|
|
Slack (MET) : 1.280ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[3]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.192ns (logic 0.186ns (15.599%) route 1.006ns (84.401%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.546 2.795 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y177 FDCE f usb_inst/doppler_imag_cap_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y177 FDCE r usb_inst/doppler_imag_cap_reg[3]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X3Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_cap_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.795
|
|
-------------------------------------------------------------------
|
|
slack 1.280
|
|
|
|
Slack (MET) : 1.280ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[9]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.192ns (logic 0.186ns (15.599%) route 1.006ns (84.401%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.546 2.795 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y177 FDCE f usb_inst/doppler_imag_cap_reg[9]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y177 FDCE r usb_inst/doppler_imag_cap_reg[9]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X3Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_cap_reg[9]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.795
|
|
-------------------------------------------------------------------
|
|
slack 1.280
|
|
|
|
Slack (MET) : 1.285ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.200ns (logic 0.186ns (15.496%) route 1.014ns (84.504%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.554 2.803 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y180 FDCE f usb_inst/rx_data_captured_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y180 FDCE r usb_inst/rx_data_captured_reg[0]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X3Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.518 usb_inst/rx_data_captured_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.518
|
|
arrival time 2.803
|
|
-------------------------------------------------------------------
|
|
slack 1.285
|
|
|
|
Slack (MET) : 1.285ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[2]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.200ns (logic 0.186ns (15.496%) route 1.014ns (84.504%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.007ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.118ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.554 2.803 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y180 FDCE f usb_inst/rx_data_captured_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.915 2.118 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y180 FDCE r usb_inst/rx_data_captured_reg[2]/C
|
|
clock pessimism -0.508 1.610
|
|
SLICE_X3Y180 FDCE (Remov_fdce_C_CLR) -0.092 1.518 usb_inst/rx_data_captured_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.518
|
|
arrival time 2.803
|
|
-------------------------------------------------------------------
|
|
slack 1.285
|
|
|
|
Slack (MET) : 1.301ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.236ns (logic 0.186ns (15.044%) route 1.050ns (84.956%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.590 2.839 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y176 FDCE f usb_inst/range_profile_hold_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[0]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Remov_fdce_C_CLR) -0.067 1.538 usb_inst/range_profile_hold_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.538
|
|
arrival time 2.839
|
|
-------------------------------------------------------------------
|
|
slack 1.301
|
|
|
|
Slack (MET) : 1.301ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[2]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.236ns (logic 0.186ns (15.044%) route 1.050ns (84.956%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.590 2.839 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y176 FDCE f usb_inst/range_profile_hold_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[2]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Remov_fdce_C_CLR) -0.067 1.538 usb_inst/range_profile_hold_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.538
|
|
arrival time 2.839
|
|
-------------------------------------------------------------------
|
|
slack 1.301
|
|
|
|
Slack (MET) : 1.301ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[3]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.236ns (logic 0.186ns (15.044%) route 1.050ns (84.956%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.590 2.839 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y176 FDCE f usb_inst/range_profile_hold_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[3]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Remov_fdce_C_CLR) -0.067 1.538 usb_inst/range_profile_hold_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.538
|
|
arrival time 2.839
|
|
-------------------------------------------------------------------
|
|
slack 1.301
|
|
|
|
Slack (MET) : 1.301ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[4]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.236ns (logic 0.186ns (15.044%) route 1.050ns (84.956%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.590 2.839 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y176 FDCE f usb_inst/range_profile_hold_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[4]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Remov_fdce_C_CLR) -0.067 1.538 usb_inst/range_profile_hold_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.538
|
|
arrival time 2.839
|
|
-------------------------------------------------------------------
|
|
slack 1.301
|
|
|
|
Slack (MET) : 1.301ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[5]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.236ns (logic 0.186ns (15.044%) route 1.050ns (84.956%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.590 2.839 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y176 FDCE f usb_inst/range_profile_hold_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[5]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Remov_fdce_C_CLR) -0.067 1.538 usb_inst/range_profile_hold_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -1.538
|
|
arrival time 2.839
|
|
-------------------------------------------------------------------
|
|
slack 1.301
|
|
|
|
Slack (MET) : 1.301ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[6]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.236ns (logic 0.186ns (15.044%) route 1.050ns (84.956%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.590 2.839 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y176 FDCE f usb_inst/range_profile_hold_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[6]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Remov_fdce_C_CLR) -0.067 1.538 usb_inst/range_profile_hold_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.538
|
|
arrival time 2.839
|
|
-------------------------------------------------------------------
|
|
slack 1.301
|
|
|
|
Slack (MET) : 1.301ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_hold_reg[7]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.236ns (logic 0.186ns (15.044%) route 1.050ns (84.956%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.002ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.113ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.590 2.839 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y176 FDCE f usb_inst/range_profile_hold_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.910 2.113 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y176 FDCE r usb_inst/range_profile_hold_reg[7]/C
|
|
clock pessimism -0.508 1.605
|
|
SLICE_X2Y176 FDCE (Remov_fdce_C_CLR) -0.067 1.538 usb_inst/range_profile_hold_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.538
|
|
arrival time 2.839
|
|
-------------------------------------------------------------------
|
|
slack 1.301
|
|
|
|
Slack (MET) : 1.306ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[31]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.330ns (logic 0.186ns (13.986%) route 1.144ns (86.014%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.024ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.111ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.683 2.933 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y176 FDCE f usb_inst/ft601_data_out_reg[31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.908 2.111 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y176 FDCE r usb_inst/ft601_data_out_reg[31]/C
|
|
clock pessimism -0.484 1.627
|
|
OLOGIC_X0Y176 FDCE (Remov_fdce_C_CLR) 0.000 1.627 usb_inst/ft601_data_out_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time -1.627
|
|
arrival time 2.933
|
|
-------------------------------------------------------------------
|
|
slack 1.306
|
|
|
|
Slack (MET) : 1.308ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.225ns (logic 0.186ns (15.188%) route 1.039ns (84.812%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.009ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.120ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.578 2.828 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y182 FDCE f usb_inst/cmd_opcode_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.917 2.120 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y182 FDCE r usb_inst/cmd_opcode_reg[0]/C
|
|
clock pessimism -0.508 1.612
|
|
SLICE_X0Y182 FDCE (Remov_fdce_C_CLR) -0.092 1.520 usb_inst/cmd_opcode_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.520
|
|
arrival time 2.828
|
|
-------------------------------------------------------------------
|
|
slack 1.308
|
|
|
|
Slack (MET) : 1.313ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[5]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.251ns (logic 0.186ns (14.866%) route 1.065ns (85.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.605 2.854 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y178 FDCE f usb_inst/doppler_imag_cap_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_imag_cap_reg[5]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X2Y178 FDCE (Remov_fdce_C_CLR) -0.067 1.541 usb_inst/doppler_imag_cap_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -1.541
|
|
arrival time 2.854
|
|
-------------------------------------------------------------------
|
|
slack 1.313
|
|
|
|
Slack (MET) : 1.313ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.251ns (logic 0.186ns (14.866%) route 1.065ns (85.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.605 2.854 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y178 FDCE f usb_inst/doppler_real_cap_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_real_cap_reg[1]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X2Y178 FDCE (Remov_fdce_C_CLR) -0.067 1.541 usb_inst/doppler_real_cap_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.541
|
|
arrival time 2.854
|
|
-------------------------------------------------------------------
|
|
slack 1.313
|
|
|
|
Slack (MET) : 1.313ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[4]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.251ns (logic 0.186ns (14.866%) route 1.065ns (85.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.605 2.854 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y178 FDCE f usb_inst/doppler_real_cap_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_real_cap_reg[4]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X2Y178 FDCE (Remov_fdce_C_CLR) -0.067 1.541 usb_inst/doppler_real_cap_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.541
|
|
arrival time 2.854
|
|
-------------------------------------------------------------------
|
|
slack 1.313
|
|
|
|
Slack (MET) : 1.313ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[5]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.251ns (logic 0.186ns (14.866%) route 1.065ns (85.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.605 2.854 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y178 FDCE f usb_inst/doppler_real_cap_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y178 FDCE r usb_inst/doppler_real_cap_reg[5]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X2Y178 FDCE (Remov_fdce_C_CLR) -0.067 1.541 usb_inst/doppler_real_cap_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -1.541
|
|
arrival time 2.854
|
|
-------------------------------------------------------------------
|
|
slack 1.313
|
|
|
|
Slack (MET) : 1.329ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_valid_sync_d_reg/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.263ns (logic 0.186ns (14.724%) route 1.077ns (85.276%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.001ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.617 2.866 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y175 FDCE f usb_inst/doppler_valid_sync_d_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y175 FDCE r usb_inst/doppler_valid_sync_d_reg/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X2Y175 FDCE (Remov_fdce_C_CLR) -0.067 1.537 usb_inst/doppler_valid_sync_d_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.537
|
|
arrival time 2.866
|
|
-------------------------------------------------------------------
|
|
slack 1.329
|
|
|
|
Slack (MET) : 1.329ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_valid_sync_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.263ns (logic 0.186ns (14.724%) route 1.077ns (85.276%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.001ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.617 2.866 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y175 FDCE f usb_inst/doppler_valid_sync_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y175 FDCE r usb_inst/doppler_valid_sync_reg[0]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X2Y175 FDCE (Remov_fdce_C_CLR) -0.067 1.537 usb_inst/doppler_valid_sync_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.537
|
|
arrival time 2.866
|
|
-------------------------------------------------------------------
|
|
slack 1.329
|
|
|
|
Slack (MET) : 1.329ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_valid_sync_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.263ns (logic 0.186ns (14.724%) route 1.077ns (85.276%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.001ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.617 2.866 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y175 FDCE f usb_inst/doppler_valid_sync_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y175 FDCE r usb_inst/doppler_valid_sync_reg[1]/C
|
|
clock pessimism -0.508 1.604
|
|
SLICE_X2Y175 FDCE (Remov_fdce_C_CLR) -0.067 1.537 usb_inst/doppler_valid_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.537
|
|
arrival time 2.866
|
|
-------------------------------------------------------------------
|
|
slack 1.329
|
|
|
|
Slack (MET) : 1.336ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[12]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y181 FDCE f usb_inst/range_profile_cap_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y181 FDCE r usb_inst/range_profile_cap_reg[12]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X2Y181 FDCE (Remov_fdce_C_CLR) -0.067 1.544 usb_inst/range_profile_cap_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time -1.544
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.336
|
|
|
|
Slack (MET) : 1.336ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[20]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y181 FDCE f usb_inst/range_profile_cap_reg[20]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y181 FDCE r usb_inst/range_profile_cap_reg[20]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X2Y181 FDCE (Remov_fdce_C_CLR) -0.067 1.544 usb_inst/range_profile_cap_reg[20]
|
|
-------------------------------------------------------------------
|
|
required time -1.544
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.336
|
|
|
|
Slack (MET) : 1.336ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[28]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X2Y181 FDCE f usb_inst/range_profile_cap_reg[28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X2Y181 FDCE r usb_inst/range_profile_cap_reg[28]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X2Y181 FDCE (Remov_fdce_C_CLR) -0.067 1.544 usb_inst/range_profile_cap_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time -1.544
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.336
|
|
|
|
Slack (MET) : 1.338ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[11]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.251ns (logic 0.186ns (14.866%) route 1.065ns (85.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.605 2.854 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y178 FDCE f usb_inst/range_profile_cap_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y178 FDCE r usb_inst/range_profile_cap_reg[11]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X3Y178 FDCE (Remov_fdce_C_CLR) -0.092 1.516 usb_inst/range_profile_cap_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -1.516
|
|
arrival time 2.854
|
|
-------------------------------------------------------------------
|
|
slack 1.338
|
|
|
|
Slack (MET) : 1.338ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[19]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.251ns (logic 0.186ns (14.866%) route 1.065ns (85.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.605 2.854 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y178 FDCE f usb_inst/range_profile_cap_reg[19]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y178 FDCE r usb_inst/range_profile_cap_reg[19]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X3Y178 FDCE (Remov_fdce_C_CLR) -0.092 1.516 usb_inst/range_profile_cap_reg[19]
|
|
-------------------------------------------------------------------
|
|
required time -1.516
|
|
arrival time 2.854
|
|
-------------------------------------------------------------------
|
|
slack 1.338
|
|
|
|
Slack (MET) : 1.338ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.251ns (logic 0.186ns (14.866%) route 1.065ns (85.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.605 2.854 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y178 FDCE f usb_inst/range_profile_cap_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y178 FDCE r usb_inst/range_profile_cap_reg[1]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X3Y178 FDCE (Remov_fdce_C_CLR) -0.092 1.516 usb_inst/range_profile_cap_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.516
|
|
arrival time 2.854
|
|
-------------------------------------------------------------------
|
|
slack 1.338
|
|
|
|
Slack (MET) : 1.338ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[25]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.251ns (logic 0.186ns (14.866%) route 1.065ns (85.134%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.605 2.854 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y178 FDCE f usb_inst/range_profile_cap_reg[25]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y178 FDCE r usb_inst/range_profile_cap_reg[25]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X3Y178 FDCE (Remov_fdce_C_CLR) -0.092 1.516 usb_inst/range_profile_cap_reg[25]
|
|
-------------------------------------------------------------------
|
|
required time -1.516
|
|
arrival time 2.854
|
|
-------------------------------------------------------------------
|
|
slack 1.338
|
|
|
|
Slack (MET) : 1.346ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.259ns (logic 0.186ns (14.770%) route 1.073ns (85.230%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.613 2.862 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y178 FDCE f usb_inst/doppler_imag_cap_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y178 FDCE r usb_inst/doppler_imag_cap_reg[1]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X1Y178 FDCE (Remov_fdce_C_CLR) -0.092 1.516 usb_inst/doppler_imag_cap_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.516
|
|
arrival time 2.862
|
|
-------------------------------------------------------------------
|
|
slack 1.346
|
|
|
|
Slack (MET) : 1.346ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_cap_reg[3]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.259ns (logic 0.186ns (14.770%) route 1.073ns (85.230%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.613 2.862 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y178 FDCE f usb_inst/doppler_real_cap_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y178 FDCE r usb_inst/doppler_real_cap_reg[3]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X1Y178 FDCE (Remov_fdce_C_CLR) -0.092 1.516 usb_inst/doppler_real_cap_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.516
|
|
arrival time 2.862
|
|
-------------------------------------------------------------------
|
|
slack 1.346
|
|
|
|
Slack (MET) : 1.350ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/range_profile_cap_reg[4]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.263ns (logic 0.186ns (14.727%) route 1.077ns (85.273%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.005ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.116ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.617 2.866 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y178 FDCE f usb_inst/range_profile_cap_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.913 2.116 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y178 FDCE r usb_inst/range_profile_cap_reg[4]/C
|
|
clock pessimism -0.508 1.608
|
|
SLICE_X0Y178 FDCE (Remov_fdce_C_CLR) -0.092 1.516 usb_inst/range_profile_cap_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.516
|
|
arrival time 2.866
|
|
-------------------------------------------------------------------
|
|
slack 1.350
|
|
|
|
Slack (MET) : 1.353ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[4]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.265ns (logic 0.186ns (14.701%) route 1.079ns (85.299%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.619 2.868 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y177 FDCE f usb_inst/doppler_imag_cap_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y177 FDCE r usb_inst/doppler_imag_cap_reg[4]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X1Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_cap_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.868
|
|
-------------------------------------------------------------------
|
|
slack 1.353
|
|
|
|
Slack (MET) : 1.353ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[6]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.265ns (logic 0.186ns (14.701%) route 1.079ns (85.299%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.619 2.868 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y177 FDCE f usb_inst/doppler_imag_cap_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y177 FDCE r usb_inst/doppler_imag_cap_reg[6]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X1Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_cap_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.868
|
|
-------------------------------------------------------------------
|
|
slack 1.353
|
|
|
|
Slack (MET) : 1.353ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_cap_reg[7]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.265ns (logic 0.186ns (14.701%) route 1.079ns (85.299%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.619 2.868 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y177 FDCE f usb_inst/doppler_imag_cap_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y177 FDCE r usb_inst/doppler_imag_cap_reg[7]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X1Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_cap_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.868
|
|
-------------------------------------------------------------------
|
|
slack 1.353
|
|
|
|
Slack (MET) : 1.355ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/ft601_data_out_reg[30]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.379ns (logic 0.186ns (13.490%) route 1.193ns (86.510%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.024ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.111ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.732 2.982 usb_inst/por_counter_reg[15]
|
|
OLOGIC_X0Y175 FDCE f usb_inst/ft601_data_out_reg[30]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.908 2.111 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y175 FDCE r usb_inst/ft601_data_out_reg[30]/C
|
|
clock pessimism -0.484 1.627
|
|
OLOGIC_X0Y175 FDCE (Remov_fdce_C_CLR) 0.000 1.627 usb_inst/ft601_data_out_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time -1.627
|
|
arrival time 2.982
|
|
-------------------------------------------------------------------
|
|
slack 1.355
|
|
|
|
Slack (MET) : 1.357ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.269ns (logic 0.186ns (14.658%) route 1.083ns (85.342%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.622 2.872 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y177 FDCE f usb_inst/doppler_imag_hold_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[0]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_hold_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.872
|
|
-------------------------------------------------------------------
|
|
slack 1.357
|
|
|
|
Slack (MET) : 1.357ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[11]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.269ns (logic 0.186ns (14.658%) route 1.083ns (85.342%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.622 2.872 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y177 FDCE f usb_inst/doppler_imag_hold_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[11]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_hold_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.872
|
|
-------------------------------------------------------------------
|
|
slack 1.357
|
|
|
|
Slack (MET) : 1.357ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.269ns (logic 0.186ns (14.658%) route 1.083ns (85.342%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.622 2.872 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y177 FDCE f usb_inst/doppler_imag_hold_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[1]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_hold_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.872
|
|
-------------------------------------------------------------------
|
|
slack 1.357
|
|
|
|
Slack (MET) : 1.357ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[2]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.269ns (logic 0.186ns (14.658%) route 1.083ns (85.342%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.622 2.872 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y177 FDCE f usb_inst/doppler_imag_hold_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[2]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_hold_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.872
|
|
-------------------------------------------------------------------
|
|
slack 1.357
|
|
|
|
Slack (MET) : 1.357ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[4]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.269ns (logic 0.186ns (14.658%) route 1.083ns (85.342%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.622 2.872 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y177 FDCE f usb_inst/doppler_imag_hold_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[4]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_hold_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.872
|
|
-------------------------------------------------------------------
|
|
slack 1.357
|
|
|
|
Slack (MET) : 1.357ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[5]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.269ns (logic 0.186ns (14.658%) route 1.083ns (85.342%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.622 2.872 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y177 FDCE f usb_inst/doppler_imag_hold_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[5]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_hold_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.872
|
|
-------------------------------------------------------------------
|
|
slack 1.357
|
|
|
|
Slack (MET) : 1.357ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[6]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.269ns (logic 0.186ns (14.658%) route 1.083ns (85.342%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.622 2.872 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y177 FDCE f usb_inst/doppler_imag_hold_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[6]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_hold_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.872
|
|
-------------------------------------------------------------------
|
|
slack 1.357
|
|
|
|
Slack (MET) : 1.357ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_imag_hold_reg[7]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.269ns (logic 0.186ns (14.658%) route 1.083ns (85.342%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.004ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.115ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.622 2.872 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y177 FDCE f usb_inst/doppler_imag_hold_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.912 2.115 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y177 FDCE r usb_inst/doppler_imag_hold_reg[7]/C
|
|
clock pessimism -0.508 1.607
|
|
SLICE_X0Y177 FDCE (Remov_fdce_C_CLR) -0.092 1.515 usb_inst/doppler_imag_hold_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.515
|
|
arrival time 2.872
|
|
-------------------------------------------------------------------
|
|
slack 1.357
|
|
|
|
Slack (MET) : 1.361ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[10]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y181 FDCE f usb_inst/doppler_real_hold_reg[10]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[10]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X3Y181 FDCE (Remov_fdce_C_CLR) -0.092 1.519 usb_inst/doppler_real_hold_reg[10]
|
|
-------------------------------------------------------------------
|
|
required time -1.519
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.361
|
|
|
|
Slack (MET) : 1.361ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[11]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y181 FDCE f usb_inst/doppler_real_hold_reg[11]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[11]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X3Y181 FDCE (Remov_fdce_C_CLR) -0.092 1.519 usb_inst/doppler_real_hold_reg[11]
|
|
-------------------------------------------------------------------
|
|
required time -1.519
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.361
|
|
|
|
Slack (MET) : 1.361ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[12]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y181 FDCE f usb_inst/doppler_real_hold_reg[12]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[12]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X3Y181 FDCE (Remov_fdce_C_CLR) -0.092 1.519 usb_inst/doppler_real_hold_reg[12]
|
|
-------------------------------------------------------------------
|
|
required time -1.519
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.361
|
|
|
|
Slack (MET) : 1.361ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[13]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y181 FDCE f usb_inst/doppler_real_hold_reg[13]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[13]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X3Y181 FDCE (Remov_fdce_C_CLR) -0.092 1.519 usb_inst/doppler_real_hold_reg[13]
|
|
-------------------------------------------------------------------
|
|
required time -1.519
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.361
|
|
|
|
Slack (MET) : 1.361ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[14]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y181 FDCE f usb_inst/doppler_real_hold_reg[14]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[14]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X3Y181 FDCE (Remov_fdce_C_CLR) -0.092 1.519 usb_inst/doppler_real_hold_reg[14]
|
|
-------------------------------------------------------------------
|
|
required time -1.519
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.361
|
|
|
|
Slack (MET) : 1.361ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[15]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y181 FDCE f usb_inst/doppler_real_hold_reg[15]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[15]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X3Y181 FDCE (Remov_fdce_C_CLR) -0.092 1.519 usb_inst/doppler_real_hold_reg[15]
|
|
-------------------------------------------------------------------
|
|
required time -1.519
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.361
|
|
|
|
Slack (MET) : 1.361ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[7]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y181 FDCE f usb_inst/doppler_real_hold_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[7]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X3Y181 FDCE (Remov_fdce_C_CLR) -0.092 1.519 usb_inst/doppler_real_hold_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.519
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.361
|
|
|
|
Slack (MET) : 1.361ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/doppler_real_hold_reg[8]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.277ns (logic 0.186ns (14.567%) route 1.091ns (85.433%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.008ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.119ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.630 2.880 usb_inst/por_counter_reg[15]
|
|
SLICE_X3Y181 FDCE f usb_inst/doppler_real_hold_reg[8]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.916 2.119 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X3Y181 FDCE r usb_inst/doppler_real_hold_reg[8]/C
|
|
clock pessimism -0.508 1.611
|
|
SLICE_X3Y181 FDCE (Remov_fdce_C_CLR) -0.092 1.519 usb_inst/doppler_real_hold_reg[8]
|
|
-------------------------------------------------------------------
|
|
required time -1.519
|
|
arrival time 2.880
|
|
-------------------------------------------------------------------
|
|
slack 1.361
|
|
|
|
Slack (MET) : 1.364ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[2]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.297ns (logic 0.186ns (14.338%) route 1.111ns (85.662%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.651 2.900 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y174 FDCE f usb_inst/cmd_opcode_reg[2]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[2]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X1Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/cmd_opcode_reg[2]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.900
|
|
-------------------------------------------------------------------
|
|
slack 1.364
|
|
|
|
Slack (MET) : 1.364ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[3]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.297ns (logic 0.186ns (14.338%) route 1.111ns (85.662%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.651 2.900 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y174 FDCE f usb_inst/cmd_opcode_reg[3]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[3]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X1Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/cmd_opcode_reg[3]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.900
|
|
-------------------------------------------------------------------
|
|
slack 1.364
|
|
|
|
Slack (MET) : 1.364ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[4]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.297ns (logic 0.186ns (14.338%) route 1.111ns (85.662%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.651 2.900 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y174 FDCE f usb_inst/cmd_opcode_reg[4]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[4]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X1Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/cmd_opcode_reg[4]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.900
|
|
-------------------------------------------------------------------
|
|
slack 1.364
|
|
|
|
Slack (MET) : 1.364ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[5]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.297ns (logic 0.186ns (14.338%) route 1.111ns (85.662%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.651 2.900 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y174 FDCE f usb_inst/cmd_opcode_reg[5]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[5]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X1Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/cmd_opcode_reg[5]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.900
|
|
-------------------------------------------------------------------
|
|
slack 1.364
|
|
|
|
Slack (MET) : 1.364ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[6]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.297ns (logic 0.186ns (14.338%) route 1.111ns (85.662%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.651 2.900 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y174 FDCE f usb_inst/cmd_opcode_reg[6]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[6]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X1Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/cmd_opcode_reg[6]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.900
|
|
-------------------------------------------------------------------
|
|
slack 1.364
|
|
|
|
Slack (MET) : 1.364ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_opcode_reg[7]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.297ns (logic 0.186ns (14.338%) route 1.111ns (85.662%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.651 2.900 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y174 FDCE f usb_inst/cmd_opcode_reg[7]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_opcode_reg[7]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X1Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/cmd_opcode_reg[7]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.900
|
|
-------------------------------------------------------------------
|
|
slack 1.364
|
|
|
|
Slack (MET) : 1.364ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cmd_value_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.297ns (logic 0.186ns (14.338%) route 1.111ns (85.662%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.651 2.900 usb_inst/por_counter_reg[15]
|
|
SLICE_X1Y174 FDCE f usb_inst/cmd_value_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X1Y174 FDCE r usb_inst/cmd_value_reg[1]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X1Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/cmd_value_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.900
|
|
-------------------------------------------------------------------
|
|
slack 1.364
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/cfar_data_pending_reg/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.286ns (logic 0.186ns (14.464%) route 1.100ns (85.536%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.121ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.639 2.889 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y183 FDCE f usb_inst/cfar_data_pending_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.918 2.121 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y183 FDCE r usb_inst/cfar_data_pending_reg/C
|
|
clock pessimism -0.508 1.613
|
|
SLICE_X0Y183 FDCE (Remov_fdce_C_CLR) -0.092 1.521 usb_inst/cfar_data_pending_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.521
|
|
arrival time 2.889
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/status_req_sync_reg[0]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.286ns (logic 0.186ns (14.464%) route 1.100ns (85.536%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.121ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.639 2.889 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y183 FDCE f usb_inst/status_req_sync_reg[0]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.918 2.121 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y183 FDCE r usb_inst/status_req_sync_reg[0]/C
|
|
clock pessimism -0.508 1.613
|
|
SLICE_X0Y183 FDCE (Remov_fdce_C_CLR) -0.092 1.521 usb_inst/status_req_sync_reg[0]
|
|
-------------------------------------------------------------------
|
|
required time -1.521
|
|
arrival time 2.889
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/status_req_sync_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.286ns (logic 0.186ns (14.464%) route 1.100ns (85.536%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.121ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.639 2.889 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y183 FDCE f usb_inst/status_req_sync_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.918 2.121 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y183 FDCE r usb_inst/status_req_sync_reg[1]/C
|
|
clock pessimism -0.508 1.613
|
|
SLICE_X0Y183 FDCE (Remov_fdce_C_CLR) -0.092 1.521 usb_inst/status_req_sync_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.521
|
|
arrival time 2.889
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/status_req_toggle_100m_reg/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.286ns (logic 0.186ns (14.464%) route 1.100ns (85.536%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.010ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.121ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.508ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.639 2.889 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y183 FDCE f usb_inst/status_req_toggle_100m_reg/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.918 2.121 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y183 FDCE r usb_inst/status_req_toggle_100m_reg/C
|
|
clock pessimism -0.508 1.613
|
|
SLICE_X0Y183 FDCE (Remov_fdce_C_CLR) -0.092 1.521 usb_inst/status_req_toggle_100m_reg
|
|
-------------------------------------------------------------------
|
|
required time -1.521
|
|
arrival time 2.889
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[1]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.301ns (logic 0.186ns (14.297%) route 1.115ns (85.703%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.654 2.904 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y174 FDCE f usb_inst/rx_data_captured_reg[1]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[1]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X0Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/rx_data_captured_reg[1]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.904
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[26]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.301ns (logic 0.186ns (14.297%) route 1.115ns (85.703%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.654 2.904 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y174 FDCE f usb_inst/rx_data_captured_reg[26]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[26]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X0Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/rx_data_captured_reg[26]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.904
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[27]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.301ns (logic 0.186ns (14.297%) route 1.115ns (85.703%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.654 2.904 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y174 FDCE f usb_inst/rx_data_captured_reg[27]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[27]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X0Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/rx_data_captured_reg[27]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.904
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[28]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.301ns (logic 0.186ns (14.297%) route 1.115ns (85.703%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.654 2.904 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y174 FDCE f usb_inst/rx_data_captured_reg[28]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[28]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X0Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/rx_data_captured_reg[28]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.904
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[29]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.301ns (logic 0.186ns (14.297%) route 1.115ns (85.703%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.654 2.904 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y174 FDCE f usb_inst/rx_data_captured_reg[29]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[29]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X0Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/rx_data_captured_reg[29]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.904
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[30]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.301ns (logic 0.186ns (14.297%) route 1.115ns (85.703%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.654 2.904 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y174 FDCE f usb_inst/rx_data_captured_reg[30]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[30]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X0Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/rx_data_captured_reg[30]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.904
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
Slack (MET) : 1.368ns (arrival time - required time)
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: usb_inst/rx_data_captured_reg[31]/CLR
|
|
(removal check against rising-edge clock ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Path Group: **async_default**
|
|
Path Type: Removal (Min at Fast Process Corner)
|
|
Requirement: 0.000ns (ft601_clk_in rise@0.000ns - ft601_clk_in rise@0.000ns)
|
|
Data Path Delay: 1.301ns (logic 0.186ns (14.297%) route 1.115ns (85.703%))
|
|
Logic Levels: 1 (LUT1=1)
|
|
Clock Path Skew: 0.025ns (DCD - SCD - CPR)
|
|
Destination Clock Delay (DCD): 2.112ns
|
|
Source Clock Delay (SCD): 1.603ns
|
|
Clock Pessimism Removal (CPR): 0.484ns
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.461 2.204 usb_inst/ft601_gpio1_OBUF
|
|
SLICE_X0Y181 LUT1 (Prop_lut1_I0_O) 0.045 2.249 f usb_inst/FSM_sequential_current_state[2]_i_2/O
|
|
net (fo=363, routed) 0.654 2.904 usb_inst/por_counter_reg[15]
|
|
SLICE_X0Y174 FDCE f usb_inst/rx_data_captured_reg[31]/CLR
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.425 0.425 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.750 1.175 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.029 1.204 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.909 2.112 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y174 FDCE r usb_inst/rx_data_captured_reg[31]/C
|
|
clock pessimism -0.484 1.628
|
|
SLICE_X0Y174 FDCE (Remov_fdce_C_CLR) -0.092 1.536 usb_inst/rx_data_captured_reg[31]
|
|
-------------------------------------------------------------------
|
|
required time -1.536
|
|
arrival time 2.904
|
|
-------------------------------------------------------------------
|
|
slack 1.368
|
|
|
|
|
|
|
|
|
|
|
|
---------------------------------------------------------------------------------------------------
|
|
Path Group: **default**
|
|
From Clock: ft601_clk_in
|
|
To Clock:
|
|
|
|
Setup : 0 Failing Endpoints, Worst Slack 0.470ns, Total Violation 0.000ns
|
|
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
|
|
---------------------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack (MET) : 0.470ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[27]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 7.030ns (logic 3.350ns (47.652%) route 3.680ns (52.348%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 3.680 4.059 ft601_data_IOBUF[27]_inst/T
|
|
N19 OBUFT (TriStatE_obuft_T_O)
|
|
2.971 7.030 r ft601_data_IOBUF[27]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 7.030 ft601_data[27]
|
|
N19 r ft601_data[27] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -7.030
|
|
-------------------------------------------------------------------
|
|
slack 0.470
|
|
|
|
Slack (MET) : 0.569ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[26]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 6.931ns (logic 3.359ns (48.461%) route 3.572ns (51.539%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 3.572 3.951 ft601_data_IOBUF[26]_inst/T
|
|
N18 OBUFT (TriStatE_obuft_T_O)
|
|
2.980 6.931 r ft601_data_IOBUF[26]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 6.931 ft601_data[26]
|
|
N18 r ft601_data[26] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -6.931
|
|
-------------------------------------------------------------------
|
|
slack 0.569
|
|
|
|
Slack (MET) : 0.717ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[21]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 6.783ns (logic 3.327ns (49.057%) route 3.455ns (50.943%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 3.455 3.834 ft601_data_TRI[0]
|
|
L18 OBUFT (TriStatE_obuft_T_O)
|
|
2.948 6.783 r ft601_data_OBUFT[21]_inst/O
|
|
net (fo=0) 0.000 6.783 ft601_data[21]
|
|
L18 r ft601_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -6.783
|
|
-------------------------------------------------------------------
|
|
slack 0.717
|
|
|
|
Slack (MET) : 0.801ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[5]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 6.699ns (logic 3.358ns (50.128%) route 3.341ns (49.872%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 3.341 3.720 ft601_data_TRI[0]
|
|
N22 OBUFT (TriStatE_obuft_T_O)
|
|
2.979 6.699 r ft601_data_OBUFT[5]_inst/O
|
|
net (fo=0) 0.000 6.699 ft601_data[5]
|
|
N22 r ft601_data[5] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -6.699
|
|
-------------------------------------------------------------------
|
|
slack 0.801
|
|
|
|
Slack (MET) : 0.821ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[23]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 6.679ns (logic 3.340ns (50.013%) route 3.338ns (49.987%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 3.338 3.717 ft601_data_TRI[0]
|
|
M18 OBUFT (TriStatE_obuft_T_O)
|
|
2.961 6.679 r ft601_data_OBUFT[23]_inst/O
|
|
net (fo=0) 0.000 6.679 ft601_data[23]
|
|
M18 r ft601_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -6.679
|
|
-------------------------------------------------------------------
|
|
slack 0.821
|
|
|
|
Slack (MET) : 0.923ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[7]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 6.577ns (logic 3.355ns (51.016%) route 3.222ns (48.984%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 3.222 3.601 ft601_data_TRI[0]
|
|
M22 OBUFT (TriStatE_obuft_T_O)
|
|
2.976 6.577 r ft601_data_OBUFT[7]_inst/O
|
|
net (fo=0) 0.000 6.577 ft601_data[7]
|
|
M22 r ft601_data[7] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -6.577
|
|
-------------------------------------------------------------------
|
|
slack 0.923
|
|
|
|
Slack (MET) : 1.170ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[30]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 6.330ns (logic 3.328ns (52.579%) route 3.002ns (47.421%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 3.002 3.381 ft601_data_IOBUF[30]_inst/T
|
|
H19 OBUFT (TriStatE_obuft_T_O)
|
|
2.949 6.330 r ft601_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 6.330 ft601_data[30]
|
|
H19 r ft601_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -6.330
|
|
-------------------------------------------------------------------
|
|
slack 1.170
|
|
|
|
Slack (MET) : 1.280ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[31]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 6.220ns (logic 3.326ns (53.476%) route 2.894ns (46.524%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.894 3.273 ft601_data_IOBUF[31]_inst/T
|
|
J19 OBUFT (TriStatE_obuft_T_O)
|
|
2.947 6.220 r ft601_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 6.220 ft601_data[31]
|
|
J19 r ft601_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -6.220
|
|
-------------------------------------------------------------------
|
|
slack 1.280
|
|
|
|
Slack (MET) : 1.502ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[0]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.998ns (logic 3.351ns (55.872%) route 2.647ns (44.128%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.647 3.026 ft601_data_IOBUF[0]_inst/T
|
|
L21 OBUFT (TriStatE_obuft_T_O)
|
|
2.972 5.998 r ft601_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 5.998 ft601_data[0]
|
|
L21 r ft601_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.998
|
|
-------------------------------------------------------------------
|
|
slack 1.502
|
|
|
|
Slack (MET) : 1.616ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[2]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.884ns (logic 3.354ns (57.001%) route 2.530ns (42.999%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.530 2.909 ft601_data_IOBUF[2]_inst/T
|
|
M21 OBUFT (TriStatE_obuft_T_O)
|
|
2.975 5.884 r ft601_data_IOBUF[2]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 5.884 ft601_data[2]
|
|
M21 r ft601_data[2] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.884
|
|
-------------------------------------------------------------------
|
|
slack 1.616
|
|
|
|
Slack (MET) : 1.754ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[9]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.746ns (logic 3.327ns (57.902%) route 2.419ns (42.098%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.419 2.798 ft601_data_TRI[0]
|
|
K17 OBUFT (TriStatE_obuft_T_O)
|
|
2.948 5.746 r ft601_data_OBUFT[9]_inst/O
|
|
net (fo=0) 0.000 5.746 ft601_data[9]
|
|
K17 r ft601_data[9] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.746
|
|
-------------------------------------------------------------------
|
|
slack 1.754
|
|
|
|
Slack (MET) : 1.827ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[8]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.673ns (logic 3.327ns (58.639%) route 2.347ns (41.361%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.347 2.726 ft601_data_TRI[0]
|
|
H18 OBUFT (TriStatE_obuft_T_O)
|
|
2.948 5.673 r ft601_data_OBUFT[8]_inst/O
|
|
net (fo=0) 0.000 5.673 ft601_data[8]
|
|
H18 r ft601_data[8] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.673
|
|
-------------------------------------------------------------------
|
|
slack 1.827
|
|
|
|
Slack (MET) : 1.855ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[6]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.645ns (logic 3.334ns (59.057%) route 2.311ns (40.943%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.311 2.690 ft601_data_TRI[0]
|
|
L13 OBUFT (TriStatE_obuft_T_O)
|
|
2.955 5.645 r ft601_data_OBUFT[6]_inst/O
|
|
net (fo=0) 0.000 5.645 ft601_data[6]
|
|
L13 r ft601_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.645
|
|
-------------------------------------------------------------------
|
|
slack 1.855
|
|
|
|
Slack (MET) : 1.939ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[10]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.561ns (logic 3.322ns (59.744%) route 2.239ns (40.256%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.239 2.618 ft601_data_TRI[0]
|
|
H17 OBUFT (TriStatE_obuft_T_O)
|
|
2.943 5.561 r ft601_data_OBUFT[10]_inst/O
|
|
net (fo=0) 0.000 5.561 ft601_data[10]
|
|
H17 r ft601_data[10] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.561
|
|
-------------------------------------------------------------------
|
|
slack 1.939
|
|
|
|
Slack (MET) : 1.968ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[4]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.532ns (logic 3.338ns (60.336%) route 2.194ns (39.664%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.194 2.573 ft601_data_TRI[0]
|
|
M13 OBUFT (TriStatE_obuft_T_O)
|
|
2.959 5.532 r ft601_data_OBUFT[4]_inst/O
|
|
net (fo=0) 0.000 5.532 ft601_data[4]
|
|
M13 r ft601_data[4] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.532
|
|
-------------------------------------------------------------------
|
|
slack 1.968
|
|
|
|
Slack (MET) : 1.971ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[11]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.529ns (logic 3.326ns (60.159%) route 2.203ns (39.841%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.203 2.582 ft601_data_TRI[0]
|
|
J17 OBUFT (TriStatE_obuft_T_O)
|
|
2.947 5.529 r ft601_data_OBUFT[11]_inst/O
|
|
net (fo=0) 0.000 5.529 ft601_data[11]
|
|
J17 r ft601_data[11] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.529
|
|
-------------------------------------------------------------------
|
|
slack 1.971
|
|
|
|
Slack (MET) : 2.029ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[29]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.471ns (logic 3.328ns (60.835%) route 2.143ns (39.165%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.143 2.522 ft601_data_IOBUF[29]_inst/T
|
|
K13 OBUFT (TriStatE_obuft_T_O)
|
|
2.949 5.471 r ft601_data_IOBUF[29]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 5.471 ft601_data[29]
|
|
K13 r ft601_data[29] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.471
|
|
-------------------------------------------------------------------
|
|
slack 2.029
|
|
|
|
Slack (MET) : 2.030ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[3]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.470ns (logic 3.338ns (61.014%) route 2.133ns (38.986%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.133 2.512 ft601_data_TRI[0]
|
|
M20 OBUFT (TriStatE_obuft_T_O)
|
|
2.959 5.470 r ft601_data_OBUFT[3]_inst/O
|
|
net (fo=0) 0.000 5.470 ft601_data[3]
|
|
M20 r ft601_data[3] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.470
|
|
-------------------------------------------------------------------
|
|
slack 2.030
|
|
|
|
Slack (MET) : 2.057ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[12]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.443ns (logic 3.316ns (60.925%) route 2.127ns (39.075%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.127 2.506 ft601_data_TRI[0]
|
|
L15 OBUFT (TriStatE_obuft_T_O)
|
|
2.937 5.443 r ft601_data_OBUFT[12]_inst/O
|
|
net (fo=0) 0.000 5.443 ft601_data[12]
|
|
L15 r ft601_data[12] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.443
|
|
-------------------------------------------------------------------
|
|
slack 2.057
|
|
|
|
Slack (MET) : 2.063ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[14]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.437ns (logic 3.317ns (61.009%) route 2.120ns (38.991%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.120 2.499 ft601_data_TRI[0]
|
|
L14 OBUFT (TriStatE_obuft_T_O)
|
|
2.938 5.437 r ft601_data_OBUFT[14]_inst/O
|
|
net (fo=0) 0.000 5.437 ft601_data[14]
|
|
L14 r ft601_data[14] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.437
|
|
-------------------------------------------------------------------
|
|
slack 2.063
|
|
|
|
Slack (MET) : 2.068ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[15]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.432ns (logic 3.310ns (60.940%) route 2.122ns (39.060%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.122 2.501 ft601_data_TRI[0]
|
|
H15 OBUFT (TriStatE_obuft_T_O)
|
|
2.931 5.432 r ft601_data_OBUFT[15]_inst/O
|
|
net (fo=0) 0.000 5.432 ft601_data[15]
|
|
H15 r ft601_data[15] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.432
|
|
-------------------------------------------------------------------
|
|
slack 2.068
|
|
|
|
Slack (MET) : 2.099ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[28]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.401ns (logic 3.324ns (61.538%) route 2.077ns (38.462%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.077 2.456 ft601_data_IOBUF[28]_inst/T
|
|
K14 OBUFT (TriStatE_obuft_T_O)
|
|
2.945 5.401 r ft601_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 5.401 ft601_data[28]
|
|
K14 r ft601_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.401
|
|
-------------------------------------------------------------------
|
|
slack 2.099
|
|
|
|
Slack (MET) : 2.125ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[1]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.375ns (logic 3.351ns (62.336%) route 2.025ns (37.664%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 2.025 2.404 ft601_data_IOBUF[1]_inst/T
|
|
N20 OBUFT (TriStatE_obuft_T_O)
|
|
2.972 5.375 r ft601_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 5.375 ft601_data[1]
|
|
N20 r ft601_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.375
|
|
-------------------------------------------------------------------
|
|
slack 2.125
|
|
|
|
Slack (MET) : 2.191ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[13]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.309ns (logic 3.313ns (62.403%) route 1.996ns (37.597%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.996 2.375 ft601_data_TRI[0]
|
|
J15 OBUFT (TriStatE_obuft_T_O)
|
|
2.934 5.309 r ft601_data_OBUFT[13]_inst/O
|
|
net (fo=0) 0.000 5.309 ft601_data[13]
|
|
J15 r ft601_data[13] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.309
|
|
-------------------------------------------------------------------
|
|
slack 2.191
|
|
|
|
Slack (MET) : 2.293ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[20]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.207ns (logic 3.328ns (63.912%) route 1.879ns (36.088%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.879 2.258 ft601_data_TRI[0]
|
|
G18 OBUFT (TriStatE_obuft_T_O)
|
|
2.949 5.207 r ft601_data_OBUFT[20]_inst/O
|
|
net (fo=0) 0.000 5.207 ft601_data[20]
|
|
G18 r ft601_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.207
|
|
-------------------------------------------------------------------
|
|
slack 2.293
|
|
|
|
Slack (MET) : 2.411ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[18]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.089ns (logic 3.330ns (65.429%) route 1.759ns (34.571%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.759 2.138 ft601_data_TRI[0]
|
|
H13 OBUFT (TriStatE_obuft_T_O)
|
|
2.951 5.089 r ft601_data_OBUFT[18]_inst/O
|
|
net (fo=0) 0.000 5.089 ft601_data[18]
|
|
H13 r ft601_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.089
|
|
-------------------------------------------------------------------
|
|
slack 2.411
|
|
|
|
Slack (MET) : 2.418ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[22]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 5.082ns (logic 3.320ns (65.322%) route 1.762ns (34.678%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.762 2.141 ft601_data_TRI[0]
|
|
G17 OBUFT (TriStatE_obuft_T_O)
|
|
2.941 5.082 r ft601_data_OBUFT[22]_inst/O
|
|
net (fo=0) 0.000 5.082 ft601_data[22]
|
|
G17 r ft601_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -5.082
|
|
-------------------------------------------------------------------
|
|
slack 2.418
|
|
|
|
Slack (MET) : 2.524ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[16]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 4.976ns (logic 3.327ns (66.852%) route 1.649ns (33.148%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.649 2.028 ft601_data_TRI[0]
|
|
G13 OBUFT (TriStatE_obuft_T_O)
|
|
2.948 4.976 r ft601_data_OBUFT[16]_inst/O
|
|
net (fo=0) 0.000 4.976 ft601_data[16]
|
|
G13 r ft601_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -4.976
|
|
-------------------------------------------------------------------
|
|
slack 2.524
|
|
|
|
Slack (MET) : 2.537ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[24]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 4.963ns (logic 3.317ns (66.845%) route 1.645ns (33.155%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.645 2.024 ft601_data_IOBUF[24]_inst/T
|
|
H14 OBUFT (TriStatE_obuft_T_O)
|
|
2.938 4.963 r ft601_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 4.963 ft601_data[24]
|
|
H14 r ft601_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -4.963
|
|
-------------------------------------------------------------------
|
|
slack 2.537
|
|
|
|
Slack (MET) : 2.648ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[25]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 4.852ns (logic 3.324ns (68.497%) route 1.529ns (31.503%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.529 1.908 ft601_data_IOBUF[25]_inst/T
|
|
J14 OBUFT (TriStatE_obuft_T_O)
|
|
2.945 4.852 r ft601_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 4.852 ft601_data[25]
|
|
J14 r ft601_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -4.852
|
|
-------------------------------------------------------------------
|
|
slack 2.648
|
|
|
|
Slack (MET) : 2.651ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[17]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 4.849ns (logic 3.319ns (68.436%) route 1.531ns (31.564%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.531 1.910 ft601_data_TRI[0]
|
|
G15 OBUFT (TriStatE_obuft_T_O)
|
|
2.940 4.849 r ft601_data_OBUFT[17]_inst/O
|
|
net (fo=0) 0.000 4.849 ft601_data[17]
|
|
G15 r ft601_data[17] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -4.849
|
|
-------------------------------------------------------------------
|
|
slack 2.651
|
|
|
|
Slack (MET) : 2.770ns (required time - arrival time)
|
|
Source: usb_inst/ft601_data_oe_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[19]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 4.730ns (logic 3.319ns (70.156%) route 1.412ns (29.844%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y195 0.000 0.000 r usb_inst/ft601_data_oe_reg/C
|
|
SLICE_X0Y195 FDPE (Prop_fdpe_C_Q) 0.379 0.379 f usb_inst/ft601_data_oe_reg/Q
|
|
net (fo=33, routed) 1.412 1.791 ft601_data_TRI[0]
|
|
G16 OBUFT (TriStatE_obuft_T_O)
|
|
2.940 4.730 r ft601_data_OBUFT[19]_inst/O
|
|
net (fo=0) 0.000 4.730 ft601_data[19]
|
|
G16 r ft601_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -4.730
|
|
-------------------------------------------------------------------
|
|
slack 2.770
|
|
|
|
Slack (MET) : 4.131ns (required time - arrival time)
|
|
Source: usb_inst/ft601_be_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_be[1]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 3.369ns (logic 3.368ns (99.970%) route 0.001ns (0.030%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y217 0.000 0.000 r usb_inst/ft601_be_reg[1]/C
|
|
OLOGIC_X0Y217 FDPE (Prop_fdpe_C_Q) 0.418 0.418 r usb_inst/ft601_be_reg[1]/Q
|
|
net (fo=1, routed) 0.001 0.419 ft601_be_OBUF[1]
|
|
A20 OBUF (Prop_obuf_I_O) 2.950 3.369 r ft601_be_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 3.369 ft601_be[1]
|
|
A20 r ft601_be[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -3.369
|
|
-------------------------------------------------------------------
|
|
slack 4.131
|
|
|
|
Slack (MET) : 4.133ns (required time - arrival time)
|
|
Source: usb_inst/ft601_be_reg[0]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_be[0]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 3.367ns (logic 3.366ns (99.970%) route 0.001ns (0.030%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y218 0.000 0.000 r usb_inst/ft601_be_reg[0]/C
|
|
OLOGIC_X0Y218 FDPE (Prop_fdpe_C_Q) 0.418 0.418 r usb_inst/ft601_be_reg[0]/Q
|
|
net (fo=1, routed) 0.001 0.419 ft601_be_OBUF[0]
|
|
B20 OBUF (Prop_obuf_I_O) 2.948 3.367 r ft601_be_OBUF[0]_inst/O
|
|
net (fo=0) 0.000 3.367 ft601_be[0]
|
|
B20 r ft601_be[0] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -3.367
|
|
-------------------------------------------------------------------
|
|
slack 4.133
|
|
|
|
Slack (MET) : 4.151ns (required time - arrival time)
|
|
Source: usb_inst/ft601_oe_n_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_oe_n
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 3.349ns (logic 3.348ns (99.970%) route 0.001ns (0.030%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y225 0.000 0.000 r usb_inst/ft601_oe_n_reg/C
|
|
OLOGIC_X0Y225 FDPE (Prop_fdpe_C_Q) 0.418 0.418 r usb_inst/ft601_oe_n_reg/Q
|
|
net (fo=1, routed) 0.001 0.419 ft601_oe_n_OBUF
|
|
C17 OBUF (Prop_obuf_I_O) 2.930 3.349 r ft601_oe_n_OBUF_inst/O
|
|
net (fo=0) 0.000 3.349 ft601_oe_n
|
|
C17 r ft601_oe_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -3.349
|
|
-------------------------------------------------------------------
|
|
slack 4.151
|
|
|
|
Slack (MET) : 4.153ns (required time - arrival time)
|
|
Source: usb_inst/ft601_rd_n_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_rd_n
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 3.347ns (logic 3.346ns (99.970%) route 0.001ns (0.030%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y226 0.000 0.000 r usb_inst/ft601_rd_n_reg/C
|
|
OLOGIC_X0Y226 FDPE (Prop_fdpe_C_Q) 0.418 0.418 r usb_inst/ft601_rd_n_reg/Q
|
|
net (fo=1, routed) 0.001 0.419 ft601_rd_n_OBUF
|
|
D17 OBUF (Prop_obuf_I_O) 2.928 3.347 r ft601_rd_n_OBUF_inst/O
|
|
net (fo=0) 0.000 3.347 ft601_rd_n
|
|
D17 r ft601_rd_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -3.347
|
|
-------------------------------------------------------------------
|
|
slack 4.153
|
|
|
|
Slack (MET) : 4.156ns (required time - arrival time)
|
|
Source: usb_inst/ft601_wr_n_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_wr_n
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 3.344ns (logic 3.343ns (99.970%) route 0.001ns (0.030%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y242 0.000 0.000 r usb_inst/ft601_wr_n_reg/C
|
|
OLOGIC_X0Y242 FDPE (Prop_fdpe_C_Q) 0.418 0.418 r usb_inst/ft601_wr_n_reg/Q
|
|
net (fo=1, routed) 0.001 0.419 ft601_wr_n_OBUF
|
|
E13 OBUF (Prop_obuf_I_O) 2.925 3.344 r ft601_wr_n_OBUF_inst/O
|
|
net (fo=0) 0.000 3.344 ft601_wr_n
|
|
E13 r ft601_wr_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -3.344
|
|
-------------------------------------------------------------------
|
|
slack 4.156
|
|
|
|
Slack (MET) : 4.173ns (required time - arrival time)
|
|
Source: usb_inst/ft601_be_reg[2]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_be[2]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 3.327ns (logic 3.326ns (99.970%) route 0.001ns (0.030%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y239 0.000 0.000 r usb_inst/ft601_be_reg[2]/C
|
|
OLOGIC_X0Y239 FDPE (Prop_fdpe_C_Q) 0.418 0.418 r usb_inst/ft601_be_reg[2]/Q
|
|
net (fo=1, routed) 0.001 0.419 ft601_be_OBUF[2]
|
|
D16 OBUF (Prop_obuf_I_O) 2.908 3.327 r ft601_be_OBUF[2]_inst/O
|
|
net (fo=0) 0.000 3.327 ft601_be[2]
|
|
D16 r ft601_be[2] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -3.327
|
|
-------------------------------------------------------------------
|
|
slack 4.173
|
|
|
|
Slack (MET) : 4.175ns (required time - arrival time)
|
|
Source: usb_inst/ft601_be_reg[3]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_be[3]
|
|
Path Group: **default**
|
|
Path Type: Max at Slow Process Corner
|
|
Requirement: 7.500ns (MaxDelay Path 7.500ns)
|
|
Data Path Delay: 3.325ns (logic 3.324ns (99.970%) route 0.001ns (0.030%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Output Delay: 0.000ns
|
|
Timing Exception: MaxDelay Path 7.500ns -datapath_only
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y240 0.000 0.000 r usb_inst/ft601_be_reg[3]/C
|
|
OLOGIC_X0Y240 FDPE (Prop_fdpe_C_Q) 0.418 0.418 r usb_inst/ft601_be_reg[3]/Q
|
|
net (fo=1, routed) 0.001 0.419 ft601_be_OBUF[3]
|
|
E16 OBUF (Prop_obuf_I_O) 2.906 3.325 r ft601_be_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 3.325 ft601_be[3]
|
|
E16 r ft601_be[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
max delay 7.500 7.500
|
|
output delay -0.000 7.500
|
|
-------------------------------------------------------------------
|
|
required time 7.500
|
|
arrival time -3.325
|
|
-------------------------------------------------------------------
|
|
slack 4.175
|
|
|
|
|
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------
|
|
Path Group: (none)
|
|
From Clock: ft601_clk_in
|
|
To Clock:
|
|
|
|
Max Delay 3 Endpoints
|
|
Min Delay 42 Endpoints
|
|
--------------------------------------------------------------------------------------
|
|
|
|
|
|
Max Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_chip_reset_n
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 6.377ns (logic 3.679ns (57.690%) route 2.698ns (42.310%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 2.698 7.935 ft601_gpio1_OBUF
|
|
A14 OBUF (Prop_obuf_I_O) 3.300 11.235 r ft601_chip_reset_n_OBUF_inst/O
|
|
net (fo=0) 0.000 11.235 ft601_chip_reset_n
|
|
A14 r ft601_chip_reset_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: hb_counter_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_gpio0
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 5.982ns (logic 3.680ns (61.507%) route 2.303ns (38.493%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.539 4.847 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y181 FDRE r hb_counter_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y181 FDRE (Prop_fdre_C_Q) 0.379 5.226 r hb_counter_reg[24]/Q
|
|
net (fo=4, routed) 2.303 7.529 ft601_gpio0_OBUF
|
|
A18 OBUF (Prop_obuf_I_O) 3.301 10.830 r ft601_gpio0_OBUF_inst/O
|
|
net (fo=0) 0.000 10.830 ft601_gpio0
|
|
A18 r ft601_gpio0 (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_gpio1
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Max at Slow Process Corner
|
|
Data Path Delay: 5.896ns (logic 3.674ns (62.313%) route 2.222ns (37.687%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 1.400 1.400 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 1.827 3.227 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.081 3.308 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 1.550 4.858 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.379 5.237 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 2.222 7.459 ft601_gpio1_OBUF
|
|
A19 OBUF (Prop_obuf_I_O) 3.295 10.754 r ft601_gpio1_OBUF_inst/O
|
|
net (fo=0) 0.000 10.754 ft601_gpio1
|
|
A19 r ft601_gpio1 (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
|
|
|
|
|
|
|
|
Min Delay Paths
|
|
--------------------------------------------------------------------------------------
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[15]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[15]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.496ns (logic 1.495ns (99.933%) route 0.001ns (0.067%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y189 FDCE r usb_inst/ft601_data_out_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y189 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[15]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[15]
|
|
H15 OBUFT (Prop_obuft_I_O) 1.318 3.091 r ft601_data_OBUFT[15]_inst/O
|
|
net (fo=0) 0.000 3.091 ft601_data[15]
|
|
H15 r ft601_data[15] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[13]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[13]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.499ns (logic 1.498ns (99.933%) route 0.001ns (0.067%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y190 FDCE r usb_inst/ft601_data_out_reg[13]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y190 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[13]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[13]
|
|
J15 OBUFT (Prop_obuft_I_O) 1.321 3.094 r ft601_data_OBUFT[13]_inst/O
|
|
net (fo=0) 0.000 3.094 ft601_data[13]
|
|
J15 r ft601_data[13] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[12]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[12]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.502ns (logic 1.501ns (99.933%) route 0.001ns (0.067%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y155 FDCE r usb_inst/ft601_data_out_reg[12]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y155 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[12]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[12]
|
|
L15 OBUFT (Prop_obuft_I_O) 1.324 3.097 r ft601_data_OBUFT[12]_inst/O
|
|
net (fo=0) 0.000 3.097 ft601_data[12]
|
|
L15 r ft601_data[12] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[14]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[14]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.503ns (logic 1.502ns (99.933%) route 0.001ns (0.067%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y156 FDCE r usb_inst/ft601_data_out_reg[14]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y156 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[14]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[14]
|
|
L14 OBUFT (Prop_obuft_I_O) 1.325 3.098 r ft601_data_OBUFT[14]_inst/O
|
|
net (fo=0) 0.000 3.098 ft601_data[14]
|
|
L14 r ft601_data[14] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[24]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[24]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.503ns (logic 1.502ns (99.933%) route 0.001ns (0.067%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y193 FDCE r usb_inst/ft601_data_out_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y193 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[24]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_IOBUF[24]_inst/I
|
|
H14 OBUFT (Prop_obuft_I_O) 1.325 3.098 r ft601_data_IOBUF[24]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.098 ft601_data[24]
|
|
H14 r ft601_data[24] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[31]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[31]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.512ns (logic 1.511ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.635 1.588 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y176 FDCE r usb_inst/ft601_data_out_reg[31]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y176 FDCE (Prop_fdce_C_Q) 0.177 1.765 r usb_inst/ft601_data_out_reg[31]/Q
|
|
net (fo=1, routed) 0.001 1.766 ft601_data_IOBUF[31]_inst/I
|
|
J19 OBUFT (Prop_obuft_I_O) 1.334 3.100 r ft601_data_IOBUF[31]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.100 ft601_data[31]
|
|
J19 r ft601_data[31] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[22]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[22]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.505ns (logic 1.504ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y192 FDCE r usb_inst/ft601_data_out_reg[22]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y192 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[22]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[22]
|
|
G17 OBUFT (Prop_obuft_I_O) 1.327 3.100 r ft601_data_OBUFT[22]_inst/O
|
|
net (fo=0) 0.000 3.100 ft601_data[22]
|
|
G17 r ft601_data[22] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[17]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[17]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.504ns (logic 1.503ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y196 FDCE r usb_inst/ft601_data_out_reg[17]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y196 FDCE (Prop_fdce_C_Q) 0.177 1.773 r usb_inst/ft601_data_out_reg[17]/Q
|
|
net (fo=1, routed) 0.001 1.774 ft601_data_OBUF[17]
|
|
G15 OBUFT (Prop_obuft_I_O) 1.326 3.100 r ft601_data_OBUFT[17]_inst/O
|
|
net (fo=0) 0.000 3.100 ft601_data[17]
|
|
G15 r ft601_data[17] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[19]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[19]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.505ns (logic 1.504ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y195 FDCE r usb_inst/ft601_data_out_reg[19]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y195 FDCE (Prop_fdce_C_Q) 0.177 1.773 r usb_inst/ft601_data_out_reg[19]/Q
|
|
net (fo=1, routed) 0.001 1.774 ft601_data_OBUF[19]
|
|
G16 OBUFT (Prop_obuft_I_O) 1.327 3.100 r ft601_data_OBUFT[19]_inst/O
|
|
net (fo=0) 0.000 3.100 ft601_data[19]
|
|
G16 r ft601_data[19] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[30]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[30]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.514ns (logic 1.513ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.635 1.588 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y175 FDCE r usb_inst/ft601_data_out_reg[30]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y175 FDCE (Prop_fdce_C_Q) 0.177 1.765 r usb_inst/ft601_data_out_reg[30]/Q
|
|
net (fo=1, routed) 0.001 1.766 ft601_data_IOBUF[30]_inst/I
|
|
H19 OBUFT (Prop_obuft_I_O) 1.336 3.102 r ft601_data_IOBUF[30]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.102 ft601_data[30]
|
|
H19 r ft601_data[30] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[10]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[10]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.508ns (logic 1.507ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y188 FDCE r usb_inst/ft601_data_out_reg[10]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y188 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[10]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[10]
|
|
H17 OBUFT (Prop_obuft_I_O) 1.330 3.103 r ft601_data_OBUFT[10]_inst/O
|
|
net (fo=0) 0.000 3.103 ft601_data[10]
|
|
H17 r ft601_data[10] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[25]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[25]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.509ns (logic 1.508ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y194 FDCE r usb_inst/ft601_data_out_reg[25]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y194 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[25]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_IOBUF[25]_inst/I
|
|
J14 OBUFT (Prop_obuft_I_O) 1.331 3.104 r ft601_data_IOBUF[25]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.104 ft601_data[25]
|
|
J14 r ft601_data[25] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[28]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[28]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.510ns (logic 1.509ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y161 FDCE r usb_inst/ft601_data_out_reg[28]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y161 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[28]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_IOBUF[28]_inst/I
|
|
K14 OBUFT (Prop_obuft_I_O) 1.332 3.105 r ft601_data_IOBUF[28]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.105 ft601_data[28]
|
|
K14 r ft601_data[28] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[21]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[21]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.513ns (logic 1.512ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y167 FDCE r usb_inst/ft601_data_out_reg[21]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y167 FDCE (Prop_fdce_C_Q) 0.177 1.769 r usb_inst/ft601_data_out_reg[21]/Q
|
|
net (fo=1, routed) 0.001 1.770 ft601_data_OBUF[21]
|
|
L18 OBUFT (Prop_obuft_I_O) 1.335 3.105 r ft601_data_OBUFT[21]_inst/O
|
|
net (fo=0) 0.000 3.105 ft601_data[21]
|
|
L18 r ft601_data[21] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[11]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[11]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.512ns (logic 1.511ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y157 FDCE r usb_inst/ft601_data_out_reg[11]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y157 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[11]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[11]
|
|
J17 OBUFT (Prop_obuft_I_O) 1.334 3.107 r ft601_data_OBUFT[11]_inst/O
|
|
net (fo=0) 0.000 3.107 ft601_data[11]
|
|
J17 r ft601_data[11] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[8]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[8]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.513ns (logic 1.512ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y187 FDCE r usb_inst/ft601_data_out_reg[8]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y187 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[8]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[8]
|
|
H18 OBUFT (Prop_obuft_I_O) 1.335 3.107 r ft601_data_OBUFT[8]_inst/O
|
|
net (fo=0) 0.000 3.107 ft601_data[8]
|
|
H18 r ft601_data[8] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[9]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[9]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.513ns (logic 1.512ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y158 FDCE r usb_inst/ft601_data_out_reg[9]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y158 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[9]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[9]
|
|
K17 OBUFT (Prop_obuft_I_O) 1.335 3.108 r ft601_data_OBUFT[9]_inst/O
|
|
net (fo=0) 0.000 3.108 ft601_data[9]
|
|
K17 r ft601_data[9] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[20]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[20]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.514ns (logic 1.513ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y191 FDCE r usb_inst/ft601_data_out_reg[20]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y191 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[20]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[20]
|
|
G18 OBUFT (Prop_obuft_I_O) 1.336 3.109 r ft601_data_OBUFT[20]_inst/O
|
|
net (fo=0) 0.000 3.109 ft601_data[20]
|
|
G18 r ft601_data[20] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[29]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[29]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.514ns (logic 1.513ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y162 FDCE r usb_inst/ft601_data_out_reg[29]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y162 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[29]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_IOBUF[29]_inst/I
|
|
K13 OBUFT (Prop_obuft_I_O) 1.336 3.109 r ft601_data_IOBUF[29]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.109 ft601_data[29]
|
|
K13 r ft601_data[29] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[16]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[16]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.512ns (logic 1.511ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y197 FDCE r usb_inst/ft601_data_out_reg[16]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y197 FDCE (Prop_fdce_C_Q) 0.177 1.774 r usb_inst/ft601_data_out_reg[16]/Q
|
|
net (fo=1, routed) 0.001 1.775 ft601_data_OBUF[16]
|
|
G13 OBUFT (Prop_obuft_I_O) 1.334 3.109 r ft601_data_OBUFT[16]_inst/O
|
|
net (fo=0) 0.000 3.109 ft601_data[16]
|
|
G13 r ft601_data[16] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[18]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[18]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.516ns (logic 1.515ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.644 1.597 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y198 FDCE r usb_inst/ft601_data_out_reg[18]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y198 FDCE (Prop_fdce_C_Q) 0.177 1.774 r usb_inst/ft601_data_out_reg[18]/Q
|
|
net (fo=1, routed) 0.001 1.775 ft601_data_OBUF[18]
|
|
H13 OBUFT (Prop_obuft_I_O) 1.338 3.113 r ft601_data_OBUFT[18]_inst/O
|
|
net (fo=0) 0.000 3.113 ft601_data[18]
|
|
H13 r ft601_data[18] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[6]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[6]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.519ns (logic 1.518ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y159 FDCE r usb_inst/ft601_data_out_reg[6]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y159 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[6]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[6]
|
|
L13 OBUFT (Prop_obuft_I_O) 1.341 3.114 r ft601_data_OBUFT[6]_inst/O
|
|
net (fo=0) 0.000 3.114 ft601_data[6]
|
|
L13 r ft601_data[6] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[3]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[3]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.523ns (logic 1.522ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y163 FDCE r usb_inst/ft601_data_out_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y163 FDCE (Prop_fdce_C_Q) 0.177 1.770 r usb_inst/ft601_data_out_reg[3]/Q
|
|
net (fo=1, routed) 0.001 1.771 ft601_data_OBUF[3]
|
|
M20 OBUFT (Prop_obuft_I_O) 1.345 3.116 r ft601_data_OBUFT[3]_inst/O
|
|
net (fo=0) 0.000 3.116 ft601_data[3]
|
|
M20 r ft601_data[3] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[23]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[23]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.526ns (logic 1.525ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.639 1.592 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y168 FDCE r usb_inst/ft601_data_out_reg[23]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y168 FDCE (Prop_fdce_C_Q) 0.177 1.769 r usb_inst/ft601_data_out_reg[23]/Q
|
|
net (fo=1, routed) 0.001 1.770 ft601_data_OBUF[23]
|
|
M18 OBUFT (Prop_obuft_I_O) 1.348 3.118 r ft601_data_OBUFT[23]_inst/O
|
|
net (fo=0) 0.000 3.118 ft601_data[23]
|
|
M18 r ft601_data[23] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[4]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[4]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.524ns (logic 1.523ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.642 1.595 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y160 FDCE r usb_inst/ft601_data_out_reg[4]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y160 FDCE (Prop_fdce_C_Q) 0.177 1.772 r usb_inst/ft601_data_out_reg[4]/Q
|
|
net (fo=1, routed) 0.001 1.773 ft601_data_OBUF[4]
|
|
M13 OBUFT (Prop_obuft_I_O) 1.346 3.119 r ft601_data_OBUFT[4]_inst/O
|
|
net (fo=0) 0.000 3.119 ft601_data[4]
|
|
M13 r ft601_data[4] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[0]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[0]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.536ns (logic 1.535ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 1.590 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y179 FDCE r usb_inst/ft601_data_out_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y179 FDCE (Prop_fdce_C_Q) 0.177 1.767 r usb_inst/ft601_data_out_reg[0]/Q
|
|
net (fo=1, routed) 0.001 1.768 ft601_data_IOBUF[0]_inst/I
|
|
L21 OBUFT (Prop_obuft_I_O) 1.358 3.126 r ft601_data_IOBUF[0]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.126 ft601_data[0]
|
|
L21 r ft601_data[0] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[27]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[27]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.536ns (logic 1.535ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y165 FDCE r usb_inst/ft601_data_out_reg[27]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y165 FDCE (Prop_fdce_C_Q) 0.177 1.770 r usb_inst/ft601_data_out_reg[27]/Q
|
|
net (fo=1, routed) 0.001 1.771 ft601_data_IOBUF[27]_inst/I
|
|
N19 OBUFT (Prop_obuft_I_O) 1.358 3.128 r ft601_data_IOBUF[27]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.128 ft601_data[27]
|
|
N19 r ft601_data[27] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[2]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[2]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.539ns (logic 1.538ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 1.590 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y180 FDCE r usb_inst/ft601_data_out_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y180 FDCE (Prop_fdce_C_Q) 0.177 1.767 r usb_inst/ft601_data_out_reg[2]/Q
|
|
net (fo=1, routed) 0.001 1.768 ft601_data_IOBUF[2]_inst/I
|
|
M21 OBUFT (Prop_obuft_I_O) 1.361 3.129 r ft601_data_IOBUF[2]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.129 ft601_data[2]
|
|
M21 r ft601_data[2] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[1]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[1]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.536ns (logic 1.535ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y164 FDCE r usb_inst/ft601_data_out_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y164 FDCE (Prop_fdce_C_Q) 0.177 1.770 r usb_inst/ft601_data_out_reg[1]/Q
|
|
net (fo=1, routed) 0.001 1.771 ft601_data_IOBUF[1]_inst/I
|
|
N20 OBUFT (Prop_obuft_I_O) 1.358 3.129 r ft601_data_IOBUF[1]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.129 ft601_data[1]
|
|
N20 r ft601_data[1] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[7]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[7]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.541ns (logic 1.540ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 1.590 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y169 FDCE r usb_inst/ft601_data_out_reg[7]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y169 FDCE (Prop_fdce_C_Q) 0.177 1.767 r usb_inst/ft601_data_out_reg[7]/Q
|
|
net (fo=1, routed) 0.001 1.768 ft601_data_OBUF[7]
|
|
M22 OBUFT (Prop_obuft_I_O) 1.363 3.131 r ft601_data_OBUFT[7]_inst/O
|
|
net (fo=0) 0.000 3.131 ft601_data[7]
|
|
M22 r ft601_data[7] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[5]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[5]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.544ns (logic 1.543ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.637 1.590 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y170 FDCE r usb_inst/ft601_data_out_reg[5]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y170 FDCE (Prop_fdce_C_Q) 0.177 1.767 r usb_inst/ft601_data_out_reg[5]/Q
|
|
net (fo=1, routed) 0.001 1.768 ft601_data_OBUF[5]
|
|
N22 OBUFT (Prop_obuft_I_O) 1.366 3.134 r ft601_data_OBUFT[5]_inst/O
|
|
net (fo=0) 0.000 3.134 ft601_data[5]
|
|
N22 r ft601_data[5] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_data_out_reg[26]/C
|
|
(rising edge-triggered cell FDCE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_data[26]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.544ns (logic 1.543ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUFT=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.640 1.593 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y166 FDCE r usb_inst/ft601_data_out_reg[26]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y166 FDCE (Prop_fdce_C_Q) 0.177 1.770 r usb_inst/ft601_data_out_reg[26]/Q
|
|
net (fo=1, routed) 0.001 1.771 ft601_data_IOBUF[26]_inst/I
|
|
N18 OBUFT (Prop_obuft_I_O) 1.366 3.137 r ft601_data_IOBUF[26]_inst/OBUFT/O
|
|
net (fo=1, unset) 0.000 3.137 ft601_data[26]
|
|
N18 r ft601_data[26] (INOUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_be_reg[3]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_be[3]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.503ns (logic 1.502ns (99.933%) route 0.001ns (0.067%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.730 1.683 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y240 FDPE r usb_inst/ft601_be_reg[3]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y240 FDPE (Prop_fdpe_C_Q) 0.177 1.860 r usb_inst/ft601_be_reg[3]/Q
|
|
net (fo=1, routed) 0.001 1.861 ft601_be_OBUF[3]
|
|
E16 OBUF (Prop_obuf_I_O) 1.325 3.186 r ft601_be_OBUF[3]_inst/O
|
|
net (fo=0) 0.000 3.186 ft601_be[3]
|
|
E16 r ft601_be[3] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_be_reg[2]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_be[2]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.505ns (logic 1.504ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.730 1.683 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y239 FDPE r usb_inst/ft601_be_reg[2]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y239 FDPE (Prop_fdpe_C_Q) 0.177 1.860 r usb_inst/ft601_be_reg[2]/Q
|
|
net (fo=1, routed) 0.001 1.861 ft601_be_OBUF[2]
|
|
D16 OBUF (Prop_obuf_I_O) 1.327 3.188 r ft601_be_OBUF[2]_inst/O
|
|
net (fo=0) 0.000 3.188 ft601_be[2]
|
|
D16 r ft601_be[2] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_rd_n_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_rd_n
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.524ns (logic 1.523ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.723 1.676 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y226 FDPE r usb_inst/ft601_rd_n_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y226 FDPE (Prop_fdpe_C_Q) 0.177 1.853 r usb_inst/ft601_rd_n_reg/Q
|
|
net (fo=1, routed) 0.001 1.854 ft601_rd_n_OBUF
|
|
D17 OBUF (Prop_obuf_I_O) 1.346 3.200 r ft601_rd_n_OBUF_inst/O
|
|
net (fo=0) 0.000 3.200 ft601_rd_n
|
|
D17 r ft601_rd_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_oe_n_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_oe_n
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.526ns (logic 1.525ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.723 1.676 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y225 FDPE r usb_inst/ft601_oe_n_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y225 FDPE (Prop_fdpe_C_Q) 0.177 1.853 r usb_inst/ft601_oe_n_reg/Q
|
|
net (fo=1, routed) 0.001 1.854 ft601_oe_n_OBUF
|
|
C17 OBUF (Prop_obuf_I_O) 1.348 3.202 r ft601_oe_n_OBUF_inst/O
|
|
net (fo=0) 0.000 3.202 ft601_oe_n
|
|
C17 r ft601_oe_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_wr_n_reg/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_wr_n
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.522ns (logic 1.521ns (99.934%) route 0.001ns (0.066%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.730 1.683 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y242 FDPE r usb_inst/ft601_wr_n_reg/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y242 FDPE (Prop_fdpe_C_Q) 0.177 1.860 r usb_inst/ft601_wr_n_reg/Q
|
|
net (fo=1, routed) 0.001 1.861 ft601_wr_n_OBUF
|
|
E13 OBUF (Prop_obuf_I_O) 1.344 3.205 r ft601_wr_n_OBUF_inst/O
|
|
net (fo=0) 0.000 3.205 ft601_wr_n
|
|
E13 r ft601_wr_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_be_reg[0]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_be[0]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.544ns (logic 1.543ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.727 1.680 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y218 FDPE r usb_inst/ft601_be_reg[0]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y218 FDPE (Prop_fdpe_C_Q) 0.177 1.857 r usb_inst/ft601_be_reg[0]/Q
|
|
net (fo=1, routed) 0.001 1.858 ft601_be_OBUF[0]
|
|
B20 OBUF (Prop_obuf_I_O) 1.366 3.225 r ft601_be_OBUF[0]_inst/O
|
|
net (fo=0) 0.000 3.225 ft601_be[0]
|
|
B20 r ft601_be[0] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: usb_inst/ft601_be_reg[1]/C
|
|
(rising edge-triggered cell FDPE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_be[1]
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 1.546ns (logic 1.545ns (99.935%) route 0.001ns (0.065%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.727 1.680 usb_inst/ft601_clk_in_IBUF_BUFG
|
|
OLOGIC_X0Y217 FDPE r usb_inst/ft601_be_reg[1]/C
|
|
------------------------------------------------------------------- -------------------
|
|
OLOGIC_X0Y217 FDPE (Prop_fdpe_C_Q) 0.177 1.857 r usb_inst/ft601_be_reg[1]/Q
|
|
net (fo=1, routed) 0.001 1.858 ft601_be_OBUF[1]
|
|
A20 OBUF (Prop_obuf_I_O) 1.368 3.227 r ft601_be_OBUF[1]_inst/O
|
|
net (fo=0) 0.000 3.227 ft601_be[1]
|
|
A20 r ft601_be[1] (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_gpio1
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.145ns (logic 1.391ns (64.848%) route 0.754ns (35.152%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 0.754 2.498 ft601_gpio1_OBUF
|
|
A19 OBUF (Prop_obuf_I_O) 1.250 3.748 r ft601_gpio1_OBUF_inst/O
|
|
net (fo=0) 0.000 3.748 ft601_gpio1
|
|
A19 r ft601_gpio1 (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: hb_counter_reg[24]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_gpio0
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.185ns (logic 1.397ns (63.905%) route 0.789ns (36.095%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.643 1.596 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X5Y181 FDRE r hb_counter_reg[24]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X5Y181 FDRE (Prop_fdre_C_Q) 0.141 1.737 r hb_counter_reg[24]/Q
|
|
net (fo=4, routed) 0.789 2.526 ft601_gpio0_OBUF
|
|
A18 OBUF (Prop_obuf_I_O) 1.256 3.781 r ft601_gpio0_OBUF_inst/O
|
|
net (fo=0) 0.000 3.781 ft601_gpio0
|
|
A18 r ft601_gpio0 (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
Slack: inf
|
|
Source: por_counter_reg[15]/C
|
|
(rising edge-triggered cell FDRE clocked by ft601_clk_in {rise@0.000ns fall@5.000ns period=10.000ns})
|
|
Destination: ft601_chip_reset_n
|
|
(output port)
|
|
Path Group: (none)
|
|
Path Type: Min at Fast Process Corner
|
|
Data Path Delay: 2.399ns (logic 1.396ns (58.187%) route 1.003ns (41.813%))
|
|
Logic Levels: 1 (OBUF=1)
|
|
Clock Uncertainty: 0.056ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
|
|
Total System Jitter (TSJ): 0.050ns
|
|
Total Input Jitter (TIJ): 0.100ns
|
|
Discrete Jitter (DJ): 0.000ns
|
|
Phase Error (PE): 0.000ns
|
|
Timing Exception: False Path
|
|
|
|
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
|
|
------------------------------------------------------------------- -------------------
|
|
(clock ft601_clk_in rise edge)
|
|
0.000 0.000 r
|
|
J20 0.000 0.000 r ft601_clk_in (IN)
|
|
net (fo=0) 0.000 0.000 ft601_clk_in
|
|
J20 IBUF (Prop_ibuf_I_O) 0.237 0.237 r ft601_clk_in_IBUF_inst/O
|
|
net (fo=1, routed) 0.690 0.927 ft601_clk_in_IBUF
|
|
BUFGCTRL_X0Y16 BUFG (Prop_bufg_I_O) 0.026 0.953 r ft601_clk_in_IBUF_BUFG_inst/O
|
|
net (fo=366, routed) 0.650 1.603 ft601_clk_in_IBUF_BUFG
|
|
SLICE_X0Y190 FDRE r por_counter_reg[15]/C
|
|
------------------------------------------------------------------- -------------------
|
|
SLICE_X0Y190 FDRE (Prop_fdre_C_Q) 0.141 1.744 r por_counter_reg[15]/Q
|
|
net (fo=7, routed) 1.003 2.747 ft601_gpio1_OBUF
|
|
A14 OBUF (Prop_obuf_I_O) 1.255 4.002 r ft601_chip_reset_n_OBUF_inst/O
|
|
net (fo=0) 0.000 4.002 ft601_chip_reset_n
|
|
A14 r ft601_chip_reset_n (OUT)
|
|
------------------------------------------------------------------- -------------------
|
|
|
|
|
|
|
|
|
|
|