PLFM_RADAR/docs/artifacts/te0713-te0701-heartbeat-2026-03-21.md

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TE0713/TE0701 heartbeat bring-up artifact

• Date: 2026-03-21
• Target: Trenz TE0713-03-82C46-A on TE0701-06
• Top module: radar_system_top_te0713_dev
• Constraint file: 9_Firmware/9_2_FPGA/constraints/te0713_te0701_minimal.xdc
• Bitstream: docs/artifacts/te0713-te0701-heartbeat-2026-03-21.bit

Build result:

• Vivado: 2025.2
• Implementation: write_bitstream Complete!
• DRC: 0 Errors
• WNS: +17.863 ns
• WHS: +0.265 ns

Purpose:

• Lowest-risk first-power image for TE0713 + TE0701
• Verifies FPGA configuration, primary clock path, and heartbeat/status outputs before FT601 or radar-path bring-up

Board-day usage:

• Program this image first
• Confirm JTAG enumeration and successful configuration
• Verify heartbeat/status activity before moving to FT601 or higher-risk integrations

Build origin:

• Built remotely on livepeerservice.ddns.net
• Vivado path: /mnt/bcache/Xilinx/Vivado/2025.2/Vivado/bin/vivado