Jason
7a35f42e61
Extract RECEIVER_RTL and SYSTEM_RTL shared arrays to replace 6 near-identical file lists. New modules now only need adding once.
552 lines
18 KiB
Bash
Executable File
552 lines
18 KiB
Bash
Executable File
#!/bin/bash
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# ===========================================================================
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# FPGA Regression Test Runner for AERIS-10 Radar
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# Phase 0: Vivado-style lint (catches issues iverilog silently accepts)
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# Phase 1+: Compile and run all verified iverilog testbenches
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#
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# Usage: ./run_regression.sh [--quick] [--skip-lint]
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# --quick Skip long-running integration tests (receiver golden, system TB)
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# --skip-lint Skip Phase 0 lint checks (not recommended)
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#
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# Exit code: 0 if all tests pass, 1 if any fail
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# ===========================================================================
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set -euo pipefail
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SCRIPT_DIR="$(cd "$(dirname "$0")" && pwd)"
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cd "$SCRIPT_DIR"
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QUICK=0
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SKIP_LINT=0
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for arg in "$@"; do
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case "$arg" in
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--quick) QUICK=1 ;;
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--skip-lint) SKIP_LINT=1 ;;
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esac
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done
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PASS=0
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FAIL=0
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SKIP=0
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LINT_WARN=0
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LINT_ERR=0
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ERRORS=""
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# Colors (if terminal supports it)
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RED='\033[0;31m'
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GREEN='\033[0;32m'
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YELLOW='\033[0;33m'
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CYAN='\033[0;36m'
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NC='\033[0m' # No Color
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# ===========================================================================
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# PHASE 0: VIVADO-STYLE LINT
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# Two layers:
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# (A) iverilog -Wall full-design compile — parse for serious warnings
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# (B) Custom regex checks for patterns Vivado treats as errors
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# ===========================================================================
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# Production RTL file list (same as system TB minus testbench files)
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# Uses ADC stub for IBUFDS/BUFIO primitives that iverilog can't parse
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PROD_RTL=(
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radar_system_top.v
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radar_transmitter.v
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dac_interface_single.v
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plfm_chirp_controller.v
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radar_receiver_final.v
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tb/ad9484_interface_400m_stub.v
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ddc_400m.v
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nco_400m_enhanced.v
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cic_decimator_4x_enhanced.v
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cdc_modules.v
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fir_lowpass.v
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ddc_input_interface.v
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chirp_memory_loader_param.v
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latency_buffer.v
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matched_filter_multi_segment.v
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matched_filter_processing_chain.v
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range_bin_decimator.v
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doppler_processor.v
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xfft_16.v
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fft_engine.v
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usb_data_interface.v
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usb_data_interface_ft2232h.v
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edge_detector.v
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radar_mode_controller.v
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rx_gain_control.v
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cfar_ca.v
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mti_canceller.v
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fpga_self_test.v
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)
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# Source-only RTL (not instantiated at top level, but should still be lint-clean)
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# Note: ad9484_interface_400m.v is excluded — it uses Xilinx primitives
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# (IBUFDS, BUFIO, BUFG, IDDR) that iverilog cannot compile. The production
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# design uses tb/ad9484_interface_400m_stub.v for simulation instead.
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EXTRA_RTL=(
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frequency_matched_filter.v
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)
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# ---------------------------------------------------------------------------
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# Shared RTL file lists for integration / system tests
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# Centralised here so a new module only needs adding once.
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# ---------------------------------------------------------------------------
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# Receiver chain (used by golden generate/compare tests)
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RECEIVER_RTL=(
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radar_receiver_final.v
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radar_mode_controller.v
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tb/ad9484_interface_400m_stub.v
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ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v
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cdc_modules.v fir_lowpass.v ddc_input_interface.v
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chirp_memory_loader_param.v latency_buffer.v
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matched_filter_multi_segment.v matched_filter_processing_chain.v
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range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
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rx_gain_control.v mti_canceller.v
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)
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# Full system top (receiver chain + TX + USB + detection + self-test)
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SYSTEM_RTL=(
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radar_system_top.v
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radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v
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"${RECEIVER_RTL[@]}"
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usb_data_interface.v usb_data_interface_ft2232h.v edge_detector.v
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cfar_ca.v fpga_self_test.v
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)
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# ---- Layer A: iverilog -Wall compilation ----
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run_lint_iverilog() {
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local label="$1"
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shift
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local files=("$@")
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local warn_file="/tmp/iverilog_lint_$$_${label}.log"
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printf " %-45s " "iverilog -Wall ($label)"
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if ! iverilog -g2001 -DSIMULATION -Wall -o /dev/null "${files[@]}" 2>"$warn_file"; then
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# Hard compile error — always fatal
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echo -e "${RED}COMPILE ERROR${NC}"
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while IFS= read -r line; do
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echo " $line"
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done < "$warn_file"
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LINT_ERR=$((LINT_ERR + 1))
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rm -f "$warn_file"
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return 1
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fi
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# Parse warnings — classify as error-level or info-level
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local err_count=0
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local info_count=0
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local err_lines=""
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while IFS= read -r line; do
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# Part-select out of range — Vivado Synth 8-524 (ERROR in Vivado)
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if echo "$line" | grep -q 'Part select.*is selecting after the vector\|out of bound bits'; then
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err_count=$((err_count + 1))
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err_lines="$err_lines\n ${RED}[VIVADO-ERR]${NC} $line"
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# Port width mismatch / connection mismatch
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elif echo "$line" | grep -q 'port.*does not match\|Port.*mismatch'; then
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err_count=$((err_count + 1))
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err_lines="$err_lines\n ${RED}[VIVADO-ERR]${NC} $line"
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# Informational warnings (timescale, dangling ports, array sensitivity)
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elif echo "$line" | grep -q 'timescale\|dangling\|sensitive to all'; then
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info_count=$((info_count + 1))
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# Unknown warning — report but don't fail
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elif [[ -n "$line" ]]; then
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info_count=$((info_count + 1))
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fi
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done < "$warn_file"
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if [[ "$err_count" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} ($err_count Vivado-class errors, $info_count info)"
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echo -e "$err_lines"
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LINT_ERR=$((LINT_ERR + err_count))
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else
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echo -e "${GREEN}PASS${NC} ($info_count info warnings)"
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fi
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rm -f "$warn_file"
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}
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# ---- Layer B: Custom regex static checks ----
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# Catches patterns that Vivado treats as errors/warnings but iverilog ignores
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run_lint_static() {
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printf " %-45s " "Static RTL checks"
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local err_count=0
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local warn_count=0
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local err_lines=""
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local warn_lines=""
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for f in "$@"; do
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[[ -f "$f" ]] || continue
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# Skip testbench files (tb/ directory) — only lint production RTL
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case "$f" in tb/*) continue ;; esac
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local linenum=0
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while IFS= read -r line; do
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linenum=$((linenum + 1))
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# --- CHECK 1: Part-select with literal range on reg ---
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# Pattern: identifier[N:M] where N exceeds declared width
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# (iverilog catches this, but belt-and-suspenders)
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# --- CHECK 2: case/casex/casez without default (non-full case) ---
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# Vivado SYNTH-6 / inferred latch warning
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# Heuristic: look for case/casex/casez, then check if 'default' appears
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# before the matching 'endcase'. This is approximate — full parsing
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# would need a real parser. We flag 'case' lines so the developer
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# can manually verify.
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# (Handled below as a multi-line check)
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# --- CHECK 3: Blocking assignment (=) inside always @(posedge ...) ---
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# Vivado SYNTH-5 warning for inferred latches / race conditions
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# Only flag if the always block is clocked (posedge/negedge)
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# This is a heuristic — we check for '= ' that isn't '<=', '==', '!='
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# inside an always block header containing 'posedge' or 'negedge'.
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# (Too complex for line-by-line — skip for now, handled by testbenches)
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# --- CHECK 4: Multi-driven register (assign + always on same signal) ---
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# (Would need cross-file analysis — skip for v1)
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done < "$f"
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done
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# --- Multi-line check: case without default ---
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for f in "$@"; do
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[[ -f "$f" ]] || continue
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case "$f" in tb/*) continue ;; esac
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# Find case blocks and check for default
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# Use awk to find case..endcase blocks missing 'default'
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local missing_defaults
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missing_defaults=$(awk '
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/^[[:space:]]*(case|casex|casez)[[:space:]]*\(/ {
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case_line = NR
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case_file = FILENAME
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has_default = 0
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in_case = 1
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next
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}
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in_case && /default[[:space:]]*:/ {
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has_default = 1
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}
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in_case && /endcase/ {
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if (!has_default) {
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printf "%s:%d: case statement without default\n", FILENAME, case_line
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}
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in_case = 0
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}
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' "$f" 2>/dev/null)
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if [[ -n "$missing_defaults" ]]; then
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while IFS= read -r hit; do
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warn_count=$((warn_count + 1))
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warn_lines="$warn_lines\n ${YELLOW}[SYNTH-6]${NC} $hit"
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done <<< "$missing_defaults"
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fi
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done
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# CHECK 5 ($readmemh in synth code) and CHECK 6 (unused includes)
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# require multi-line ifdef tracking / cross-file analysis. Not feasible
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# with line-by-line regex. Omitted — use Vivado lint instead.
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if [[ "$err_count" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} ($err_count errors, $warn_count warnings)"
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echo -e "$err_lines"
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LINT_ERR=$((LINT_ERR + err_count))
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elif [[ "$warn_count" -gt 0 ]]; then
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echo -e "${YELLOW}WARN${NC} ($warn_count warnings)"
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echo -e "$warn_lines"
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LINT_WARN=$((LINT_WARN + warn_count))
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else
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echo -e "${GREEN}PASS${NC}"
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fi
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}
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# ---------------------------------------------------------------------------
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# Helper: compile and run a single testbench
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# run_test <name> <vvp_path> <iverilog_args...>
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# ---------------------------------------------------------------------------
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run_test() {
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local name="$1"
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local vvp="$2"
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shift 2
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local args=("$@")
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printf " %-45s " "$name"
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# Compile
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if ! iverilog -g2001 -DSIMULATION -o "$vvp" "${args[@]}" 2>/tmp/iverilog_err_$$; then
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echo -e "${RED}COMPILE FAIL${NC}"
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ERRORS="$ERRORS\n $name: compile error ($(head -1 /tmp/iverilog_err_$$))"
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FAIL=$((FAIL + 1))
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return
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fi
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# Run
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local output
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output=$(timeout 120 vvp "$vvp" 2>&1) || true
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# Count PASS/FAIL in output (testbenches use explicit [PASS]/[FAIL] markers)
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local test_pass test_fail
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test_pass=$(echo "$output" | grep -Ec '^\[PASS([^]]*)\]' || true)
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test_fail=$(echo "$output" | grep -Ec '^\[FAIL([^]]*)\]' || true)
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if [[ "$test_fail" -gt 0 ]]; then
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echo -e "${RED}FAIL${NC} (pass=$test_pass, fail=$test_fail)"
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ERRORS="$ERRORS\n $name: $test_fail failure(s)"
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FAIL=$((FAIL + 1))
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elif [[ "$test_pass" -gt 0 ]]; then
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echo -e "${GREEN}PASS${NC} ($test_pass checks)"
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PASS=$((PASS + 1))
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else
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# No PASS/FAIL markers — check for clean completion
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if echo "$output" | grep -qi 'finish\|complete\|done'; then
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echo -e "${GREEN}PASS${NC} (completed)"
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PASS=$((PASS + 1))
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else
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echo -e "${YELLOW}UNKNOWN${NC} (no PASS/FAIL markers)"
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ERRORS="$ERRORS\n $name: no pass/fail markers in output"
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FAIL=$((FAIL + 1))
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fi
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fi
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rm -f "$vvp"
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}
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# ===========================================================================
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echo "============================================"
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echo " AERIS-10 FPGA Regression Test Suite"
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echo "============================================"
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echo ""
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echo "Date: $(date)"
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echo "iverilog: $(iverilog -V 2>&1 | head -1)"
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echo ""
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# ===========================================================================
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# PHASE 0: LINT (Vivado-class error detection)
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# ===========================================================================
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if [[ "$SKIP_LINT" -eq 0 ]]; then
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echo "--- PHASE 0: LINT (Vivado-class checks) ---"
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# Layer A: iverilog -Wall on full production design
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run_lint_iverilog "production" "${PROD_RTL[@]}"
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# Layer A: standalone modules not in top-level hierarchy
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for extra in "${EXTRA_RTL[@]}"; do
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if [[ -f "$extra" ]]; then
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run_lint_iverilog "$(basename "$extra" .v)" "$extra"
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fi
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done
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# Layer B: custom static regex checks
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ALL_RTL=("${PROD_RTL[@]}" "${EXTRA_RTL[@]}")
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run_lint_static "${ALL_RTL[@]}"
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echo ""
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if [[ "$LINT_ERR" -gt 0 ]]; then
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echo -e "${RED} LINT FAILED: $LINT_ERR Vivado-class error(s) detected.${NC}"
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echo " Fix lint errors before pushing to Vivado. Aborting regression."
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echo ""
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exit 1
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elif [[ "$LINT_WARN" -gt 0 ]]; then
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echo -e "${YELLOW} LINT: $LINT_WARN advisory warning(s) (non-blocking)${NC}"
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else
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echo -e "${GREEN} LINT: All checks passed${NC}"
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fi
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echo ""
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else
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echo "--- PHASE 0: LINT (skipped via --skip-lint) ---"
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echo ""
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fi
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# ===========================================================================
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# PHASE 1: UNIT TESTS — Changed Modules (HIGH PRIORITY)
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# ===========================================================================
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echo "--- PHASE 1: Changed Modules ---"
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run_test "CIC Decimator" \
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tb/tb_cic_reg.vvp \
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tb/tb_cic_decimator.v cic_decimator_4x_enhanced.v
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run_test "Chirp Controller (BRAM)" \
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tb/tb_chirp_reg.vvp \
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tb/tb_chirp_controller.v plfm_chirp_controller.v
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run_test "Chirp Contract" \
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tb/tb_chirp_ctr_reg.vvp \
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tb/tb_chirp_contract.v plfm_chirp_controller.v
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run_test "Doppler Processor (DSP48)" \
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tb/tb_doppler_reg.vvp \
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tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v
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run_test "Threshold Detector (detection bugs)" \
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tb/tb_threshold_detector.vvp \
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tb/tb_threshold_detector.v
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run_test "RX Gain Control (digital gain)" \
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tb/tb_rx_gain_control.vvp \
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tb/tb_rx_gain_control.v rx_gain_control.v
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run_test "MTI Canceller (ground clutter)" \
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tb/tb_mti_canceller.vvp \
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tb/tb_mti_canceller.v mti_canceller.v
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run_test "CFAR CA Detector" \
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tb/tb_cfar_ca.vvp \
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tb/tb_cfar_ca.v cfar_ca.v
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run_test "FPGA Self-Test" \
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tb/tb_fpga_self_test.vvp \
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tb/tb_fpga_self_test.v fpga_self_test.v
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echo ""
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# ===========================================================================
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# PHASE 2: INTEGRATION TESTS
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# ===========================================================================
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echo "--- PHASE 2: Integration Tests ---"
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run_test "DDC Chain (NCO→CIC→FIR)" \
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tb/tb_ddc_reg.vvp \
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tb/tb_ddc_cosim.v ddc_400m.v nco_400m_enhanced.v \
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cic_decimator_4x_enhanced.v fir_lowpass.v cdc_modules.v
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# Real-data co-simulation: committed golden hex vs RTL (exact match required).
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# These catch architecture mismatches (e.g. 32-pt → dual 16-pt Doppler FFT)
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# that self-blessing golden-generate/compare tests cannot detect.
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run_test "Doppler Real-Data (ADI CN0566, exact match)" \
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tb/tb_doppler_realdata.vvp \
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tb/tb_doppler_realdata.v doppler_processor.v xfft_16.v fft_engine.v
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run_test "Full-Chain Real-Data (decim→Doppler, exact match)" \
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tb/tb_fullchain_realdata.vvp \
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tb/tb_fullchain_realdata.v range_bin_decimator.v \
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doppler_processor.v xfft_16.v fft_engine.v
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if [[ "$QUICK" -eq 0 ]]; then
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# Golden generate
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run_test "Receiver (golden generate)" \
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tb/tb_rx_golden_reg.vvp \
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-DGOLDEN_GENERATE \
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tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
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# Golden compare
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run_test "Receiver (golden compare)" \
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tb/tb_rx_compare_reg.vvp \
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tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
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# Full system top (monitoring-only, legacy)
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run_test "System Top (radar_system_tb)" \
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tb/tb_system_reg.vvp \
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tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
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# E2E integration (46 strict checks: TX, RX, USB R/W, CDC, safety, reset)
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run_test "System E2E (tb_system_e2e)" \
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tb/tb_system_e2e_reg.vvp \
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tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
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# USB_MODE=1 (FT2232H production) variants of system tests
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run_test "System Top USB_MODE=1 (FT2232H)" \
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tb/tb_system_ft2232h_reg.vvp \
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-DUSB_MODE_1 \
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tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
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run_test "System E2E USB_MODE=1 (FT2232H)" \
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tb/tb_system_e2e_ft2232h_reg.vvp \
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-DUSB_MODE_1 \
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tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
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else
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echo " (skipped receiver golden + system top + E2E — use without --quick)"
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SKIP=$((SKIP + 6))
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fi
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|
echo ""
|
|
|
|
# ===========================================================================
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|
# PHASE 3: UNIT TESTS — Signal Processing
|
|
# ===========================================================================
|
|
echo "--- PHASE 3: Signal Processing ---"
|
|
|
|
run_test "FFT Engine" \
|
|
tb/tb_fft_reg.vvp \
|
|
tb/tb_fft_engine.v fft_engine.v
|
|
|
|
run_test "NCO 400MHz" \
|
|
tb/tb_nco_reg.vvp \
|
|
tb/tb_nco_400m.v nco_400m_enhanced.v
|
|
|
|
run_test "FIR Lowpass" \
|
|
tb/tb_fir_reg.vvp \
|
|
tb/tb_fir_lowpass.v fir_lowpass.v
|
|
|
|
run_test "Matched Filter Chain" \
|
|
tb/tb_mf_reg.vvp \
|
|
tb/tb_matched_filter_processing_chain.v matched_filter_processing_chain.v \
|
|
fft_engine.v chirp_memory_loader_param.v
|
|
|
|
echo ""
|
|
|
|
# ===========================================================================
|
|
# PHASE 4: UNIT TESTS — Infrastructure
|
|
# ===========================================================================
|
|
echo "--- PHASE 4: Infrastructure ---"
|
|
|
|
run_test "CDC Modules (3 variants)" \
|
|
tb/tb_cdc_reg.vvp \
|
|
tb/tb_cdc_modules.v cdc_modules.v
|
|
|
|
run_test "Edge Detector" \
|
|
tb/tb_edge_reg.vvp \
|
|
tb/tb_edge_detector.v edge_detector.v
|
|
|
|
run_test "USB Data Interface" \
|
|
tb/tb_usb_reg.vvp \
|
|
tb/tb_usb_data_interface.v usb_data_interface.v
|
|
|
|
run_test "Range Bin Decimator" \
|
|
tb/tb_rbd_reg.vvp \
|
|
tb/tb_range_bin_decimator.v range_bin_decimator.v
|
|
|
|
run_test "Radar Mode Controller" \
|
|
tb/tb_rmc_reg.vvp \
|
|
tb/tb_radar_mode_controller.v radar_mode_controller.v
|
|
|
|
echo ""
|
|
|
|
# ===========================================================================
|
|
# SUMMARY
|
|
# ===========================================================================
|
|
TOTAL=$((PASS + FAIL + SKIP))
|
|
echo "============================================"
|
|
echo " RESULTS"
|
|
echo "============================================"
|
|
if [[ "$SKIP_LINT" -eq 0 ]]; then
|
|
if [[ "$LINT_ERR" -gt 0 ]]; then
|
|
echo -e " Lint: ${RED}$LINT_ERR error(s)${NC}, $LINT_WARN warning(s)"
|
|
elif [[ "$LINT_WARN" -gt 0 ]]; then
|
|
echo -e " Lint: ${GREEN}0 errors${NC}, ${YELLOW}$LINT_WARN warning(s)${NC}"
|
|
else
|
|
echo -e " Lint: ${GREEN}clean${NC}"
|
|
fi
|
|
fi
|
|
echo " Tests: $PASS passed, $FAIL failed, $SKIP skipped / $TOTAL total"
|
|
echo "============================================"
|
|
|
|
if [[ -n "$ERRORS" ]]; then
|
|
echo ""
|
|
echo "Failures:"
|
|
echo -e "$ERRORS"
|
|
fi
|
|
|
|
echo ""
|
|
|
|
# Exit with error if any failures
|
|
if [[ "$FAIL" -gt 0 ]]; then
|
|
exit 1
|
|
fi
|
|
|
|
exit 0
|