Jason
a5a5e96a57
Bug: rounding logic 'adc_i <= ddc_i[17:2] + ddc_i[1]' overflows when ddc_i[17:2]=0x7FFF and ddc_i[1]=1, causing 0x7FFF+1=0x8000 (sign flip from max positive to most negative value). Fix: add explicit saturation — clamp to 0x7FFF when truncated value is max positive and round bit is set. Negative values cannot overflow since rounding only moves toward zero. New testbench: tb_ddc_input_interface.v with 26 tests covering rounding, truncation, overflow saturation at positive boundary, negative full scale, valid synchronization, and sync error detection.
67 lines
2.0 KiB
Verilog
67 lines
2.0 KiB
Verilog
`timescale 1ns / 1ps
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// ddc_input_interface.v
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module ddc_input_interface (
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input wire clk, // 100MHz
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input wire reset_n,
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// DDC Input (18-bit)
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input wire signed [17:0] ddc_i,
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input wire signed [17:0] ddc_q,
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input wire valid_i,
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input wire valid_q,
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// Scaled output (16-bit)
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output reg signed [15:0] adc_i,
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output reg signed [15:0] adc_q,
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output reg adc_valid,
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// Status
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output wire data_sync_error
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);
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// Synchronize valid signals
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reg valid_i_reg, valid_q_reg;
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reg valid_sync;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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valid_i_reg <= 1'b0;
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valid_q_reg <= 1'b0;
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valid_sync <= 1'b0;
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adc_valid <= 1'b0;
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end else begin
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valid_i_reg <= valid_i;
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valid_q_reg <= valid_q;
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// Require both I and Q valid simultaneously
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valid_sync <= valid_i_reg && valid_q_reg;
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adc_valid <= valid_sync;
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end
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end
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// Scale 18-bit to 16-bit with convergent rounding + saturation
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// ddc_i[17:2] extracts the upper 16 bits; ddc_i[1] is the rounding bit.
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// Without saturation, 0x7FFF + 1 = 0x8000 (sign flip at positive full scale).
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// Fix: saturate to 0x7FFF when rounding would overflow a positive value.
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// Negative values cannot overflow: the most negative 18-bit value (-131072)
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// truncates to -8192 (0x8000 as 16-bit) and rounding only moves toward zero.
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wire [15:0] trunc_i = ddc_i[17:2];
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wire [15:0] trunc_q = ddc_q[17:2];
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wire round_i = ddc_i[1];
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wire round_q = ddc_q[1];
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// Overflow occurs only when truncated value is max positive AND round bit set
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wire sat_i = (trunc_i == 16'h7FFF) & round_i;
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wire sat_q = (trunc_q == 16'h7FFF) & round_q;
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always @(posedge clk) begin
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if (valid_sync) begin
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adc_i <= sat_i ? 16'sh7FFF : (trunc_i + {15'b0, round_i});
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adc_q <= sat_q ? 16'sh7FFF : (trunc_q + {15'b0, round_q});
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end
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end
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// Error detection
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assign data_sync_error = (valid_i_reg ^ valid_q_reg);
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endmodule |