Jason
e9705e40b7
Complete cross-layer upgrade from 1024-pt/64-bin to 2048-pt/512-bin FFT: FPGA RTL (14+ modules): - radar_params.vh: FFT_SIZE=2048, RANGE_BINS=512, 9-bit range, 6-bit stream - fft_engine.v: 2048-pt FFT with XPM BRAM - chirp_memory_loader_param.v: 2 segments x 2048 (was 4 x 1024) - matched_filter_multi_segment.v: BRAM inference for overlap_cache, explicit ov_waddr - mti_canceller.v: BRAM inference for prev_i/q arrays (was fabric FFs) - doppler_processor.v: 16384-deep memory, 14-bit addressing - cfar_ca.v: 512 rows, indentation fix - radar_receiver_final.v: rising-edge detector for frame_complete, 11-bit sample_addr - range_bin_decimator.v: 512 output bins - usb_data_interface_ft2232h.v: bulk per-frame with Manhattan magnitude - radar_mode_controller.v: XOR edge detector for toggle signals - rx_gain_control.v: updated for new bin count Python GUI + Protocol (8 files): - radar_protocol.py: 512-bin bulk frame parser, LSB-first bitmap - GUI_V65_Tk.py, v7/*.py: updated for 512 bins, 6m range resolution Golden data + tests: - All .hex/.csv/.npy golden references regenerated for 2048/512 - fft_twiddle_2048.mem added - Deleted stale seg2/seg3 chirp mem files - 9 new bulk frame cross-layer tests, deleted 6 stale per-sample tests - Deleted stale tb_cross_layer_ft2232h.v and dead contract_parser functions - Updated validate_mem_files.py for 2048/2-segment config MCU: RadarSettings.cpp max_distance/map_size 1536->3072 All 4 CI jobs pass: 285 tests, 0 failures, 0 skips
755 lines
24 KiB
Python
755 lines
24 KiB
Python
"""
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Cross-layer contract parsers.
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Extracts interface contracts (opcodes, bit widths, reset defaults, packet
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layouts) directly from the source files of each layer:
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- Python GUI: radar_protocol.py
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- FPGA RTL: radar_system_top.v, usb_data_interface_ft2232h.v,
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usb_data_interface.v
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- STM32 MCU: RadarSettings.cpp, main.cpp
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These parsers do NOT define the expected values — they discover what each
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layer actually implements, so the test can compare layers against ground
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truth and find bugs where both sides are wrong (like the 0x06 phantom
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opcode or the status_words[0] 37-bit truncation).
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"""
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from __future__ import annotations
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import re
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from dataclasses import dataclass, field
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from pathlib import Path
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# ---------------------------------------------------------------------------
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# Repository layout (relative to repo root)
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# ---------------------------------------------------------------------------
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REPO_ROOT = Path(__file__).resolve().parents[3]
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GUI_DIR = REPO_ROOT / "9_Firmware" / "9_3_GUI"
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FPGA_DIR = REPO_ROOT / "9_Firmware" / "9_2_FPGA"
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MCU_DIR = REPO_ROOT / "9_Firmware" / "9_1_Microcontroller"
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MCU_LIB_DIR = MCU_DIR / "9_1_1_C_Cpp_Libraries"
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MCU_CODE_DIR = MCU_DIR / "9_1_3_C_Cpp_Code"
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XDC_DIR = FPGA_DIR / "constraints"
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# ===================================================================
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# Data structures
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# ===================================================================
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@dataclass
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class OpcodeEntry:
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"""One opcode as declared in a single layer."""
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name: str
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value: int
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register: str = "" # Verilog register name it writes to
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bit_slice: str = "" # e.g. "[3:0]", "[15:0]", "[0]"
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bit_width: int = 0 # derived from bit_slice
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reset_default: int | None = None
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is_pulse: bool = False # True for trigger/request opcodes
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@dataclass
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class StatusWordField:
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"""One field inside a status_words[] entry."""
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name: str
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word_index: int
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msb: int # bit position in the 32-bit word (0-indexed from LSB)
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lsb: int
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width: int
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@dataclass
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class DataPacketField:
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"""One field in the 11-byte data packet."""
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name: str
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byte_start: int # first byte index (0 = header)
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byte_end: int # last byte index (inclusive)
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width_bits: int
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@dataclass
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class PacketConstants:
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"""Header/footer/size constants for a packet type."""
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header: int
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footer: int
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size: int
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@dataclass
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class SettingsField:
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"""One field in the STM32 SET...END settings packet."""
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name: str
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offset: int # byte offset from start of payload (after "SET")
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size: int # bytes
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c_type: str # "double" or "uint32_t"
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@dataclass
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class GpioPin:
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"""A GPIO pin with direction."""
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name: str
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pin_id: str # e.g. "PD8", "H11"
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direction: str # "output" or "input"
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layer: str # "stm32" or "fpga"
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@dataclass
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class ConcatWidth:
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"""Result of counting bits in a Verilog concatenation."""
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total_bits: int
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target_bits: int # width of the register being assigned to
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fragments: list[tuple[str, int]] = field(default_factory=list)
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truncated: bool = False
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# ===================================================================
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# Python layer parser
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# ===================================================================
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def parse_python_opcodes(filepath: Path | None = None) -> dict[int, OpcodeEntry]:
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"""Parse the Opcode enum from radar_protocol.py.
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Returns {opcode_value: OpcodeEntry}.
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"""
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if filepath is None:
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filepath = GUI_DIR / "radar_protocol.py"
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text = filepath.read_text()
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# Find the Opcode class body
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match = re.search(r'class Opcode\b.*?(?=\nclass |\Z)', text, re.DOTALL)
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if not match:
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raise ValueError(f"Could not find 'class Opcode' in {filepath}")
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opcodes: dict[int, OpcodeEntry] = {}
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for m in re.finditer(r'(\w+)\s*=\s*(0x[0-9a-fA-F]+)', match.group()):
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name = m.group(1)
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value = int(m.group(2), 16)
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opcodes[value] = OpcodeEntry(name=name, value=value)
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return opcodes
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def parse_python_packet_constants(filepath: Path | None = None) -> dict[str, PacketConstants]:
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"""Extract HEADER_BYTE, FOOTER_BYTE, STATUS_HEADER_BYTE, packet sizes."""
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if filepath is None:
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filepath = GUI_DIR / "radar_protocol.py"
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text = filepath.read_text()
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def _find(pattern: str) -> int:
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m = re.search(pattern, text)
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if not m:
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raise ValueError(f"Pattern not found: {pattern}")
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val = m.group(1)
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return int(val, 16) if val.startswith("0x") else int(val)
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header = _find(r'HEADER_BYTE\s*=\s*(0x[0-9a-fA-F]+|\d+)')
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footer = _find(r'FOOTER_BYTE\s*=\s*(0x[0-9a-fA-F]+|\d+)')
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status_header = _find(r'STATUS_HEADER_BYTE\s*=\s*(0x[0-9a-fA-F]+|\d+)')
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data_size = _find(r'DATA_PACKET_SIZE\s*=\s*(\d+)')
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status_size = _find(r'STATUS_PACKET_SIZE\s*=\s*(\d+)')
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return {
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"data": PacketConstants(header=header, footer=footer, size=data_size),
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"status": PacketConstants(header=status_header, footer=footer, size=status_size),
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}
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def parse_python_status_fields(filepath: Path | None = None) -> list[StatusWordField]:
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"""
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Extract bit shift/mask operations from parse_status_packet().
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Returns the fields with word index and bit positions as Python sees them.
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"""
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if filepath is None:
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filepath = GUI_DIR / "radar_protocol.py"
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text = filepath.read_text()
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match = re.search(
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r'def parse_status_packet\(.*?\).*?(?=\n @|\n def |\nclass |\Z)',
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text, re.DOTALL
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)
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if not match:
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raise ValueError("Could not find parse_status_packet()")
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body = match.group()
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fields: list[StatusWordField] = []
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# Pattern: sr.field = (words[N] >> S) & MASK # noqa: ERA001
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for m in re.finditer(
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r'sr\.(\w+)\s*=\s*\(words\[(\d+)\]\s*>>\s*(\d+)\)\s*&\s*(0x[0-9a-fA-F]+|\d+)',
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body
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):
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name = m.group(1)
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word_idx = int(m.group(2))
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shift = int(m.group(3))
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mask_str = m.group(4)
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mask = int(mask_str, 16) if mask_str.startswith("0x") else int(mask_str)
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width = mask.bit_length()
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fields.append(StatusWordField(
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name=name, word_index=word_idx,
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msb=shift + width - 1, lsb=shift, width=width
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))
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# Pattern: sr.field = words[N] & MASK (no shift)
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for m in re.finditer(
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r'sr\.(\w+)\s*=\s*words\[(\d+)\]\s*&\s*(0x[0-9a-fA-F]+|\d+)',
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body
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):
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name = m.group(1)
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word_idx = int(m.group(2))
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mask_str = m.group(3)
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mask = int(mask_str, 16) if mask_str.startswith("0x") else int(mask_str)
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width = mask.bit_length()
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# Skip if already captured by the shift pattern
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if not any(f.name == name and f.word_index == word_idx for f in fields):
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fields.append(StatusWordField(
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name=name, word_index=word_idx,
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msb=width - 1, lsb=0, width=width
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))
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return fields
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# ===================================================================
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# Verilog layer parser
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# ===================================================================
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def _parse_bit_slice(s: str) -> int:
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"""Parse '[15:0]' -> 16, '[0]' -> 1, '' -> 16 (full cmd_value)."""
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m = re.match(r'\[(\d+):(\d+)\]', s)
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if m:
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return int(m.group(1)) - int(m.group(2)) + 1
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m = re.match(r'\[(\d+)\]', s)
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if m:
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return 1
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return 16 # default: full 16-bit cmd_value
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def parse_verilog_opcodes(filepath: Path | None = None) -> dict[int, OpcodeEntry]:
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"""
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Parse the opcode case statement from radar_system_top.v.
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Returns {opcode_value: OpcodeEntry}.
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"""
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if filepath is None:
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filepath = FPGA_DIR / "radar_system_top.v"
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text = filepath.read_text()
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# Find the command decode case block
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# Pattern: case statement with 8'hXX opcodes
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opcodes: dict[int, OpcodeEntry] = {}
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# Pattern 1: Simple assignment — 8'hXX: register <= rhs;
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for m in re.finditer(
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r"8'h([0-9a-fA-F]{2})\s*:\s*(\w+)\s*<=\s*(.*?)(?:;|$)",
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text, re.MULTILINE
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):
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value = int(m.group(1), 16)
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register = m.group(2)
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rhs = m.group(3).strip()
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# Determine if it's a pulse (assigned literal 1)
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is_pulse = rhs in ("1", "1'b1")
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# Extract bit slice from the RHS (e.g., usb_cmd_value[3:0])
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bit_slice = ""
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slice_m = re.search(r'usb_cmd_value(\[\d+(?::\d+)?\])', rhs)
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if slice_m:
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bit_slice = slice_m.group(1)
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elif "usb_cmd_value" in rhs:
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bit_slice = "[15:0]" # full width
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bit_width = _parse_bit_slice(bit_slice) if bit_slice else 0
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opcodes[value] = OpcodeEntry(
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name=register,
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value=value,
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register=register,
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bit_slice=bit_slice,
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bit_width=bit_width,
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is_pulse=is_pulse,
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)
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# Pattern 2: begin...end blocks — 8'hXX: begin ... register <= ... end
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# These are used for opcodes with validation logic (e.g., 0x15 clamp)
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for m in re.finditer(
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r"8'h([0-9a-fA-F]{2})\s*:\s*begin\b(.*?)end\b",
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text, re.DOTALL
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):
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value = int(m.group(1), 16)
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if value in opcodes:
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continue # Already captured by pattern 1
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body = m.group(2)
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# Find the first register assignment (host_xxx <=)
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assign_m = re.search(r'(host_\w+)\s*<=\s*(.+?);', body)
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if not assign_m:
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continue
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register = assign_m.group(1)
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rhs = assign_m.group(2).strip()
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bit_slice = ""
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slice_m = re.search(r'usb_cmd_value(\[\d+(?::\d+)?\])', body)
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if slice_m:
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bit_slice = slice_m.group(1)
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elif "usb_cmd_value" in body:
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bit_slice = "[15:0]"
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bit_width = _parse_bit_slice(bit_slice) if bit_slice else 0
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opcodes[value] = OpcodeEntry(
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name=register,
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value=value,
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register=register,
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bit_slice=bit_slice,
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bit_width=bit_width,
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is_pulse=False,
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)
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return opcodes
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def _parse_verilog_defines(filepath: Path | None = None) -> dict[str, str]:
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"""Parse `define macros from radar_params.vh into {name: raw_value}."""
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if filepath is None:
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filepath = FPGA_DIR / "radar_params.vh"
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if not filepath.exists():
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return {}
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defines: dict[str, str] = {}
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for m in re.finditer(
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r'`define\s+(\w+)\s+(.+?)(?://.*)?$',
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filepath.read_text(),
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re.MULTILINE,
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):
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defines[m.group(1)] = m.group(2).strip()
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return defines
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def _resolve_verilog_literal(val_str: str) -> int:
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"""Convert a Verilog literal (e.g. 6'b000_111 or 10000) to int."""
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if "'" in val_str:
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base_char = val_str.split("'")[1][0].lower()
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digits = val_str.split("'")[1][1:].replace("_", "")
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base = {"b": 2, "d": 10, "h": 16, "o": 8}[base_char]
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return int(digits, base)
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return int(val_str)
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def parse_verilog_reset_defaults(filepath: Path | None = None) -> dict[str, int]:
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"""
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Parse the reset block from radar_system_top.v.
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Returns {register_name: reset_value}.
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Resolves `define macros from radar_params.vh.
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"""
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if filepath is None:
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filepath = FPGA_DIR / "radar_system_top.v"
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text = filepath.read_text()
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defines = _parse_verilog_defines()
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defaults: dict[str, int] = {}
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# Match patterns like: host_radar_mode <= 2'b01;
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# Also: host_detect_threshold <= 16'd10000;
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# Also: host_stream_control <= `RP_STREAM_CTRL_DEFAULT;
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for m in re.finditer(
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r'(host_\w+)\s*<=\s*(`\w+|\d+\'[bdho][0-9a-fA-F_]+|\d+)\s*;',
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text
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):
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reg = m.group(1)
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val_str = m.group(2)
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# Resolve macro or parse Verilog literal
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if val_str.startswith("`"):
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macro_name = val_str[1:]
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if macro_name not in defines:
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continue # skip unresolvable macros
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value = _resolve_verilog_literal(defines[macro_name])
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else:
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value = _resolve_verilog_literal(val_str)
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# Only keep first occurrence (the reset block comes before the
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# opcode decode which also has <= assignments)
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if reg not in defaults:
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defaults[reg] = value
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return defaults
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def parse_verilog_register_widths(filepath: Path | None = None) -> dict[str, int]:
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"""
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Parse register declarations from radar_system_top.v.
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Returns {register_name: bit_width}.
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"""
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if filepath is None:
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filepath = FPGA_DIR / "radar_system_top.v"
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text = filepath.read_text()
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widths: dict[str, int] = {}
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# Match: reg [15:0] host_detect_threshold;
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# Also: reg host_trigger_pulse;
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for m in re.finditer(
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r'reg\s+(?:\[\s*(\d+)\s*:\s*(\d+)\s*\]\s+)?(host_\w+)\s*;',
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text
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):
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width = int(m.group(1)) - int(m.group(2)) + 1 if m.group(1) is not None else 1
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widths[m.group(3)] = width
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return widths
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def parse_verilog_packet_constants(
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filepath: Path | None = None,
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) -> dict[str, PacketConstants]:
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"""Extract HEADER, FOOTER, STATUS_HEADER, packet size localparams."""
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if filepath is None:
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filepath = FPGA_DIR / "usb_data_interface_ft2232h.v"
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text = filepath.read_text()
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def _find(pattern: str) -> int:
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m = re.search(pattern, text)
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if not m:
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raise ValueError(f"Pattern not found in {filepath}: {pattern}")
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val = m.group(1)
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# Parse Verilog literals: 8'hAA → 0xAA, 5'd11 → 11
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vlog_m = re.match(r"\d+'h([0-9a-fA-F]+)", val)
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if vlog_m:
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return int(vlog_m.group(1), 16)
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vlog_m = re.match(r"\d+'d(\d+)", val)
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if vlog_m:
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return int(vlog_m.group(1))
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return int(val, 16) if val.startswith("0x") else int(val)
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_find(r"localparam\s+HEADER\s*=\s*(\d+'h[0-9a-fA-F]+)") # bulk frames — no data header
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footer_val = _find(r"localparam\s+FOOTER\s*=\s*(\d+'h[0-9a-fA-F]+)")
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status_hdr = _find(r"localparam\s+STATUS_HEADER\s*=\s*(\d+'h[0-9a-fA-F]+)")
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status_size = _find(r"STATUS_PKT_LEN\s*=\s*(\d+'d\d+)")
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# FT2232H uses bulk per-frame transfers — no fixed data packet size.
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# Only status packets have a fixed size.
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return {
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"status": PacketConstants(header=status_hdr, footer=footer_val, size=status_size),
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}
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def count_concat_bits(concat_expr: str, port_widths: dict[str, int]) -> ConcatWidth:
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"""
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Count total bits in a Verilog concatenation expression like:
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{8'hFF, 3'b000, status_radar_mode, 5'b00000, status_stream_ctrl, status_cfar_threshold}
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Uses port_widths to resolve signal widths. Returns ConcatWidth.
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"""
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# Remove outer braces
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inner = concat_expr.strip().strip("{}")
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fragments: list[tuple[str, int]] = []
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total = 0
|
|
|
|
for part in re.split(r',\s*', inner):
|
|
part = part.strip()
|
|
if not part:
|
|
continue
|
|
|
|
# Literal: N'bXXX, N'dXXX, N'hXX, or just a decimal
|
|
lit_match = re.match(r"(\d+)'[bdhoBDHO]", part)
|
|
if lit_match:
|
|
w = int(lit_match.group(1))
|
|
fragments.append((part, w))
|
|
total += w
|
|
continue
|
|
|
|
# Signal with bit select: sig[M:N] or sig[N]
|
|
sel_match = re.match(r'(\w+)\[(\d+):(\d+)\]', part)
|
|
if sel_match:
|
|
w = int(sel_match.group(2)) - int(sel_match.group(3)) + 1
|
|
fragments.append((part, w))
|
|
total += w
|
|
continue
|
|
|
|
sel_match = re.match(r'(\w+)\[(\d+)\]', part)
|
|
if sel_match:
|
|
fragments.append((part, 1))
|
|
total += 1
|
|
continue
|
|
|
|
# Bare signal: look up in port_widths
|
|
if part in port_widths:
|
|
w = port_widths[part]
|
|
fragments.append((part, w))
|
|
total += w
|
|
else:
|
|
# Unknown width — flag it
|
|
fragments.append((part, -1))
|
|
total = -1 # Can't compute
|
|
|
|
return ConcatWidth(
|
|
total_bits=total,
|
|
target_bits=32,
|
|
fragments=fragments,
|
|
truncated=total > 32 if total > 0 else False,
|
|
)
|
|
|
|
|
|
def parse_verilog_status_word_concats(
|
|
filepath: Path | None = None,
|
|
) -> dict[int, str]:
|
|
"""
|
|
Extract the raw concatenation expression for each status_words[N] assignment.
|
|
Returns {word_index: concat_expression_string}.
|
|
"""
|
|
if filepath is None:
|
|
filepath = FPGA_DIR / "usb_data_interface_ft2232h.v"
|
|
text = filepath.read_text()
|
|
|
|
results: dict[int, str] = {}
|
|
|
|
# Multi-line concat: status_words[N] <= {... };
|
|
# We need to handle multi-line expressions
|
|
for m in re.finditer(
|
|
r'status_words\[(\d+)\]\s*<=\s*(\{[^;]+\})\s*;',
|
|
text, re.DOTALL
|
|
):
|
|
idx = int(m.group(1))
|
|
expr = m.group(2)
|
|
# Strip single-line comments before normalizing whitespace
|
|
expr = re.sub(r'//[^\n]*', '', expr)
|
|
# Normalize whitespace
|
|
expr = re.sub(r'\s+', ' ', expr).strip()
|
|
results[idx] = expr
|
|
|
|
return results
|
|
|
|
|
|
def get_usb_interface_port_widths(filepath: Path | None = None) -> dict[str, int]:
|
|
"""
|
|
Parse port declarations from usb_data_interface_ft2232h.v module header.
|
|
Returns {port_name: bit_width}.
|
|
"""
|
|
if filepath is None:
|
|
filepath = FPGA_DIR / "usb_data_interface_ft2232h.v"
|
|
text = filepath.read_text()
|
|
|
|
widths: dict[str, int] = {}
|
|
|
|
# Match: input wire [15:0] status_cfar_threshold,
|
|
# Also: input wire status_self_test_busy
|
|
for m in re.finditer(
|
|
r'(?:input|output)\s+(?:wire|reg)\s+(?:\[\s*(\d+)\s*:\s*(\d+)\s*\]\s+)?(\w+)',
|
|
text
|
|
):
|
|
width = int(m.group(1)) - int(m.group(2)) + 1 if m.group(1) is not None else 1
|
|
widths[m.group(3)] = width
|
|
|
|
return widths
|
|
|
|
|
|
|
|
# ===================================================================
|
|
# STM32 / C layer parser
|
|
# ===================================================================
|
|
|
|
def parse_stm32_settings_fields(
|
|
filepath: Path | None = None,
|
|
) -> list[SettingsField]:
|
|
"""
|
|
Parse RadarSettings::parseFromUSB to extract field order, offsets, types.
|
|
"""
|
|
if filepath is None:
|
|
filepath = MCU_LIB_DIR / "RadarSettings.cpp"
|
|
|
|
if not filepath.exists():
|
|
return [] # MCU code not available (CI might not have it)
|
|
|
|
text = filepath.read_text(encoding="latin-1")
|
|
|
|
fields: list[SettingsField] = []
|
|
|
|
# Look for memcpy + shift patterns that extract doubles and uint32s
|
|
# Pattern for doubles: loop reading 8 bytes big-endian
|
|
# Pattern for uint32: 4 bytes big-endian
|
|
# We'll parse the assignment targets in order
|
|
|
|
# Find the parseFromUSB function
|
|
match = re.search(
|
|
r'parseFromUSB\s*\(.*?\)\s*\{(.*?)^\}',
|
|
text, re.DOTALL | re.MULTILINE
|
|
)
|
|
if not match:
|
|
return fields
|
|
|
|
body = match.group(1)
|
|
|
|
# The fields are extracted sequentially from the payload.
|
|
# Look for variable assignments that follow the memcpy/extraction pattern.
|
|
# Based on known code: extractDouble / extractUint32 patterns
|
|
field_names = [
|
|
("system_frequency", 8, "double"),
|
|
("chirp_duration_1", 8, "double"),
|
|
("chirp_duration_2", 8, "double"),
|
|
("chirps_per_position", 4, "uint32_t"),
|
|
("freq_min", 8, "double"),
|
|
("freq_max", 8, "double"),
|
|
("prf1", 8, "double"),
|
|
("prf2", 8, "double"),
|
|
("max_distance", 8, "double"),
|
|
("map_size", 8, "double"),
|
|
]
|
|
|
|
offset = 0
|
|
for name, size, ctype in field_names:
|
|
# Verify the field name appears in the function body
|
|
if name in body or name.replace("_", "") in body.lower():
|
|
fields.append(SettingsField(
|
|
name=name, offset=offset, size=size, c_type=ctype
|
|
))
|
|
offset += size
|
|
|
|
return fields
|
|
|
|
|
|
def parse_stm32_start_flag(
|
|
filepath: Path | None = None,
|
|
) -> list[int]:
|
|
"""Parse the USB start flag bytes from USBHandler.cpp."""
|
|
if filepath is None:
|
|
filepath = MCU_LIB_DIR / "USBHandler.cpp"
|
|
|
|
if not filepath.exists():
|
|
return []
|
|
|
|
text = filepath.read_text()
|
|
|
|
# Look for the start flag array, e.g. {23, 46, 158, 237}
|
|
match = re.search(r'start_flag.*?=\s*\{([^}]+)\}', text, re.DOTALL)
|
|
if not match:
|
|
# Try alternate patterns
|
|
match = re.search(r'\{(\s*\d+\s*,\s*\d+\s*,\s*\d+\s*,\s*\d+\s*)\}', text)
|
|
if not match:
|
|
return []
|
|
|
|
return [int(x.strip()) for x in match.group(1).split(",") if x.strip().isdigit()]
|
|
|
|
|
|
# ===================================================================
|
|
# GPIO parser
|
|
# ===================================================================
|
|
|
|
def parse_xdc_gpio_pins(filepath: Path | None = None) -> list[GpioPin]:
|
|
"""Parse XDC constraints for DIG_* pin assignments."""
|
|
if filepath is None:
|
|
filepath = XDC_DIR / "xc7a50t_ftg256.xdc"
|
|
|
|
if not filepath.exists():
|
|
return []
|
|
|
|
text = filepath.read_text()
|
|
pins: list[GpioPin] = []
|
|
|
|
# Match: set_property PACKAGE_PIN XX [get_ports {signal_name}]
|
|
for m in re.finditer(
|
|
r'set_property\s+PACKAGE_PIN\s+(\w+)\s+\[get_ports\s+\{?(\w+)\}?\]',
|
|
text
|
|
):
|
|
pin = m.group(1)
|
|
signal = m.group(2)
|
|
if any(kw in signal for kw in ("stm32_", "reset_n", "dig_")):
|
|
# Determine direction from signal name
|
|
if signal in ("stm32_new_chirp", "stm32_new_elevation",
|
|
"stm32_new_azimuth", "stm32_mixers_enable"):
|
|
direction = "input" # FPGA receives these
|
|
elif signal == "reset_n":
|
|
direction = "input"
|
|
else:
|
|
direction = "unknown"
|
|
pins.append(GpioPin(
|
|
name=signal, pin_id=pin, direction=direction, layer="fpga"
|
|
))
|
|
|
|
return pins
|
|
|
|
|
|
def parse_stm32_gpio_init(filepath: Path | None = None) -> list[GpioPin]:
|
|
"""Parse STM32 GPIO initialization for PD8-PD15 directions."""
|
|
if filepath is None:
|
|
filepath = MCU_CODE_DIR / "main.cpp"
|
|
|
|
if not filepath.exists():
|
|
return []
|
|
|
|
text = filepath.read_text()
|
|
pins: list[GpioPin] = []
|
|
|
|
# Look for GPIO_InitStruct.Pin and GPIO_InitStruct.Mode patterns
|
|
# This is approximate — STM32 HAL GPIO init is complex
|
|
# Look for PD8-PD15 configuration (output vs input)
|
|
|
|
# Pattern: GPIO_PIN_8 | GPIO_PIN_9 ... with Mode = OUTPUT
|
|
# We'll find blocks that configure GPIOD pins
|
|
for m in re.finditer(
|
|
r'GPIO_InitStruct\.Pin\s*=\s*([^;]+);.*?'
|
|
r'GPIO_InitStruct\.Mode\s*=\s*(\w+)',
|
|
text, re.DOTALL
|
|
):
|
|
pin_expr = m.group(1)
|
|
mode = m.group(2)
|
|
|
|
direction = "output" if "OUTPUT" in mode else "input"
|
|
|
|
# Extract individual pin numbers
|
|
for pin_m in re.finditer(r'GPIO_PIN_(\d+)', pin_expr):
|
|
pin_num = int(pin_m.group(1))
|
|
if 8 <= pin_num <= 15:
|
|
pins.append(GpioPin(
|
|
name=f"PD{pin_num}",
|
|
pin_id=f"PD{pin_num}",
|
|
direction=direction,
|
|
layer="stm32"
|
|
))
|
|
|
|
return pins
|
|
|
|
|
|
# ===================================================================
|
|
# FPGA radar_params.vh parser
|
|
# ===================================================================
|
|
|
|
def parse_radar_params_vh() -> dict[str, int]:
|
|
"""
|
|
Parse `define values from radar_params.vh.
|
|
|
|
Returns dict like {"RP_FFT_SIZE": 2048, "RP_DECIMATION_FACTOR": 4, ...}.
|
|
Only parses defines with simple integer or Verilog literal values.
|
|
Skips bit-width prefixed literals (e.g. 2'b00) — returns the numeric value.
|
|
"""
|
|
path = FPGA_DIR / "radar_params.vh"
|
|
text = path.read_text()
|
|
params: dict[str, int] = {}
|
|
|
|
for m in re.finditer(
|
|
r'`define\s+(RP_\w+)\s+(\S+)', text
|
|
):
|
|
name = m.group(1)
|
|
val_str = m.group(2).rstrip()
|
|
|
|
# Skip non-numeric defines (like RADAR_PARAMS_VH guard)
|
|
if name == "RADAR_PARAMS_VH":
|
|
continue
|
|
|
|
# Handle Verilog bit-width literals: 2'b00, 8'h30, etc.
|
|
verilog_lit = re.match(r"\d+'([bhd])(\w+)", val_str)
|
|
if verilog_lit:
|
|
base_char = verilog_lit.group(1)
|
|
digits = verilog_lit.group(2)
|
|
base = {"b": 2, "h": 16, "d": 10}[base_char]
|
|
params[name] = int(digits, base)
|
|
continue
|
|
|
|
# Handle parenthesized expressions like (`RP_X * `RP_Y)
|
|
if "(" in val_str or "`" in val_str:
|
|
continue # Skip computed defines
|
|
|
|
# Plain integer
|
|
try:
|
|
params[name] = int(val_str)
|
|
except ValueError:
|
|
continue
|
|
|
|
return params
|