PLFM_RADAR

tb

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

ad9484_interface_400m.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cdc_modules.v

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2026-03-09 00:17:39 +00:00

chirp_lut_init.v

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2026-03-09 00:17:39 +00:00

chirp_memory_loader_param.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cic_decimator_4x_enhanced.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

cntrt.xdc

Create cntrt.xdc

2026-03-10 02:42:15 +00:00

dac_interface_single.v

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2026-03-09 00:17:39 +00:00

ddc_400m.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

ddc_input_interface.v

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2026-03-09 00:17:39 +00:00

doppler_processor.v

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2026-03-09 00:17:39 +00:00

edge_detector.v

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2026-03-09 00:17:39 +00:00

fft_1024_forward.v

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2026-03-09 00:17:39 +00:00

fft_1024_inverse.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

fir_lowpass.v

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2026-03-09 00:17:39 +00:00

frequency_matched_filter.v

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2026-03-09 00:17:39 +00:00

latency_buffer_2159.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

level_shifter_interface.v

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2026-03-10 01:31:50 +00:00

long_chirp_seg0_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg0_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg1_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg2_i.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg2_q.mem

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2026-03-09 00:17:39 +00:00

long_chirp_seg3_i.mem

Add missing long_chirp_seg3 memory files for complete chirp waveform

2026-03-15 18:06:35 +02:00

long_chirp_seg3_q.mem

Add missing long_chirp_seg3 memory files for complete chirp waveform

2026-03-15 18:06:35 +02:00

lvds_to_cmos_400m.v

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2026-03-09 00:17:39 +00:00

matched_filter_multi_segment.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

matched_filter_processing_chain.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

nco_400m_enhanced.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

plfm_chirp_controller.v

Fix 6 RTL bugs in FPGA signal processing chain

2026-03-15 06:14:04 +02:00

radar_mode_controller.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

radar_receiver_final.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00

radar_system_tb.v

Create radar_system_tb.v

2026-03-10 01:35:26 +00:00

radar_system_top.v

Fix CDC timing violations: add synchronizers for all inter-clock crossings

2026-03-15 17:58:14 +02:00

radar_transmitter.v

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2026-03-09 00:17:39 +00:00

range_bin_decimator.v

Add 3 missing FPGA modules with enhanced testbenches (168/168 pass)

2026-03-15 13:37:10 +02:00

short_chirp_i.mem

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2026-03-09 00:17:39 +00:00

short_chirp_q.mem

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2026-03-09 00:17:39 +00:00

usb_data_interface.v

Fix CDC timing violations: add synchronizers for all inter-clock crossings

2026-03-15 17:58:14 +02:00

usb_packet_analyzer.v

Fix synthesis blockers in 9 RTL files for Vivado compatibility

2026-03-15 14:53:35 +02:00

xfft_32.v

Fix 6 RTL files + add xfft_32 stub for successful Vivado synthesis

2026-03-15 17:37:59 +02:00