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19284ac27710383aabb660efc00a0428c087f26a
PLFM_RADAR/9_Firmware/9_2_FPGA
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Jason 19284ac277 Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21 
Build 21 Vivado results extracted and documented:
- WNS +0.156 ns, WHS +0.064 ns, WPWS +0.361 ns (all timing met)
- 6,192 LUTs (4.6%), 9,064 FFs (3.4%), 16 BRAM (4.4%), 139 DSP48E1 (18.8%)
- Total power: 0.732 W
- Barrel-shift twiddle freed 1 DSP (140 -> 139) as expected
- TCL script fix: wrap check_timing in catch (Vivado 2025.2 bug)
- Updated release-notes.html, implementation-log.html, reports.html
2026-03-20 02:21:33 +02:00
..
constraints
Fix Vivado DRC: consolidate data_pending flags into single always block, fix MMCM LOCKED false_path
2026-03-20 01:56:20 +02:00
formal
Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)
2026-03-19 23:54:48 +02:00
scripts
Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21
2026-03-20 02:21:33 +02:00
tb
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
.gitignore
CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
2026-03-19 11:31:46 +02:00
ad9484_interface_400m.v
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
adc_clk_mmcm_integration.md
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
adc_clk_mmcm.v
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
cdc_modules.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
chirp_memory_loader_param.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
cic_decimator_4x_enhanced.v
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
dac_interface_single.v
Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I
2026-03-16 22:24:22 +02:00
ddc_400m.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
ddc_input_interface.v
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
2026-03-16 18:14:06 +02:00
doppler_processor.v
Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)
2026-03-19 10:31:16 +02:00
edge_detector.v
Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator
2026-03-17 13:48:47 +02:00
fft_engine.v
FFT engine: merge SHIFT into WRITE (5→4 cycle butterfly, 20% throughput) + barrel-shift twiddle index
2026-03-20 00:20:59 +02:00
fft_twiddle_32.mem
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
fft_twiddle_1024.mem
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
fir_lowpass.v
FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache
2026-03-19 20:39:01 +02:00
frequency_matched_filter.v
Convert async→sync reset on DSP/BRAM datapath registers for timing closure
2026-03-17 20:11:13 +02:00
latency_buffer.v
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
2026-03-18 01:28:42 +02:00
long_chirp_lut.mem
Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)
2026-03-19 10:31:16 +02:00
long_chirp_seg0_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg0_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg1_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg1_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg2_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg2_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg3_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg3_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
matched_filter_multi_segment.v
Fix matched filter synth errors: overlap_copy_count part-select width, add FSM default
2026-03-19 20:53:29 +02:00
matched_filter_processing_chain.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
nco_400m_enhanced.v
Improve timing margins with targeted datapath register tuning
2026-03-17 23:51:04 +02:00
plfm_chirp_controller.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
radar_mode_controller.v
Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)
2026-03-19 23:54:48 +02:00
radar_receiver_final.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
radar_system_top_te0712_dev.v
Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
2026-03-18 03:57:26 +02:00
radar_system_top_te0713_dev.v
Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments
2026-03-19 16:47:59 +02:00
radar_system_top.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
radar_transmitter.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
range_bin_decimator.v
Fix range_bin_decimator overflow guard priority bug: group completion now takes precedence over overflow guard in ST_PROCESS, ensuring all OUTPUT_BINS outputs are emitted when sufficient input samples exist. Split formal property 5 into 5a (upper bound) and 5b (exact count when start_bin=0), added Cover 4 for overflow guard path, reduced BMC depth to 50.
2026-03-17 15:41:06 +02:00
run_regression.sh
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
short_chirp_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
short_chirp_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
usb_data_interface.v
Fix Vivado DRC: consolidate data_pending flags into single always block, fix MMCM LOCKED false_path
2026-03-20 01:56:20 +02:00
xfft_32.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00