Fix doppler_processor windowing pipeline bugs + multi-segment buffer_write_ptr bug, add co-sim suites
RTL bug fixes:
- doppler_processor.v: Add S_PRE_READ state to prime BRAM pipeline, restructure
S_LOAD_FFT with sub-counter staging, fix BRAM address off-by-one
(read_doppler_index <= fft_sample_counter + 2, was +1). All 3 Doppler
co-sim scenarios now achieve BIT-PERFECT match (correlation=1.0, energy=1.0).
- matched_filter_multi_segment.v: Move buffer_write_ptr >= SEGMENT_ADVANCE check
outside if(ddc_valid) block to prevent FSM deadlock. 32/32 tests PASS.
New co-simulation infrastructure:
- Doppler co-sim: tb_doppler_cosim.v (14/14 structural checks),
gen_doppler_golden.py (3 scenarios: stationary/moving/two_targets),
compare_doppler.py (bit-perfect thresholds)
- Multi-segment co-sim: tb_multiseg_cosim.v (32/32), gen_multiseg_golden.py
with short and long test vector suites
Jason
17731dd482