Files

T

Jason fcf3999e39 Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

Split cdc_adc_to_processing reset_n into src_reset_n/dst_reset_n so source
and destination clock domains use correctly-synchronized resets. Previously
cdc_chirp_counter's destination-side sync chain (100MHz) was reset by
sys_reset_120m_n (120MHz domain), causing 30 CDC critical warnings.

RTL changes:
- cdc_modules.v: split reset port, source logic uses src_reset_n,
  destination sync chains + output logic use dst_reset_n
- radar_system_top.v: cdc_chirp_counter gets proper per-domain resets
- ddc_400m.v: CDC_FIR_i/q use reset_n_400m (src) and reset_n (dst)
- formal/fv_cdc_adc.v: updated wrapper for new port interface

Build 7 fixes (previously untouched):
- radar_transmitter.v: SPI level-shifter assigns, STM32 GPIO CDC sync
- latency_buffer_2159.v: BRAM read registration
- constraints: ft601 IOB -quiet fix
- tb_latency_buffer.v: updated for BRAM changes

Testbench hardening (tb_cdc_modules.v, +31 new assertions):
- A5-A7: split-domain reset tests (staggered deassertion, independent
  dst reset while src active — catches the P0 bug class)
- A8: port connectivity (no X/Z on outputs)
- B7: cdc_single_bit port connectivity
- C6: cdc_handshake reset recovery + port connectivity

Full regression: 13/13 test suites pass (257 total assertions).

2026-03-17 19:38:09 +02:00

README.md

Widen ft601_be to [3:0] for 32-bit FT601 mode, fix NCO XSim TB

2026-03-16 23:17:38 +02:00

xc7a50t_ftg256.xdc

Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I

2026-03-16 22:24:22 +02:00

xc7a200t_fbg484.xdc

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

README.md

AERIS-10 FPGA Constraint Files

Two Targets

File	Device	Package	Purpose
`xc7a50t_ftg256.xdc`	XC7A50T-2FTG256I	FTG256 (256-ball BGA)	Upstream author's board (copy of `cntrt.xdc`)
`xc7a200t_fbg484.xdc`	XC7A200T-2FBG484I	FBG484 (484-ball BGA)	Production board (new PCB design)

Why Two Files

The upstream prototype uses a smaller XC7A50T in an FTG256 package. The production AERIS-10 radar migrates to the XC7A200T for more logic, BRAM, and DSP resources. The two devices have completely different packages and pin names, so each needs its own constraint file. Both files constrain the same RTL top module (radar_system_top.v).

Bank Voltage Assignments

XC7A50T-FTG256 (Upstream)

Bank	VCCO	Signals
0	3.3V	JTAG, flash CS
14	3.3V	ADC LVDS (LVDS_33), SPI flash
15	3.3V	DAC, clocks, STM32 3.3V SPI, DIG bus
34	1.8V	ADAR1000 control, SPI 1.8V side
35	3.3V	Unused (no signal connections)

XC7A200T-FBG484 (Production)

Bank	VCCO	Used/Avail	Signals
13	3.3V	17/35	Debug overflow (doppler bins, range bins, status)
14	2.5V	19/50	ADC LVDS_25 + DIFF_TERM, ADC power-down
15	3.3V	27/50	System clocks (100M, 120M), DAC, RF, STM32 3.3V SPI, DIG bus
16	3.3V	50/50	FT601 USB 3.0 (32-bit data + byte enable + control)
34	1.8V	19/50	ADAR1000 beamformer control, SPI 1.8V side
35	3.3V	50/50	Status outputs (beam position, chirp, doppler data bus)

Signal Differences Between Targets

Signal	Upstream (FTG256)	Production (FBG484)
FT601 USB	Unwired (chip placed, no nets)	Fully wired, Bank 16
`dac_clk`	Not connected (DAC clocked by AD9523 directly)	Routed, FPGA drives DAC
`ft601_be` width	`[1:0]` in upstream RTL	`[3:0]` (RTL updated)
ADC LVDS standard	LVDS_33 (3.3V bank)	LVDS_25 (2.5V bank, better quality)
Status/debug outputs	No physical pins (commented out)	All routed to Banks 35 + 13

How to Select in Vivado

In the Vivado project, only one XDC should be active at a time:

Add both files to the project: File > Add Sources > Add Constraints
In the Sources panel, right-click the XDC you do NOT want and select Set File Properties > Enabled = false (or remove it from the active constraint set)
Alternatively, use two separate constraint sets and switch between them

For TCL-based flows:

# For production target:
read_xdc constraints/xc7a200t_fbg484.xdc

# For upstream target:
read_xdc constraints/xc7a50t_ftg256.xdc

Notes

The production XDC pin assignments are recommended for the new PCB. The PCB designer should follow this allocation.
Bank 16 (FT601) is fully utilized at 50/50 pins. No room for expansion on that bank.
Bank 35 (status/debug) is also at capacity (50/50). Additional debug signals should use Bank 13 spare pins (18 remaining).
Clock inputs are placed on MRCC (Multi-Region Clock Capable) pins to ensure proper clock tree access.