FlintyLemming/PLFM_RADAR
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PLFM_RADAR/9_Firmware/9_2_FPGA
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Jason 0745cc4f48 Pipeline CFAR noise computation: break critical path for timing closure 
Split ST_CFAR_THR into two pipeline stages (THR + MUL) to fix Build 23
timing violation (WNS = -0.309 ns). The combinational path from
leading_sum through GO/SO cross-multiply into alpha*noise DSP was too
long for 10 ns.

New pipeline:
  ST_CFAR_THR: register noise_sum_comb (mode select + cross-multiply)
  ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP
  ST_CFAR_CMP: compare + update window (unchanged)

3 cycles per CUT instead of 2 (~85 us vs 70 us per frame, negligible).
All detection results identical: 23/23 CFAR standalone, 22/22 full
regression, 3/3 real-data co-sim (5137/5137 exact match) PASS.
2026-03-20 05:24:08 +02:00
..
constraints
Fix Vivado DRC: consolidate data_pending flags into single always block, fix MMCM LOCKED false_path
2026-03-20 01:56:20 +02:00
formal
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
scripts
Build 21 docs + TCL fix: WNS +0.156ns, 139 DSP, tag v0.1.4-build21
2026-03-20 02:21:33 +02:00
tb
Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)
2026-03-20 04:57:34 +02:00
.gitignore
CIC comb pipeline registers, BUFG sim guard, system TB fix, regression runner
2026-03-19 11:31:46 +02:00
ad9484_interface_400m.v
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
adc_clk_mmcm_integration.md
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
adc_clk_mmcm.v
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
cdc_modules.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
cfar_ca.v
Pipeline CFAR noise computation: break critical path for timing closure
2026-03-20 05:24:08 +02:00
chirp_memory_loader_param.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
cic_decimator_4x_enhanced.v
Gap 7 MMCM jitter cleaner + CIC comb CREG pipeline + XDC clock-name fix
2026-03-19 22:59:46 +02:00
dac_interface_single.v
Migrate hardware platform from XC7A50T to XC7A200T-2FBG484I
2026-03-16 22:24:22 +02:00
ddc_400m.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
ddc_input_interface.v
Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale
2026-03-16 18:14:06 +02:00
doppler_processor.v
Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)
2026-03-19 10:31:16 +02:00
edge_detector.v
Fix all 10 CDC bugs from report_cdc audit, add overflow guard in range_bin_decimator
2026-03-17 13:48:47 +02:00
fft_engine.v
FFT engine: merge SHIFT into WRITE (5→4 cycle butterfly, 20% throughput) + barrel-shift twiddle index
2026-03-20 00:20:59 +02:00
fft_twiddle_32.mem
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
fft_twiddle_1024.mem
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
fir_lowpass.v
FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache
2026-03-19 20:39:01 +02:00
frequency_matched_filter.v
Convert async→sync reset on DSP/BRAM datapath registers for timing closure
2026-03-17 20:11:13 +02:00
latency_buffer.v
Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts
2026-03-18 01:28:42 +02:00
long_chirp_lut.mem
Fix Bug #11 (platform SPI transmit-only), FPGA B2 (chirp BRAM migration), FPGA B3 (DSP48 pipelining)
2026-03-19 10:31:16 +02:00
long_chirp_seg0_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg0_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg1_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg1_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg2_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg2_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg3_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
long_chirp_seg3_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
matched_filter_multi_segment.v
Fix matched filter synth errors: overlap_copy_count part-select width, add FSM default
2026-03-19 20:53:29 +02:00
matched_filter_processing_chain.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00
nco_400m_enhanced.v
Improve timing margins with targeted datapath register tuning
2026-03-17 23:51:04 +02:00
plfm_chirp_controller.v
E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)
2026-03-20 01:45:00 +02:00
radar_mode_controller.v
Gap 2 GUI Settings: runtime chirp timing, stream control gating, status readback (18/18 FPGA, 20/20 MCU)
2026-03-19 23:54:48 +02:00
radar_receiver_final.v
Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)
2026-03-20 04:57:34 +02:00
radar_system_top_te0712_dev.v
Add TE0712/TE0701 split target with dedicated top, XDC, and build flow
2026-03-18 03:57:26 +02:00
radar_system_top_te0713_dev.v
Update heartbeat dev target: LVCMOS33 for Bank 16 FT601 compat, add comments
2026-03-19 16:47:59 +02:00
radar_system_top.v
Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)
2026-03-20 04:57:34 +02:00
radar_transmitter.v
Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions
2026-03-17 19:38:09 +02:00
range_bin_decimator.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
run_regression.sh
Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)
2026-03-20 04:57:34 +02:00
rx_gain_control.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
short_chirp_i.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
short_chirp_q.mem
Regenerate chirp .mem files, add USB testbench, convert radar_system_tb to Verilog-2001
2026-03-16 19:53:40 +02:00
usb_data_interface.v
Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)
2026-03-20 04:38:35 +02:00
xfft_32.v
Replace FFT stubs with synthesizable radix-2 DIT engine, fix BRAM inference
2026-03-16 10:25:07 +02:00