Previous output_delay of 11.667 ns was a synthetic back-calculation
(period − 5 ns), not a datasheet number. It over-constrained FPGA
launch by ~8 ns vs the actual FT2232H 245-Sync FIFO setup requirement.
Per FTDI TN_167:
- t_su (data to CLKOUT rising): 3.5 ns (was 11.667 — too tight)
- t_h (data hold after CLKOUT): 1.0 ns (was 0.0 — no hold check)
- t_co (CLKOUT to data valid): 10.0 ns (was 9.667 — close)
- t_coh (CLKOUT to data hold): 0.5 ns (was 0.0 — no hold check)
NB: values must be verified against the exact TN_167 revision in use
before shipping. If the engineer's revision differs, numbers change
but the direction (big relaxation of output_delay_max) is correct.
Jason
0496291fc5