Jason
e93bc33c6c
Fix 1: Combinational magnitude + non-sticky detection flag (tb: 23/23) Fix 2: Rename all cfar_* signals to detect_*/threshold_* (honest naming) Fix 3: New rx_gain_control.v between DDC and FFT, opcode 0x16 (tb: 33/33) Fix 4: Clamp host_chirps_per_elev to DOPPLER_FFT_SIZE, error flag (E2E: 54/54) Fix 5: Decimator watchdog timeout, 256-cycle limit (tb: 63/63) Fix 6: Remove bypass_mode dead code from ddc_400m.v (DDC tb: 21/21) Fix 7: Range-mode register 0x20 with status readback (USB tb: 77/77)
96 lines
3.5 KiB
Verilog
96 lines
3.5 KiB
Verilog
`timescale 1ns / 1ps
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/**
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* rx_gain_control.v
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*
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* Host-configurable digital gain control for the receive path.
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* Placed between DDC output (ddc_input_interface) and matched filter input.
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*
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* Features:
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* - Bidirectional power-of-2 gain shift (arithmetic shift)
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* - gain_shift[3] = direction: 0 = left shift (amplify), 1 = right shift (attenuate)
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* - gain_shift[2:0] = amount: 0..7 bits
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* - Symmetric saturation to ±32767 on overflow (left shift only)
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* - Saturation counter: 8-bit, counts samples that clipped (wraps at 255)
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* - 1-cycle latency, valid-in/valid-out pipeline
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* - Zero-overhead pass-through when gain_shift == 0
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*
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* Intended insertion point in radar_receiver_final.v:
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* ddc_input_interface → rx_gain_control → matched_filter_multi_segment
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*/
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module rx_gain_control (
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input wire clk,
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input wire reset_n,
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// Data input (from DDC / ddc_input_interface)
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input wire signed [15:0] data_i_in,
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input wire signed [15:0] data_q_in,
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input wire valid_in,
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// Gain configuration (from host via USB command)
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// [3] = direction: 0=amplify (left shift), 1=attenuate (right shift)
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// [2:0] = shift amount: 0..7 bits
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input wire [3:0] gain_shift,
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// Data output (to matched filter)
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output reg signed [15:0] data_i_out,
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output reg signed [15:0] data_q_out,
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output reg valid_out,
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// Diagnostics
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output reg [7:0] saturation_count // Number of clipped samples (wraps at 255)
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);
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// Decompose gain_shift
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wire shift_right = gain_shift[3];
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wire [2:0] shift_amt = gain_shift[2:0];
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// -------------------------------------------------------------------------
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// Combinational shift + saturation
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// -------------------------------------------------------------------------
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// Use wider intermediates to detect overflow on left shift.
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// 24 bits is enough: 16 + 7 shift = 23 significant bits max.
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wire signed [23:0] shifted_i;
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wire signed [23:0] shifted_q;
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assign shifted_i = shift_right ? (data_i_in >>> shift_amt)
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: (data_i_in <<< shift_amt);
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assign shifted_q = shift_right ? (data_q_in >>> shift_amt)
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: (data_q_in <<< shift_amt);
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// Saturation: clamp to signed 16-bit range [-32768, +32767]
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wire overflow_i = (shifted_i > 24'sd32767) || (shifted_i < -24'sd32768);
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wire overflow_q = (shifted_q > 24'sd32767) || (shifted_q < -24'sd32768);
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wire signed [15:0] sat_i = overflow_i ? (shifted_i[23] ? -16'sd32768 : 16'sd32767)
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: shifted_i[15:0];
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wire signed [15:0] sat_q = overflow_q ? (shifted_q[23] ? -16'sd32768 : 16'sd32767)
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: shifted_q[15:0];
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// -------------------------------------------------------------------------
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// Registered output stage (1-cycle latency)
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// -------------------------------------------------------------------------
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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data_i_out <= 16'sd0;
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data_q_out <= 16'sd0;
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valid_out <= 1'b0;
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saturation_count <= 8'd0;
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end else begin
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valid_out <= valid_in;
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if (valid_in) begin
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data_i_out <= sat_i;
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data_q_out <= sat_q;
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// Count clipped samples (either channel clipping counts as 1)
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if ((overflow_i || overflow_q) && (saturation_count != 8'hFF))
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saturation_count <= saturation_count + 8'd1;
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end
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end
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end
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endmodule
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