Jason
476 lines
16 KiB
Verilog
476 lines
16 KiB
Verilog
`timescale 1ns / 1ps
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module radar_receiver_final (
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input wire clk, // 100MHz
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input wire reset_n,
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// ADC Physical Interface (LVDS Inputs)
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input wire [7:0] adc_d_p, // ADC Data P (LVDS)
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input wire [7:0] adc_d_n, // ADC Data N (LVDS)
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input wire adc_dco_p, // Data Clock Output P (400MHz LVDS)
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input wire adc_dco_n, // Data Clock Output N (400MHz LVDS)
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output wire adc_pwdn,
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// Chirp counter from transmitter (for frame sync and matched filter)
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input wire [5:0] chirp_counter,
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output wire [31:0] doppler_output,
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output wire doppler_valid,
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output wire [4:0] doppler_bin,
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output wire [5:0] range_bin,
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// Matched filter range profile output (for USB)
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output wire signed [15:0] range_profile_i_out,
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output wire signed [15:0] range_profile_q_out,
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output wire range_profile_valid_out,
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// Host command inputs (Gap 4: USB Read Path, CDC-synchronized)
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// CDC-synchronized in radar_system_top.v before reaching here
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input wire [1:0] host_mode, // Radar mode: 00=STM32, 01=auto-scan, 10=single-chirp
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input wire host_trigger, // Single-chirp trigger pulse (1 clk cycle)
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// Gap 2: Host-configurable chirp timing (CDC-synchronized in radar_system_top.v)
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input wire [15:0] host_long_chirp_cycles,
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input wire [15:0] host_long_listen_cycles,
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input wire [15:0] host_guard_cycles,
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input wire [15:0] host_short_chirp_cycles,
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input wire [15:0] host_short_listen_cycles,
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input wire [5:0] host_chirps_per_elev,
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// Digital gain control (Fix 3: between DDC output and matched filter)
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// [3]=direction: 0=amplify(left shift), 1=attenuate(right shift)
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// [2:0]=shift amount: 0..7 bits. Default 0 = pass-through.
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input wire [3:0] host_gain_shift,
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// STM32 toggle signals for mode 00 (STM32-driven) pass-through.
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// These are CDC-synchronized in radar_system_top.v / radar_transmitter.v
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// before reaching this module. In mode 00, the RX mode controller uses
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// these to synchronize receiver processing with STM32-timed chirps.
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input wire stm32_new_chirp_rx,
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input wire stm32_new_elevation_rx,
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input wire stm32_new_azimuth_rx,
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// CFAR integration: expose Doppler frame_complete to top level
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output wire doppler_frame_done_out,
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// Ground clutter removal controls
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input wire host_mti_enable, // 1=MTI active, 0=pass-through
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input wire [2:0] host_dc_notch_width, // DC notch: zero Doppler bins within ±width of DC
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// ADC raw data tap (clk_100m domain, post-DDC, for self-test / debug)
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output wire [15:0] dbg_adc_i, // DDC output I (16-bit signed, 100 MHz)
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output wire [15:0] dbg_adc_q, // DDC output Q (16-bit signed, 100 MHz)
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output wire dbg_adc_valid // DDC output valid (100 MHz)
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);
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// ========== INTERNAL SIGNALS ==========
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wire use_long_chirp;
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// NOTE: chirp_counter is now an input port (was undriven internal wire — bug NEW-1)
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wire chirp_start;
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wire azimuth_change;
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wire elevation_change;
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// Mode controller outputs → matched_filter_multi_segment
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wire mc_new_chirp;
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wire mc_new_elevation;
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wire mc_new_azimuth;
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wire [1:0] segment_request;
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wire mem_request;
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wire [15:0] ref_i, ref_q;
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wire mem_ready;
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wire [15:0] adc_i_scaled, adc_q_scaled;
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wire adc_valid_sync;
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// Gain-controlled signals (between DDC output and matched filter)
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wire signed [15:0] gc_i, gc_q;
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wire gc_valid;
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wire [7:0] gc_saturation_count; // Diagnostic: clipped sample counter
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// Reference signals for the processing chain
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wire [15:0] long_chirp_real, long_chirp_imag;
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wire [15:0] short_chirp_real, short_chirp_imag;
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// ========== DOPPLER PROCESSING SIGNALS ==========
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wire [31:0] range_data_32bit;
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wire range_data_valid;
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wire new_chirp_frame;
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// Doppler processor outputs
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wire [31:0] doppler_spectrum;
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wire doppler_spectrum_valid;
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wire [4:0] doppler_bin_out;
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wire doppler_processing;
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wire doppler_frame_done;
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assign doppler_frame_done_out = doppler_frame_done;
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// ========== RANGE BIN DECIMATOR SIGNALS ==========
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wire signed [15:0] decimated_range_i;
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wire signed [15:0] decimated_range_q;
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wire decimated_range_valid;
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wire [5:0] decimated_range_bin;
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// ========== MTI CANCELLER SIGNALS ==========
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wire signed [15:0] mti_range_i;
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wire signed [15:0] mti_range_q;
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wire mti_range_valid;
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wire [5:0] mti_range_bin;
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wire mti_first_chirp;
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// ========== RADAR MODE CONTROLLER SIGNALS ==========
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wire rmc_scanning;
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wire rmc_scan_complete;
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wire [5:0] rmc_chirp_count;
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wire [5:0] rmc_elevation_count;
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wire [5:0] rmc_azimuth_count;
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// ========== MODULE INSTANTIATIONS ==========
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// 0. Radar Mode Controller — drives chirp/elevation/azimuth timing signals
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// Default mode: auto-scan (2'b01). Change to 2'b00 for STM32 pass-through.
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radar_mode_controller rmc (
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.clk(clk),
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.reset_n(reset_n),
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.mode(host_mode), // Controlled by host via USB (default: 2'b01 auto-scan)
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.stm32_new_chirp(stm32_new_chirp_rx),
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.stm32_new_elevation(stm32_new_elevation_rx),
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.stm32_new_azimuth(stm32_new_azimuth_rx),
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.trigger(host_trigger), // Single-chirp trigger from host via USB
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// Gap 2: Runtime-configurable timing from host USB commands
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.cfg_long_chirp_cycles(host_long_chirp_cycles),
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.cfg_long_listen_cycles(host_long_listen_cycles),
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.cfg_guard_cycles(host_guard_cycles),
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.cfg_short_chirp_cycles(host_short_chirp_cycles),
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.cfg_short_listen_cycles(host_short_listen_cycles),
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.cfg_chirps_per_elev(host_chirps_per_elev),
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.use_long_chirp(use_long_chirp),
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.mc_new_chirp(mc_new_chirp),
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.mc_new_elevation(mc_new_elevation),
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.mc_new_azimuth(mc_new_azimuth),
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.chirp_count(rmc_chirp_count),
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.elevation_count(rmc_elevation_count),
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.azimuth_count(rmc_azimuth_count),
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.scanning(rmc_scanning),
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.scan_complete(rmc_scan_complete)
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);
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wire clk_400m;
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// NOTE: lvds_to_cmos_400m removed — ad9484_interface_400m now provides
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// the buffered 400MHz DCO clock via adc_dco_bufg, avoiding duplicate
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// IBUFDS instantiations on the same LVDS clock pair.
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// 1. ADC + CDC + AGC
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// CMOS Output Interface (400MHz Domain)
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wire [7:0] adc_data_cmos; // 8-bit ADC data (CMOS, from ad9484_interface_400m)
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wire adc_valid; // Data valid signal
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// ADC power-down control (directly tie low = ADC always on)
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assign adc_pwdn = 1'b0;
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ad9484_interface_400m adc (
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.adc_d_p(adc_d_p),
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.adc_d_n(adc_d_n),
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.adc_dco_p(adc_dco_p),
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.adc_dco_n(adc_dco_n),
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.sys_clk(clk),
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.reset_n(reset_n),
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.adc_data_400m(adc_data_cmos),
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.adc_data_valid_400m(adc_valid),
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.adc_dco_bufg(clk_400m)
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);
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// NOTE: The cdc_adc_to_processing instance that was here used src_clk=dst_clk=clk_400m
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// (same clock domain — no crossing). Gray-code CDC on same-clock with fast-changing
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// ADC data corrupts samples because Gray coding only guarantees safe transfer of
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// values that change by 1 LSB at a time. The real 400MHz→100MHz CDC crossing is
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// handled inside ddc_400m_enhanced via CIC decimation + CDC_FIR instances.
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// Removed: cdc_adc_to_processing instance. ADC data now goes directly to DDC.
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// 2. DDC Input Interface
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wire signed [17:0] ddc_out_i;
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wire signed [17:0] ddc_out_q;
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wire ddc_valid_i;
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wire ddc_valid_q;
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ddc_400m_enhanced ddc(
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.clk_400m(clk_400m), // 400MHz clock from ADC DCO
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.clk_100m(clk), // 100MHz system clock //used by the 2 FIR
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.reset_n(reset_n),
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.adc_data(adc_data_cmos), // ADC data at 400MHz (direct from ADC interface)
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.adc_data_valid_i(adc_valid), // Valid at 400MHz
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.adc_data_valid_q(adc_valid), // Valid at 400MHz
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.baseband_i(ddc_out_i), // I output at 100MHz
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.baseband_q(ddc_out_q), // Q output at 100MHz
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.baseband_valid_i(ddc_valid_i), // Valid at 100MHz
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.baseband_valid_q(ddc_valid_q),
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.mixers_enable(1'b1)
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);
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ddc_input_interface ddc_if (
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.clk(clk),
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.reset_n(reset_n),
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.ddc_i(ddc_out_i),
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.ddc_q(ddc_out_q),
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.valid_i(ddc_valid_i),
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.valid_q(ddc_valid_q),
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.adc_i(adc_i_scaled),
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.adc_q(adc_q_scaled),
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.adc_valid(adc_valid_sync),
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.data_sync_error()
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);
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// 2b. Digital Gain Control (Fix 3)
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// Host-configurable power-of-2 shift between DDC output and matched filter.
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// Default gain_shift=0 → pass-through (no behavioral change from baseline).
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rx_gain_control gain_ctrl (
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.clk(clk),
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.reset_n(reset_n),
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.data_i_in(adc_i_scaled),
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.data_q_in(adc_q_scaled),
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.valid_in(adc_valid_sync),
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.gain_shift(host_gain_shift),
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.data_i_out(gc_i),
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.data_q_out(gc_q),
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.valid_out(gc_valid),
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.saturation_count(gc_saturation_count)
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);
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// 3. Dual Chirp Memory Loader
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wire [9:0] sample_addr_from_chain;
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chirp_memory_loader_param chirp_mem (
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.clk(clk),
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.reset_n(reset_n),
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.segment_select(segment_request),
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.mem_request(mem_request),
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.use_long_chirp(use_long_chirp),
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.sample_addr(sample_addr_from_chain),
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.ref_i(ref_i),
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.ref_q(ref_q),
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.mem_ready(mem_ready)
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);
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// Sample address generator
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reg [9:0] sample_addr_reg;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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sample_addr_reg <= 0;
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end else if (mem_request) begin
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sample_addr_reg <= sample_addr_reg + 1;
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if (sample_addr_reg == 1023) sample_addr_reg <= 0;
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end
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end
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// sample_addr_wire removed — was unused implicit wire (synthesis warning)
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// 4. CRITICAL: Reference Chirp Latency Buffer
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// This aligns reference data with FFT output (2159 cycle delay)
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wire [15:0] delayed_ref_i, delayed_ref_q;
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wire mem_ready_delayed;
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latency_buffer #(
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.DATA_WIDTH(32), // 16-bit I + 16-bit Q
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.LATENCY(3187)
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) ref_latency_buffer (
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.clk(clk),
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.reset_n(reset_n),
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.data_in({ref_i, ref_q}),
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.valid_in(mem_request),
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.data_out({delayed_ref_i, delayed_ref_q}),
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.valid_out(mem_ready_delayed)
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);
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// Assign delayed reference signals
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assign long_chirp_real = delayed_ref_i;
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assign long_chirp_imag = delayed_ref_q;
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assign short_chirp_real = delayed_ref_i;
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assign short_chirp_imag = delayed_ref_q;
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// 5. Dual Chirp Matched Filter
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wire signed [15:0] range_profile_i;
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wire signed [15:0] range_profile_q;
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wire range_valid;
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// Expose matched filter output to top level for USB range profile
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assign range_profile_i_out = range_profile_i;
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assign range_profile_q_out = range_profile_q;
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assign range_profile_valid_out = range_valid;
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matched_filter_multi_segment mf_dual (
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.clk(clk),
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.reset_n(reset_n),
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.ddc_i({{2{gc_i[15]}}, gc_i}),
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.ddc_q({{2{gc_q[15]}}, gc_q}),
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.ddc_valid(gc_valid),
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.use_long_chirp(use_long_chirp),
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.chirp_counter(chirp_counter),
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.mc_new_chirp(mc_new_chirp),
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.mc_new_elevation(mc_new_elevation),
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.mc_new_azimuth(mc_new_azimuth),
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.long_chirp_real(delayed_ref_i), // From latency buffer
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.long_chirp_imag(delayed_ref_q),
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.short_chirp_real(delayed_ref_i), // Same for short chirp
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.short_chirp_imag(delayed_ref_q),
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.segment_request(segment_request),
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.mem_request(mem_request),
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.sample_addr_out(sample_addr_from_chain),
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.mem_ready(mem_ready),
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.pc_i_w(range_profile_i),
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.pc_q_w(range_profile_q),
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.pc_valid_w(range_valid)
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);
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// ========== CRITICAL: RANGE BIN DECIMATOR ==========
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// Convert 1024 range bins to 64 bins for Doppler
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range_bin_decimator #(
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.INPUT_BINS(1024),
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.OUTPUT_BINS(64),
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.DECIMATION_FACTOR(16)
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) range_decim (
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.clk(clk),
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.reset_n(reset_n),
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.range_i_in(range_profile_i),
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.range_q_in(range_profile_q),
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.range_valid_in(range_valid),
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.range_i_out(decimated_range_i),
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.range_q_out(decimated_range_q),
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.range_valid_out(decimated_range_valid),
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.range_bin_index(decimated_range_bin),
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.decimation_mode(2'b01), // Peak detection mode
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.start_bin(10'd0),
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.watchdog_timeout() // Diagnostic — unconnected (monitored via ILA if needed)
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);
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// ========== MTI CANCELLER (Ground Clutter Removal) ==========
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// 2-pulse canceller: subtracts previous chirp from current chirp.
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// H(z) = 1 - z^{-1} → null at DC Doppler, removes stationary clutter.
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// When host_mti_enable=0: transparent pass-through.
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mti_canceller #(
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.NUM_RANGE_BINS(64),
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.DATA_WIDTH(16)
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) mti_inst (
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.clk(clk),
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.reset_n(reset_n),
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.range_i_in(decimated_range_i),
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.range_q_in(decimated_range_q),
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.range_valid_in(decimated_range_valid),
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.range_bin_in(decimated_range_bin),
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.range_i_out(mti_range_i),
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.range_q_out(mti_range_q),
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.range_valid_out(mti_range_valid),
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.range_bin_out(mti_range_bin),
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.mti_enable(host_mti_enable),
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.mti_first_chirp(mti_first_chirp)
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);
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// ========== FRAME SYNC USING chirp_counter ==========
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reg [5:0] chirp_counter_prev;
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reg new_frame_pulse;
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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chirp_counter_prev <= 6'd0;
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new_frame_pulse <= 1'b0;
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end else begin
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// Default: no pulse
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new_frame_pulse <= 1'b0;
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// Dynamic frame detection using host_chirps_per_elev.
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// Detect frame boundary when chirp_counter changes AND is a
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// multiple of host_chirps_per_elev (0, N, 2N, 3N, ...).
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// Uses a modulo counter that resets at host_chirps_per_elev.
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if (chirp_counter != chirp_counter_prev) begin
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if (chirp_counter == 6'd0 ||
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chirp_counter == host_chirps_per_elev ||
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chirp_counter == {host_chirps_per_elev, 1'b0}) begin
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new_frame_pulse <= 1'b1;
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end
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end
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// Store previous value
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chirp_counter_prev <= chirp_counter;
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end
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end
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assign new_chirp_frame = new_frame_pulse;
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// ========== DATA PACKING FOR DOPPLER ==========
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// Use MTI-filtered data (or pass-through if MTI disabled)
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assign range_data_32bit = {mti_range_q, mti_range_i};
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assign range_data_valid = mti_range_valid;
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// ========== DOPPLER PROCESSOR ==========
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doppler_processor_optimized #(
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.DOPPLER_FFT_SIZE(32),
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.RANGE_BINS(64),
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.CHIRPS_PER_FRAME(32) // MUST MATCH YOUR ACTUAL FRAME SIZE!
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) doppler_proc (
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.clk(clk),
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.reset_n(reset_n),
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.range_data(range_data_32bit),
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.data_valid(range_data_valid),
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.new_chirp_frame(new_chirp_frame),
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// Outputs
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.doppler_output(doppler_output),
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.doppler_valid(doppler_valid),
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.doppler_bin(doppler_bin),
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.range_bin(range_bin),
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// Status
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.processing_active(doppler_processing),
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.frame_complete(doppler_frame_done),
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.status()
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);
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// ========== OUTPUT CONNECTIONS ==========
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// doppler_output, doppler_valid, doppler_bin, range_bin are directly
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// connected to doppler_proc ports above
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// ========== STATUS ==========
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// ========== DEBUG AND VERIFICATION ==========
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reg [31:0] frame_counter;
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reg [5:0] chirps_in_current_frame;
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|
|
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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frame_counter <= 0;
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chirps_in_current_frame <= 0;
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end else begin
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|
// Count chirps in current frame
|
|
if (range_data_valid && decimated_range_bin == 0) begin
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|
// First range bin of a chirp
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|
chirps_in_current_frame <= chirps_in_current_frame + 1;
|
|
end
|
|
|
|
// Detect frame completion
|
|
if (new_chirp_frame) begin
|
|
frame_counter <= frame_counter + 1;
|
|
`ifdef SIMULATION
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|
$display("[TOP] Frame %0d started. Previous frame had %0d chirps",
|
|
frame_counter, chirps_in_current_frame);
|
|
`endif
|
|
chirps_in_current_frame <= 0;
|
|
end
|
|
|
|
// Monitor chirp counter pattern
|
|
if (chirp_counter != chirp_counter_prev) begin
|
|
`ifdef SIMULATION
|
|
$display("[TOP] chirp_counter: %0d ? %0d",
|
|
chirp_counter_prev, chirp_counter);
|
|
`endif
|
|
end
|
|
end
|
|
end
|
|
|
|
|
|
// ========== ADC DEBUG TAP (for self-test / bring-up) ==========
|
|
assign dbg_adc_i = adc_i_scaled;
|
|
assign dbg_adc_q = adc_q_scaled;
|
|
assign dbg_adc_valid = adc_valid_sync;
|
|
|
|
endmodule |