Jason
5fd632bc47
CDC fixes across 6 RTL files based on post-implementation report_cdc analysis:
- P0: sync stm32_mixers_enable and new_chirp_pulse to clk_120m via toggle CDC
in radar_transmitter, add ft601 reset synchronizer and USB holding
registers with proper edge detection in usb_data_interface
- P1: add ASYNC_REG to edge_detector, convert new_chirp_frame to toggle CDC,
fix USB valid edge detect to use fully-synced signal
- P2: register Gray encoding in cdc_adc_to_processing source domain, sync
ft601_txe and stm32_mixers_enable for status_reg in radar_system_top
- Safety: add in_bin_count overflow guard in range_bin_decimator to prevent
downstream BRAM corruption
All 13 regression test suites pass (159 individual tests).
26 lines
818 B
Verilog
26 lines
818 B
Verilog
module edge_detector_enhanced (
|
|
input wire clk,
|
|
input wire reset_n,
|
|
input wire signal_in,
|
|
output wire rising_falling_edge
|
|
);
|
|
|
|
(* ASYNC_REG = "TRUE" *) reg signal_in_prev;
|
|
(* ASYNC_REG = "TRUE" *) reg signal_in_prev2;
|
|
|
|
always @(posedge clk or negedge reset_n) begin
|
|
if (!reset_n) begin
|
|
signal_in_prev <= 1'b0;
|
|
signal_in_prev2 <= 1'b0;
|
|
end else begin
|
|
signal_in_prev <= signal_in;
|
|
signal_in_prev2 <= signal_in_prev;
|
|
end
|
|
end
|
|
|
|
// Rising edge: was low, now high (with synchronization) signal_in_prev & ~signal_in_prev2;
|
|
//Falling edge: was high, now low (with synchronization) falling_edge = ~signal_in_prev & signal_in_prev2
|
|
assign rising_falling_edge = (signal_in_prev & ~signal_in_prev2)|(~signal_in_prev & signal_in_prev2);
|
|
|
|
|
|
endmodule |