Jason
666527fa7d
Implements the STM32 outer-loop AGC (ADAR1000_AGC) that reads the FPGA saturation flag on DIG_5/PD13 once per radar frame and adjusts the ADAR1000 VGA common gain across all 16 RX channels. Phase 4 — ADAR1000_AGC class (new files): - ADAR1000_AGC.h/.cpp: attack/recovery/holdoff logic, per-channel calibration offsets, effectiveGain() with OOB safety - test_agc_outer_loop.cpp: 13 tests covering saturation, holdoff, recovery, clamping, calibration, SPI spy, reset, mixed sequences Phase 5 — main.cpp integration: - Added #include and global outerAgc instance - AGC update+applyGain call between runRadarPulseSequence() and HAL_IWDG_Refresh() in main loop Build system & shim fixes: - Makefile: added CXX/CXXFLAGS, C++ object rules, TESTS_WITH_CXX in ALL_TESTS (21 total tests) - stm32_hal_mock.h: const uint8_t* for HAL_UART_Transmit (C++ compat), __NOP() macro for host builds - shims/main.h + real main.h: FPGA_DIG5_SAT pin defines All tests passing: MCU 21/21, GUI 92/92, cross-layer 29/29.
145 lines
4.6 KiB
C
145 lines
4.6 KiB
C
/* shim: redirect main.h -> our mock + pin defines from real main.h */
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#ifndef MAIN_H_SHIM
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#define MAIN_H_SHIM
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#include "stm32_hal_mock.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern uint8_t GUI_start_flag_received;
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extern uint8_t USB_Buffer[64];
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void Error_Handler(void);
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/* Pin definitions from real main.h (CubeMX-generated) */
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#define AD9523_PD_Pin GPIO_PIN_3
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#define AD9523_PD_GPIO_Port GPIOF
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#define AD9523_REF_SEL_Pin GPIO_PIN_4
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#define AD9523_REF_SEL_GPIO_Port GPIOF
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#define AD9523_SYNC_Pin GPIO_PIN_5
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#define AD9523_SYNC_GPIO_Port GPIOF
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#define AD9523_RESET_Pin GPIO_PIN_6
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#define AD9523_RESET_GPIO_Port GPIOF
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#define AD9523_CS_Pin GPIO_PIN_7
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#define AD9523_CS_GPIO_Port GPIOF
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#define AD9523_STATUS0_Pin GPIO_PIN_8
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#define AD9523_STATUS0_GPIO_Port GPIOF
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#define AD9523_STATUS1_Pin GPIO_PIN_9
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#define AD9523_STATUS1_GPIO_Port GPIOF
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#define AD9523_EEPROM_SEL_Pin GPIO_PIN_10
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#define AD9523_EEPROM_SEL_GPIO_Port GPIOF
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#define ADAR_1_CS_3V3_Pin GPIO_PIN_0
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#define ADAR_1_CS_3V3_GPIO_Port GPIOA
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#define ADAR_2_CS_3V3_Pin GPIO_PIN_1
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#define ADAR_2_CS_3V3_GPIO_Port GPIOA
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#define ADAR_3_CS_3V3_Pin GPIO_PIN_2
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#define ADAR_3_CS_3V3_GPIO_Port GPIOA
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#define ADAR_4_CS_3V3_Pin GPIO_PIN_3
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#define ADAR_4_CS_3V3_GPIO_Port GPIOA
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#define LED_1_Pin GPIO_PIN_12
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#define LED_1_GPIO_Port GPIOF
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#define LED_2_Pin GPIO_PIN_13
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#define LED_2_GPIO_Port GPIOF
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#define LED_3_Pin GPIO_PIN_14
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#define LED_3_GPIO_Port GPIOF
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#define LED_4_Pin GPIO_PIN_15
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#define LED_4_GPIO_Port GPIOF
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#define EN_P_5V0_PA1_Pin GPIO_PIN_0
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#define EN_P_5V0_PA1_GPIO_Port GPIOG
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#define EN_P_5V0_PA2_Pin GPIO_PIN_1
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#define EN_P_5V0_PA2_GPIO_Port GPIOG
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#define EN_P_5V0_PA3_Pin GPIO_PIN_2
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#define EN_P_5V0_PA3_GPIO_Port GPIOG /* was GPIO_PIN_2 */
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#define EN_P_5V5_PA_Pin GPIO_PIN_3
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#define EN_P_5V5_PA_GPIO_Port GPIOG
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#define EN_P_1V8_CLOCK_Pin GPIO_PIN_4
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#define EN_P_1V8_CLOCK_GPIO_Port GPIOG
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#define EN_P_3V3_CLOCK_Pin GPIO_PIN_5
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#define EN_P_3V3_CLOCK_GPIO_Port GPIOG
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#define ADF4382_RX_LKDET_Pin GPIO_PIN_6
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#define ADF4382_RX_LKDET_GPIO_Port GPIOG
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#define ADF4382_RX_DELADJ_Pin GPIO_PIN_7
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#define ADF4382_RX_DELADJ_GPIO_Port GPIOG
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#define ADF4382_RX_DELSTR_Pin GPIO_PIN_8
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#define ADF4382_RX_DELSTR_GPIO_Port GPIOG
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#define ADF4382_RX_CE_Pin GPIO_PIN_9
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#define ADF4382_RX_CE_GPIO_Port GPIOG /* was GPIO_PIN_9 */
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#define ADF4382_RX_CS_Pin GPIO_PIN_10
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#define ADF4382_RX_CS_GPIO_Port GPIOG /* was GPIO_PIN_10 */
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#define ADF4382_TX_LKDET_Pin GPIO_PIN_11
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#define ADF4382_TX_LKDET_GPIO_Port GPIOG
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#define ADF4382_TX_DELSTR_Pin GPIO_PIN_12
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#define ADF4382_TX_DELSTR_GPIO_Port GPIOG
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#define ADF4382_TX_DELADJ_Pin GPIO_PIN_13
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#define ADF4382_TX_DELADJ_GPIO_Port GPIOG
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#define ADF4382_TX_CS_Pin GPIO_PIN_14
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#define ADF4382_TX_CS_GPIO_Port GPIOG
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#define ADF4382_TX_CE_Pin GPIO_PIN_15
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#define ADF4382_TX_CE_GPIO_Port GPIOG
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/* Power enables (GPIOE) */
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#define EN_P_1V0_FPGA_Pin GPIO_PIN_7
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#define EN_P_1V0_FPGA_GPIO_Port GPIOE
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#define EN_P_1V8_FPGA_Pin GPIO_PIN_8
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#define EN_P_1V8_FPGA_GPIO_Port GPIOE
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#define EN_P_3V3_FPGA_Pin GPIO_PIN_9
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#define EN_P_3V3_FPGA_GPIO_Port GPIOE
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#define EN_P_5V0_ADAR_Pin GPIO_PIN_10
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#define EN_P_5V0_ADAR_GPIO_Port GPIOE
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#define EN_P_3V3_ADAR12_Pin GPIO_PIN_11
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#define EN_P_3V3_ADAR12_GPIO_Port GPIOE
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#define EN_P_3V3_ADAR34_Pin GPIO_PIN_12
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#define EN_P_3V3_ADAR34_GPIO_Port GPIOE
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#define EN_P_3V3_ADTR_Pin GPIO_PIN_13
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#define EN_P_3V3_ADTR_GPIO_Port GPIOE
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#define EN_P_3V3_SW_Pin GPIO_PIN_14
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#define EN_P_3V3_SW_GPIO_Port GPIOE
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#define EN_P_3V3_VDD_SW_Pin GPIO_PIN_15
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#define EN_P_3V3_VDD_SW_GPIO_Port GPIOE
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/* GPIOD pins */
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#define STEPPER_CW_P_Pin GPIO_PIN_4
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#define STEPPER_CW_P_GPIO_Port GPIOD
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#define STEPPER_CLK_P_Pin GPIO_PIN_5
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#define STEPPER_CLK_P_GPIO_Port GPIOD
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#define EN_DIS_RFPA_VDD_Pin GPIO_PIN_6
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#define EN_DIS_RFPA_VDD_GPIO_Port GPIOD
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#define EN_DIS_COOLING_Pin GPIO_PIN_7
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#define EN_DIS_COOLING_GPIO_Port GPIOD
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/* DAC pins */
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#define DAC_1_VG_CLR_Pin GPIO_PIN_4
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#define DAC_1_VG_CLR_GPIO_Port GPIOB
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#define DAC_1_VG_LDAC_Pin GPIO_PIN_5
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#define DAC_1_VG_LDAC_GPIO_Port GPIOB
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#define DAC_2_VG_CLR_Pin GPIO_PIN_8
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#define DAC_2_VG_CLR_GPIO_Port GPIOB
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#define DAC_2_VG_LDAC_Pin GPIO_PIN_9
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#define DAC_2_VG_LDAC_GPIO_Port GPIOB
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/* IMU interrupt pins */
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#define MAG_DRDY_Pin GPIO_PIN_6
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#define MAG_DRDY_GPIO_Port GPIOC
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#define ACC_INT_Pin GPIO_PIN_7
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#define ACC_INT_GPIO_Port GPIOC
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#define GYR_INT_Pin GPIO_PIN_8
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#define GYR_INT_GPIO_Port GPIOC
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/* FPGA digital I/O (directly connected GPIOs) */
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#define FPGA_DIG5_SAT_Pin GPIO_PIN_13
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#define FPGA_DIG5_SAT_GPIO_Port GPIOD
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#define FPGA_DIG6_Pin GPIO_PIN_14
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#define FPGA_DIG6_GPIO_Port GPIOD
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#define FPGA_DIG7_Pin GPIO_PIN_15
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#define FPGA_DIG7_GPIO_Port GPIOD
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#ifdef __cplusplus
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}
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#endif
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#endif /* MAIN_H_SHIM */
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