Jason
0745cc4f48
Split ST_CFAR_THR into two pipeline stages (THR + MUL) to fix Build 23 timing violation (WNS = -0.309 ns). The combinational path from leading_sum through GO/SO cross-multiply into alpha*noise DSP was too long for 10 ns. New pipeline: ST_CFAR_THR: register noise_sum_comb (mode select + cross-multiply) ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP ST_CFAR_CMP: compare + update window (unchanged) 3 cycles per CUT instead of 2 (~85 us vs 70 us per frame, negligible). All detection results identical: 23/23 CFAR standalone, 22/22 full regression, 3/3 real-data co-sim (5137/5137 exact match) PASS.
554 lines
22 KiB
Verilog
554 lines
22 KiB
Verilog
`timescale 1ns / 1ps
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/**
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* cfar_ca.v
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*
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* Cell-Averaging CFAR (Constant False Alarm Rate) Detector
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* for the AERIS-10 phased-array radar.
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*
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* Replaces the simple magnitude threshold detector in radar_system_top.v
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* (lines 474-514) with a proper adaptive-threshold CFAR algorithm.
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*
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* Architecture:
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* Phase 1 (BUFFER): As Doppler processor outputs arrive, compute |I|+|Q|
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* magnitude and store in BRAM. Address = {range_bin, doppler_bin}.
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* When CFAR is disabled, applies simple threshold pass-through.
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*
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* Phase 2 (CFAR): After frame_complete pulse from Doppler processor,
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* process each Doppler column independently:
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* a) Read 64 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
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* b) Compute initial sliding window sums (ST_CFAR_INIT)
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* c) Slide CUT through all 64 range bins:
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* - 3 sub-cycles per CUT:
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* ST_CFAR_THR: register noise_sum (mode select + cross-multiply)
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* ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP
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* ST_CFAR_CMP: compare CUT magnitude against threshold + update window
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* d) Advance to next Doppler column (ST_COL_NEXT)
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*
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* CFAR Modes (cfg_cfar_mode):
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* 2'b00 = CA-CFAR: noise = leading_sum + lagging_sum
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* 2'b01 = GO-CFAR: noise = max(leading_sum * lag_cnt, lagging_sum * lead_cnt)
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* normalized — picks larger average
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* 2'b10 = SO-CFAR: noise = min(leading_sum * lag_cnt, lagging_sum * lead_cnt)
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* 2'b11 = Reserved (falls back to CA-CFAR)
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*
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* Threshold computation:
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* threshold = (alpha * noise_sum) >> ALPHA_FRAC_BITS
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* Host sets alpha in Q4.4 fixed-point, pre-compensated for training cell count.
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* Example: for T=8 cells per side (16 total), desired Pfa=1e-4:
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* alpha_statistical ≈ 4.88
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* alpha_fpga = alpha_statistical / 16 = 0.305 → Q4.4 ≈ 0x05
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* Or host can set alpha per training cell if it accounts for count.
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*
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* Edge handling:
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* At range boundaries where the full window doesn't fit, only available
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* training cells are used. The noise estimate naturally reduces, raising
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* false alarm rate at edges — acceptable for radar (edge bins are
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* typically clutter).
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*
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* Timing:
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* Phase 2 takes ~(66 + T + 3*64) * 32 ≈ 8500 cycles per frame @ 100 MHz
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* = 85 µs. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
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* (3 cycles per CUT due to pipeline: THR → MUL → CMP)
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*
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* Resources:
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* - 1 BRAM18K for magnitude buffer (2048 x 17 bits)
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* - 1 DSP48 for alpha multiply
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* - ~300 LUTs for FSM + sliding window + comparators
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*
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* Clock domain: clk (100 MHz, same as Doppler processor)
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*/
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module cfar_ca #(
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parameter NUM_RANGE_BINS = 64,
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parameter NUM_DOPPLER_BINS = 32,
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parameter MAG_WIDTH = 17,
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parameter ALPHA_WIDTH = 8,
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parameter MAX_GUARD = 8,
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parameter MAX_TRAIN = 16
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) (
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input wire clk,
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input wire reset_n,
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// ========== DOPPLER PROCESSOR INPUTS ==========
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input wire [31:0] doppler_data,
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input wire doppler_valid,
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input wire [4:0] doppler_bin_in,
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input wire [5:0] range_bin_in,
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input wire frame_complete,
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// ========== CONFIGURATION ==========
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input wire [3:0] cfg_guard_cells,
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input wire [4:0] cfg_train_cells,
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input wire [ALPHA_WIDTH-1:0] cfg_alpha,
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input wire [1:0] cfg_cfar_mode,
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input wire cfg_cfar_enable,
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input wire [15:0] cfg_simple_threshold,
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// ========== DETECTION OUTPUTS ==========
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output reg detect_flag,
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output reg detect_valid,
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output reg [5:0] detect_range,
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output reg [4:0] detect_doppler,
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output reg [MAG_WIDTH-1:0] detect_magnitude,
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output reg [MAG_WIDTH-1:0] detect_threshold,
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// ========== STATUS ==========
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output reg [15:0] detect_count,
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output wire cfar_busy,
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output reg [7:0] cfar_status
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);
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// ============================================================================
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// INTERNAL PARAMETERS
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// ============================================================================
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localparam TOTAL_CELLS = NUM_RANGE_BINS * NUM_DOPPLER_BINS;
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localparam ADDR_WIDTH = 11;
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localparam COL_BITS = 5;
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localparam ROW_BITS = 6;
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localparam SUM_WIDTH = MAG_WIDTH + 6; // 23 bits: sum of up to 64 magnitudes
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localparam PROD_WIDTH = SUM_WIDTH + ALPHA_WIDTH; // 31 bits
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localparam ALPHA_FRAC_BITS = 4; // Q4.4
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// ============================================================================
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// FSM STATES
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// ============================================================================
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localparam [3:0] ST_IDLE = 4'd0,
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ST_BUFFER = 4'd1,
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ST_COL_LOAD = 4'd2,
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ST_CFAR_INIT = 4'd3,
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ST_CFAR_THR = 4'd4, // Register noise_sum (mode select + cross-multiply)
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ST_CFAR_MUL = 4'd8, // Compute alpha * noise_sum_reg in DSP
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ST_CFAR_CMP = 4'd5, // Compare + update window
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ST_COL_NEXT = 4'd6,
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ST_DONE = 4'd7;
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reg [3:0] state;
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assign cfar_busy = (state != ST_IDLE);
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// ============================================================================
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// MAGNITUDE COMPUTATION (combinational)
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// ============================================================================
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wire signed [15:0] dop_i = doppler_data[15:0];
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wire signed [15:0] dop_q = doppler_data[31:16];
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wire [15:0] abs_i = dop_i[15] ? (~dop_i + 16'd1) : dop_i;
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wire [15:0] abs_q = dop_q[15] ? (~dop_q + 16'd1) : dop_q;
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wire [MAG_WIDTH-1:0] cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
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// ============================================================================
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// MAGNITUDE BRAM (2048 x 17 bits)
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// ============================================================================
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reg mag_we;
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reg [ADDR_WIDTH-1:0] mag_waddr;
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reg [MAG_WIDTH-1:0] mag_wdata;
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reg [ADDR_WIDTH-1:0] mag_raddr;
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reg [MAG_WIDTH-1:0] mag_rdata;
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(* ram_style = "block" *) reg [MAG_WIDTH-1:0] mag_mem [0:TOTAL_CELLS-1];
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always @(posedge clk) begin
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if (mag_we)
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mag_mem[mag_waddr] <= mag_wdata;
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mag_rdata <= mag_mem[mag_raddr];
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end
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// ============================================================================
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// COLUMN LINE BUFFER (64 x 17 bits — distributed RAM)
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// ============================================================================
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reg [MAG_WIDTH-1:0] col_buf [0:NUM_RANGE_BINS-1];
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reg [ROW_BITS:0] col_load_idx;
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// ============================================================================
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// SLIDING WINDOW STATE
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// ============================================================================
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reg [SUM_WIDTH-1:0] leading_sum;
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reg [SUM_WIDTH-1:0] lagging_sum;
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reg [ROW_BITS:0] leading_count;
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reg [ROW_BITS:0] lagging_count;
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reg [ROW_BITS:0] cut_idx;
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reg [COL_BITS-1:0] col_idx;
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// Registered config (captured at frame start)
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reg [3:0] r_guard;
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reg [4:0] r_train;
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reg [ALPHA_WIDTH-1:0] r_alpha;
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reg [1:0] r_mode;
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reg r_enable;
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reg [15:0] r_simple_thr;
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// Threshold pipeline registers
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reg [SUM_WIDTH-1:0] noise_sum_reg; // Stage 1: registered noise_sum_comb output
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reg [PROD_WIDTH-1:0] noise_product; // Stage 2: alpha * noise_sum_reg
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reg [MAG_WIDTH-1:0] adaptive_thr;
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// Init counter for computing initial lagging sum
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reg [ROW_BITS:0] init_idx;
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// ============================================================================
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// SLIDING WINDOW DELTA COMPUTATION (combinational)
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// ============================================================================
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// Compute net delta to leading_sum and lagging_sum when CUT advances by 1.
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// All deltas computed combinationally, applied as a single NBA per register.
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// Indices of cells entering/leaving the window when CUT moves from k to k+1:
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// Leading: new training cell at index k+1-G-1 = k-G (was closest guard cell)
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// cell falling off at index k+1-G-T-1 = k-G-T
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// Lagging: cell leaving at index k+G+1 (enters guard zone)
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// new cell entering at index k+1+G+T (at far end)
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wire signed [ROW_BITS+1:0] lead_add_idx = $signed({1'b0, cut_idx}) - $signed({1'b0, r_guard});
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wire signed [ROW_BITS+1:0] lead_rem_idx = $signed({1'b0, cut_idx}) - $signed({1'b0, r_guard}) - $signed({1'b0, r_train});
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wire signed [ROW_BITS+1:0] lag_rem_idx = $signed({1'b0, cut_idx}) + $signed({1'b0, r_guard}) + 1;
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wire signed [ROW_BITS+1:0] lag_add_idx = $signed({1'b0, cut_idx}) + 1 + $signed({1'b0, r_guard}) + $signed({1'b0, r_train});
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wire lead_add_valid = (lead_add_idx >= 0) && (lead_add_idx < NUM_RANGE_BINS);
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wire lead_rem_valid = (lead_rem_idx >= 0) && (lead_rem_idx < NUM_RANGE_BINS);
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wire lag_rem_valid = (lag_rem_idx >= 0) && (lag_rem_idx < NUM_RANGE_BINS);
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wire lag_add_valid = (lag_add_idx >= 0) && (lag_add_idx < NUM_RANGE_BINS);
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// Safe col_buf read with bounds checking (combinational)
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wire [MAG_WIDTH-1:0] lead_add_val = lead_add_valid ? col_buf[lead_add_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
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wire [MAG_WIDTH-1:0] lead_rem_val = lead_rem_valid ? col_buf[lead_rem_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
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wire [MAG_WIDTH-1:0] lag_rem_val = lag_rem_valid ? col_buf[lag_rem_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
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wire [MAG_WIDTH-1:0] lag_add_val = lag_add_valid ? col_buf[lag_add_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
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// Net deltas
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wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid ? $signed({1'b0, lead_add_val}) : 0)
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- (lead_rem_valid ? $signed({1'b0, lead_rem_val}) : 0);
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wire signed [1:0] lead_cnt_delta = (lead_add_valid ? 1 : 0) - (lead_rem_valid ? 1 : 0);
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wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid ? $signed({1'b0, lag_add_val}) : 0)
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- (lag_rem_valid ? $signed({1'b0, lag_rem_val}) : 0);
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wire signed [1:0] lag_cnt_delta = (lag_add_valid ? 1 : 0) - (lag_rem_valid ? 1 : 0);
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// ============================================================================
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// NOISE ESTIMATE COMPUTATION (combinational for CFAR mode selection)
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// ============================================================================
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reg [SUM_WIDTH-1:0] noise_sum_comb;
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always @(*) begin
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case (r_mode)
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2'b00, 2'b11: begin // CA-CFAR
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noise_sum_comb = leading_sum + lagging_sum;
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end
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2'b01: begin // GO-CFAR: pick sum from side with greater average
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if (leading_count > 0 && lagging_count > 0) begin
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// leading_avg > lagging_avg ↔ leading_sum * lagging_count > lagging_sum * leading_count
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if (leading_sum * lagging_count > lagging_sum * leading_count)
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noise_sum_comb = leading_sum;
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else
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noise_sum_comb = lagging_sum;
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end else if (leading_count > 0)
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noise_sum_comb = leading_sum;
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else
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noise_sum_comb = lagging_sum;
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end
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2'b10: begin // SO-CFAR: pick sum from side with smaller average
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if (leading_count > 0 && lagging_count > 0) begin
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if (leading_sum * lagging_count < lagging_sum * leading_count)
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noise_sum_comb = leading_sum;
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else
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noise_sum_comb = lagging_sum;
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end else if (leading_count > 0)
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noise_sum_comb = leading_sum;
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else
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noise_sum_comb = lagging_sum;
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end
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default:
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noise_sum_comb = leading_sum + lagging_sum;
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endcase
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end
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// ============================================================================
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// MAIN FSM
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// ============================================================================
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always @(posedge clk or negedge reset_n) begin
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if (!reset_n) begin
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state <= ST_IDLE;
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detect_flag <= 1'b0;
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detect_valid <= 1'b0;
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detect_range <= 6'd0;
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detect_doppler <= 5'd0;
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detect_magnitude <= {MAG_WIDTH{1'b0}};
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detect_threshold <= {MAG_WIDTH{1'b0}};
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detect_count <= 16'd0;
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cfar_status <= 8'd0;
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mag_we <= 1'b0;
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mag_waddr <= {ADDR_WIDTH{1'b0}};
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mag_wdata <= {MAG_WIDTH{1'b0}};
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mag_raddr <= {ADDR_WIDTH{1'b0}};
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col_load_idx <= 0;
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col_idx <= 0;
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cut_idx <= 0;
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leading_sum <= 0;
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lagging_sum <= 0;
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leading_count <= 0;
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lagging_count <= 0;
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init_idx <= 0;
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noise_sum_reg <= 0;
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noise_product <= 0;
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adaptive_thr <= 0;
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r_guard <= 4'd2;
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r_train <= 5'd8;
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r_alpha <= 8'h30;
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r_mode <= 2'b00;
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r_enable <= 1'b0;
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r_simple_thr <= 16'd10000;
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end else begin
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// Defaults: clear one-shot outputs
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detect_valid <= 1'b0;
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detect_flag <= 1'b0;
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mag_we <= 1'b0;
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case (state)
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// ================================================================
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// ST_IDLE: Wait for first Doppler output
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// ================================================================
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ST_IDLE: begin
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cfar_status <= 8'd0;
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if (doppler_valid) begin
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// Capture configuration at frame start
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r_guard <= cfg_guard_cells;
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r_train <= (cfg_train_cells == 0) ? 5'd1 : cfg_train_cells;
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r_alpha <= cfg_alpha;
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r_mode <= cfg_cfar_mode;
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r_enable <= cfg_cfar_enable;
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r_simple_thr <= cfg_simple_threshold;
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// Buffer first sample
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mag_we <= 1'b1;
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mag_waddr <= {range_bin_in, doppler_bin_in};
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mag_wdata <= cur_mag;
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// Simple threshold pass-through when CFAR disabled
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if (!cfg_cfar_enable) begin
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detect_flag <= (cur_mag > {1'b0, cfg_simple_threshold});
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detect_valid <= 1'b1;
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detect_range <= range_bin_in;
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detect_doppler <= doppler_bin_in;
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detect_magnitude <= cur_mag;
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detect_threshold <= {1'b0, cfg_simple_threshold};
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if (cur_mag > {1'b0, cfg_simple_threshold})
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detect_count <= detect_count + 1;
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end
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state <= ST_BUFFER;
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end
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end
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// ================================================================
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// ST_BUFFER: Store magnitudes until frame complete
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// ================================================================
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ST_BUFFER: begin
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cfar_status <= {4'd1, 4'd0};
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if (doppler_valid) begin
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mag_we <= 1'b1;
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mag_waddr <= {range_bin_in, doppler_bin_in};
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mag_wdata <= cur_mag;
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if (!r_enable) begin
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detect_flag <= (cur_mag > {1'b0, r_simple_thr});
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detect_valid <= 1'b1;
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detect_range <= range_bin_in;
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detect_doppler <= doppler_bin_in;
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detect_magnitude <= cur_mag;
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detect_threshold <= {1'b0, r_simple_thr};
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if (cur_mag > {1'b0, r_simple_thr})
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detect_count <= detect_count + 1;
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end
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end
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if (frame_complete) begin
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if (r_enable) begin
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col_idx <= 0;
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col_load_idx <= 0;
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mag_raddr <= {6'd0, 5'd0};
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state <= ST_COL_LOAD;
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end else begin
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state <= ST_DONE;
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end
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end
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end
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// ================================================================
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// ST_COL_LOAD: Read one Doppler column from BRAM
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// ================================================================
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// BRAM has 1-cycle read latency. Pipeline: present addr cycle N,
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// capture data cycle N+1.
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ST_COL_LOAD: begin
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cfar_status <= {4'd2, 1'b0, col_idx[2:0]};
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if (col_load_idx == 0) begin
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// First address already presented, advance to range=1
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mag_raddr <= {6'd1, col_idx};
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col_load_idx <= 1;
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end else if (col_load_idx <= NUM_RANGE_BINS) begin
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// Capture previous read
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col_buf[col_load_idx - 1] <= mag_rdata;
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if (col_load_idx < NUM_RANGE_BINS) begin
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mag_raddr <= {col_load_idx[ROW_BITS-1:0] + 6'd1, col_idx};
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end
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col_load_idx <= col_load_idx + 1;
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end
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if (col_load_idx == NUM_RANGE_BINS + 1) begin
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// Column fully loaded → initialize CFAR window
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state <= ST_CFAR_INIT;
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init_idx <= 0;
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leading_sum <= 0;
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lagging_sum <= 0;
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leading_count <= 0;
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lagging_count <= 0;
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cut_idx <= 0;
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end
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end
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// ================================================================
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// ST_CFAR_INIT: Compute initial window sums for CUT=0
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// ================================================================
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// CUT=0 has no leading cells. Lagging cells are at
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// indices [guard+1 .. guard+train] (if they exist).
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// Iterate one training cell per cycle.
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ST_CFAR_INIT: begin
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cfar_status <= {4'd3, 1'b0, col_idx[2:0]};
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if (init_idx < r_train) begin
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if ((r_guard + 1 + init_idx) < NUM_RANGE_BINS) begin
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lagging_sum <= lagging_sum + col_buf[r_guard + 1 + init_idx];
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lagging_count <= lagging_count + 1;
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end
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init_idx <= init_idx + 1;
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end else begin
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|
// Initial sums ready → begin CFAR sliding
|
|
state <= ST_CFAR_THR;
|
|
end
|
|
end
|
|
|
|
// ================================================================
|
|
// ST_CFAR_THR: Register noise estimate (mode select + cross-multiply)
|
|
// ================================================================
|
|
// Pipeline stage 1: register the combinational noise_sum_comb
|
|
// output. This breaks the critical path:
|
|
// leading_sum → cross-multiply (GO/SO) → mux → alpha*noise DSP
|
|
// into two shorter paths:
|
|
// Cycle 1: leading_sum → cross-multiply → mux → noise_sum_reg
|
|
// Cycle 2: noise_sum_reg → alpha * noise_sum_reg → noise_product
|
|
ST_CFAR_THR: begin
|
|
cfar_status <= {4'd4, 1'b0, col_idx[2:0]};
|
|
|
|
noise_sum_reg <= noise_sum_comb;
|
|
state <= ST_CFAR_MUL;
|
|
end
|
|
|
|
// ================================================================
|
|
// ST_CFAR_MUL: Compute alpha * noise_sum_reg in DSP
|
|
// ================================================================
|
|
// Pipeline stage 2: multiply registered noise sum by alpha.
|
|
// This is a clean registered-input → DSP path.
|
|
ST_CFAR_MUL: begin
|
|
cfar_status <= {4'd4, 1'b1, col_idx[2:0]};
|
|
|
|
noise_product <= r_alpha * noise_sum_reg;
|
|
state <= ST_CFAR_CMP;
|
|
end
|
|
|
|
// ================================================================
|
|
// ST_CFAR_CMP: Compare CUT against threshold + update window
|
|
// ================================================================
|
|
ST_CFAR_CMP: begin
|
|
cfar_status <= {4'd5, 1'b0, col_idx[2:0]};
|
|
|
|
// Threshold = noise_product >> ALPHA_FRAC_BITS
|
|
// Saturate to MAG_WIDTH bits
|
|
if (noise_product[PROD_WIDTH-1:ALPHA_FRAC_BITS+MAG_WIDTH] != 0)
|
|
adaptive_thr <= {MAG_WIDTH{1'b1}}; // Saturate
|
|
else
|
|
adaptive_thr <= noise_product[ALPHA_FRAC_BITS +: MAG_WIDTH];
|
|
|
|
// Output detection result
|
|
detect_magnitude <= col_buf[cut_idx[ROW_BITS-1:0]];
|
|
detect_range <= cut_idx[ROW_BITS-1:0];
|
|
detect_doppler <= col_idx;
|
|
detect_valid <= 1'b1;
|
|
|
|
// Compare: threshold computed this cycle from noise_product
|
|
begin : threshold_compare
|
|
reg [MAG_WIDTH-1:0] thr_val;
|
|
if (noise_product[PROD_WIDTH-1:ALPHA_FRAC_BITS+MAG_WIDTH] != 0)
|
|
thr_val = {MAG_WIDTH{1'b1}};
|
|
else
|
|
thr_val = noise_product[ALPHA_FRAC_BITS +: MAG_WIDTH];
|
|
|
|
detect_threshold <= thr_val;
|
|
|
|
if (col_buf[cut_idx[ROW_BITS-1:0]] > thr_val) begin
|
|
detect_flag <= 1'b1;
|
|
detect_count <= detect_count + 1;
|
|
end
|
|
end
|
|
|
|
// Update sliding window for next CUT
|
|
if (cut_idx < NUM_RANGE_BINS - 1) begin
|
|
// Apply pre-computed deltas (single NBA per register)
|
|
leading_sum <= $unsigned($signed({1'b0, leading_sum}) + lead_delta);
|
|
leading_count <= $unsigned($signed({1'b0, leading_count}) + {{(ROW_BITS){lead_cnt_delta[1]}}, lead_cnt_delta});
|
|
lagging_sum <= $unsigned($signed({1'b0, lagging_sum}) + lag_delta);
|
|
lagging_count <= $unsigned($signed({1'b0, lagging_count}) + {{(ROW_BITS){lag_cnt_delta[1]}}, lag_cnt_delta});
|
|
|
|
cut_idx <= cut_idx + 1;
|
|
state <= ST_CFAR_THR;
|
|
end else begin
|
|
state <= ST_COL_NEXT;
|
|
end
|
|
end
|
|
|
|
// ================================================================
|
|
// ST_COL_NEXT: Advance to next Doppler column or finish
|
|
// ================================================================
|
|
ST_COL_NEXT: begin
|
|
if (col_idx < NUM_DOPPLER_BINS - 1) begin
|
|
col_idx <= col_idx + 1;
|
|
col_load_idx <= 0;
|
|
mag_raddr <= {6'd0, col_idx + 5'd1};
|
|
state <= ST_COL_LOAD;
|
|
end else begin
|
|
state <= ST_DONE;
|
|
end
|
|
end
|
|
|
|
// ================================================================
|
|
// ST_DONE: Frame complete, return to idle
|
|
// ================================================================
|
|
ST_DONE: begin
|
|
cfar_status <= 8'd0;
|
|
state <= ST_IDLE;
|
|
|
|
`ifdef SIMULATION
|
|
$display("[CFAR] Frame complete: %0d total detections", detect_count);
|
|
`endif
|
|
end
|
|
|
|
default: state <= ST_IDLE;
|
|
endcase
|
|
end
|
|
end
|
|
|
|
// ============================================================================
|
|
// BRAM + LINE BUFFER INITIALIZATION (simulation only)
|
|
// ============================================================================
|
|
`ifdef SIMULATION
|
|
integer init_i;
|
|
initial begin
|
|
for (init_i = 0; init_i < TOTAL_CELLS; init_i = init_i + 1)
|
|
mag_mem[init_i] = 0;
|
|
for (init_i = 0; init_i < NUM_RANGE_BINS; init_i = init_i + 1)
|
|
col_buf[init_i] = 0;
|
|
end
|
|
`endif
|
|
|
|
endmodule
|