Jason 2401f5f89e fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19) ...

CFAR pipeline fix (clk_100m WNS: -0.331ns → +0.156ns):
- Pre-register col_buf reads during ST_CFAR_THR pipeline stage
- 8 pipeline registers (4 values + 4 valids) break 15-level mux tree
- Delta wires use registered values, eliminating combinatorial depth

CIC reset path fix (clk_mmcm_out0 WNS: -0.074ns → +0.068ns):
- Add reset_h input port to cic_decimator_4x_enhanced.v
- Remove internal wire reset_h = ~reset_n (LUT1 inverter was root cause)
- Wire pre-registered reset_400m from ddc_400m.v into both CIC instances
- 3 sync reset blocks changed from if(!reset_n) to if(reset_h)

Build 19 results (xc7a50tftg256-2, Vivado 2025.2):
- All 5 clock domains timing met, 0 failing endpoints
- WNS: +0.068ns (400MHz), +0.156ns (100MHz), +0.627ns (120MHz)
- Utilization: 66.67% LUT, 22.36% FF, 74% BRAM, 93.33% DSP
- Bitstream: 2,140 KB

2026-04-16 23:09:31 +05:45

..

cosim

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

ad9484_interface_400m_stub.v

Fix multi-seg/chain handshake deadlock + add radar_receiver_final integration test (10/10 PASS)

2026-03-16 18:51:08 +02:00

cic_dc_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

cic_impulse_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

cic_sine_passband.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

ddc_120mhz_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

fir_dc_output.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

fir_impulse_output.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

fir_sine_passband.csv

Add Phase 0.5 DDC co-simulation suite: bit-accurate Python model, scene generator, and 5/5 scenario validation

2026-03-16 16:01:40 +02:00

gen_mf_golden_ref.py

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_out_i_case1.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_out_i_case2.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_out_i_case3.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_out_i_case4.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_out_q_case1.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_out_q_case2.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_out_q_case3.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_out_q_case4.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_ref_i_case1.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_ref_i_case2.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_ref_i_case3.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_ref_i_case4.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_ref_q_case1.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_ref_q_case2.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_ref_q_case3.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_ref_q_case4.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_sig_i_case1.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_sig_i_case2.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_sig_i_case3.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_sig_i_case4.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_sig_q_case1.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_sig_q_case2.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_sig_q_case3.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_sig_q_case4.hex

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_golden_summary.txt

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

mf_pipeline_output.csv

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

nco_1mhz_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

nco_120mhz_output.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

nco_freq_switch.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

nco_quadrature.csv

Achieve timing closure: DSP48E1 pipelines, 4-stage NCO, 28-bit CIC, ASYNC_REG

2026-03-16 01:02:07 +02:00

radar_system_tb.v

feat(usb): add FT2232H USB 2.0 interface for 50T production board

2026-04-07 19:22:16 +03:00

tb_ad9484_xsim.v

Add new testbenches and fix USB clock forwarding test

2026-03-16 22:24:34 +02:00

tb_cdc_modules.v

Fix CDC reset domain bug (P0), strengthen testbenches with 31 structural assertions

2026-03-17 19:38:09 +02:00

tb_cfar_ca.v

Integrate CA-CFAR detector: replace fixed-threshold comparator with adaptive sliding-window CFAR engine (22/22 regression PASS)

2026-03-20 04:57:34 +02:00

tb_chirp_contract.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_chirp_controller.v

E2E integration test + RTL fixes: mixer sequencing, USB data-pending flags, receiver toggle wiring (19/19 FPGA)

2026-03-20 01:45:00 +02:00

tb_cic_decimator.v

fix: close all FPGA timing — CFAR pipeline + CIC reset path (Build 19)

2026-04-16 23:09:31 +05:45

tb_ddc_400m.v

Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)

2026-03-20 04:38:35 +02:00

tb_ddc_cosim.v

Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)

2026-03-20 04:38:35 +02:00

tb_ddc_input_interface.v

Fix ddc_input_interface 18->16 bit overflow: add saturation at positive full scale

2026-03-16 18:14:06 +02:00

tb_doppler_cosim.v

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

tb_doppler_realdata.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

tb_edge_detector.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_fft_engine.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

tb_fir_lowpass.v

FIR DSP48 pipelining (BREG+MREG) + matched filter BRAM migration with overlap cache

2026-03-19 20:39:01 +02:00

tb_fpga_self_test.v

Add radar dashboard GUI with replay mode for real ADI CN0566 data visualization, FPGA self-test module, and co-sim npy arrays

2026-03-20 19:02:06 +02:00

tb_freq_matched_filter.v

Add 8 Verilog testbenches with full coverage (144/144 pass)

2026-03-15 06:14:11 +02:00

tb_fullchain_mti_cfar_realdata.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

tb_fullchain_realdata.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

tb_latency_buffer.v

Phase 1 hardware bring-up prep: ILA debug probes, CDC waivers, programming scripts

2026-03-18 01:28:42 +02:00

tb_matched_filter_processing_chain.v

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

tb_mf_chain_synth.v

fix: align all range/carrier/velocity values to PLFM hardware + FPGA bug fixes

2026-04-15 15:44:04 +05:45

tb_mf_cosim.v

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

tb_mti_canceller.v

Integrate MTI canceller and DC notch filter for ground clutter removal

2026-03-20 16:39:17 +02:00

tb_multiseg_cosim.v

fix: align all range/carrier/velocity values to PLFM hardware + FPGA bug fixes

2026-04-15 15:44:04 +05:45

tb_nco_400m.v

Achieve full timing closure on xc7a100tcsg324-1 at 400 MHz (0 violations)

2026-03-16 15:02:35 +02:00

tb_nco_xsim.v

Fix NCO XSim test 12: widen zero-crossing range for DSP48E1 quantization

2026-03-16 23:23:06 +02:00

tb_radar_mode_controller.v

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

tb_radar_receiver_final.v

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

tb_range_bin_decimator.v

feat: 2048-pt FFT upgrade with decimation=4, 512 output bins, 6m spacing

2026-04-16 17:27:55 +05:45

tb_range_fft_realdata.v

Real-data co-simulation: range FFT, Doppler, full-chain all 2048/2048 exact match

2026-03-20 03:19:22 +02:00

tb_rx_gain_control.v

fix: 9 bugs from code review — RTL sign-ext & snapshot, thread safety, protocol fixes

2026-04-13 23:35:10 +05:45

tb_system_e2e.v

fix(test,docs): remove dead xfft_32 files, update test infra for dual-16 FFT, add regression guide

2026-04-07 02:51:48 +03:00

tb_threshold_detector.v

Production fixes 1-7: detection bugs, cfar→threshold rename, digital gain control, Doppler mismatch protection, decimator watchdog, bypass_mode dead code removal, range-mode register (21/21 regression PASS)

2026-03-20 04:38:35 +02:00

tb_usb_data_interface.v

feat: hybrid AGC (FPGA phases 1-3 + GUI phase 6) with timing fix

2026-04-13 19:24:11 +05:45