Jason
86b493a780
- Phase A: Remove self-blessing golden test from FPGA regression, wire MF co-sim (4 scenarios) into run_regression.sh, add opcode count guards to cross-layer tests (+3 tests) - Phase B: Add radar_params.vh parser and architectural param consistency tests (+7 tests), add banned stale-value pattern scanner (+1 test) - Separate WaveformConfig.range_resolution_m (physical, bandwidth-dependent) from bin_spacing_m (sample-rate dependent); rename all callers - Remove 151 lines of dead golden generate/compare code from tb_radar_receiver_final.v; testbench now runs structural + bounds only - Untrack generated MF co-sim CSV files, gitignore tb/golden/ directory CI: 256 tests total (168 python + 40 cross-layer + 27 FPGA + 21 MCU), all green
66 lines
1.9 KiB
Plaintext
66 lines
1.9 KiB
Plaintext
# Verilog simulation artifacts
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*.vvp
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*.vcd
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# Debug / scratch RTL (not part of the design)
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9_Firmware/9_2_FPGA/debug_*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
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9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
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9_Firmware/9_2_FPGA/tb/tb_bram_debug.v
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# Local simulation artifacts and CSV outputs
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9_Firmware/9_2_FPGA/cic_*.csv
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9_Firmware/9_2_FPGA/fir_*.csv
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9_Firmware/9_2_FPGA/nco_*.csv
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9_Firmware/9_2_FPGA/ddc_*.csv
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9_Firmware/9_2_FPGA/mf_pipeline_output.csv
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9_Firmware/9_2_FPGA/mf_chain_autocorr.csv
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9_Firmware/9_2_FPGA/rbd_mode00_ramp.csv
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9_Firmware/9_2_FPGA/rbd_mode01_peak.csv
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9_Firmware/9_2_FPGA/rbd_mode10_avg.csv
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9_Firmware/9_2_FPGA/rbd_mode10_ramp.csv
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9_Firmware/9_2_FPGA/rmc_autoscan.csv
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9_Firmware/9_2_FPGA/tb/mf_chain_autocorr.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode00_ramp.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode01_peak.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode10_avg.csv
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9_Firmware/9_2_FPGA/tb/rbd_mode10_ramp.csv
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9_Firmware/9_2_FPGA/tb/rmc_autoscan.csv
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9_Firmware/9_2_FPGA/tb_usb_data_interface.csv
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# Co-sim intermediate CSVs (regenerated by scripts)
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9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv
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9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_*.csv
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9_Firmware/9_2_FPGA/tb/cosim/compare_mf_*.csv
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# Golden reference outputs (regenerated by testbenches)
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9_Firmware/9_2_FPGA/tb/golden/
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# macOS
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.DS_Store
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# Python
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__pycache__/
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*.pyc
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# Local organization/archival folders (not part of repo source)
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10_docs/
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# Local simulation workspaces and generated outputs
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5_Simulations/generated/
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5_Simulations/aeris10_antenna_sim.py
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5_Simulations/aeris10_radar_sim.py
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# Local FPGA report dumps and scratch constraints
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9_Firmware/9_2_FPGA/reports/
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9_Firmware/9_2_FPGA/synth_only.xdc
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# Local timing closure report snapshots
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build*_reports/
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# UART capture logs (generated by tools/uart_capture.py)
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logs/
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