Jason
063fa081fe
FPGA timing (400MHz domain WNS: +0.339ns, was +0.002ns): - DONT_TOUCH on BUFG to prevent AggressiveExplore cascade replication - NCO→mixer pipeline registers break critical 1.5ns route - Clock uncertainty reduced 200ps→100ps (adequate guardband) - Updated golden/cosim references for +1 cycle pipeline latency STM32 bug fixes: - Guard uint32_t underflow in processStartFlag (length<4) - Replace unbounded strcat in getSystemStatusForGUI with snprintf - Early-return error masking in checkSystemHealth - Add HAL_Delay in emergency blink loop GUI bug fixes: - Remove 0x03 from _HARDWARE_ONLY_OPCODES (was in both sets) - Wire real error count in V7 diagnostics panel - Fix _stop_demo showing 'Live' label during replay mode FPGA comment fixes + CI: add test_v7.py to pytest command Vivado build 50t passed: 0 failing endpoints, WHS=+0.056ns
230 lines
8.0 KiB
Verilog
230 lines
8.0 KiB
Verilog
`timescale 1ns / 1ps
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// ============================================================================
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// adc_clk_mmcm.v — MMCME2 Jitter-Cleaning Wrapper for AD9484 400 MHz DCO
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//
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// PURPOSE:
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// Replaces the direct BUFG on the ADC data clock output (adc_dco) with an
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// MMCME2_ADV configured for 1:1 frequency (400 MHz in → 400 MHz out) with
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// jitter attenuation via the PLL feedback loop.
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//
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// CURRENT ARCHITECTURE (ad9484_interface_400m.v):
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// adc_dco_p/n → IBUFDS → BUFIO (drives IDDR only, near-zero delay)
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// → BUFG (drives all fabric 400 MHz logic)
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//
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// NEW ARCHITECTURE (this module replaces the BUFG path):
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// adc_dco_p/n → IBUFDS → BUFIO (unchanged — drives IDDR only)
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// → MMCME2 CLKIN1 → CLKOUT0 → BUFG (fabric 400 MHz)
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//
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// BENEFITS:
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// 1. Jitter attenuation: MMCM PLL loop filters input jitter from ~50 ps
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// to ~20-30 ps output jitter, reducing clock uncertainty by ~20 ps.
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// 2. Phase control: CLKOUT0_PHASE can fine-tune phase offset if needed.
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// 3. Locked indicator: mmcm_locked output enables proper reset sequencing.
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// 4. Expected WNS improvement: +20-40 ps on the 400 MHz CIC critical path.
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//
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// MMCM CONFIGURATION (Artix-7 XC7A200T-2):
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// CLKIN1 = 400 MHz (from IBUFDS output)
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// DIVCLK_DIVIDE = 1
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// CLKFBOUT_MULT_F = 2.0 → VCO = 400 * 2 = 800 MHz (range: 600-1200 MHz)
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// CLKOUT0_DIVIDE_F = 2.0 → CLKOUT0 = 800 / 2 = 400 MHz
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// CLKFBOUT → BUFG → CLKFBIN (internal feedback for best jitter performance)
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//
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// INTEGRATION:
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// This module is a DROP-IN replacement for the BUFG in ad9484_interface_400m.v.
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// See adc_clk_mmcm_integration.md for step-by-step instructions.
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//
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// SIMULATION:
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// Under `ifdef SIMULATION, this module passes the clock through a simple
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// BUFG (no MMCM primitive), matching the current behavior for iverilog.
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//
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// TARGET: XC7A200T-2FBG484I (Artix-7, speed grade -2, industrial temp)
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// ============================================================================
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module adc_clk_mmcm (
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// Input: single-ended clock from IBUFDS output
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input wire clk_in, // 400 MHz from IBUFDS (adc_dco after IBUFDS)
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// System reset (active-low, from 100 MHz domain)
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input wire reset_n,
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// Outputs
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output wire clk_400m_out, // Jitter-cleaned 400 MHz on BUFG (fabric logic)
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output wire mmcm_locked // 1 = MMCM PLL is locked and clock is stable
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);
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`ifdef SIMULATION
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// ============================================================================
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// SIMULATION PATH — simple passthrough (no Xilinx primitives)
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// ============================================================================
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// iverilog and other simulators don't have MMCME2_ADV. Pass clock through
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// with a locked signal that asserts after a brief delay matching real MMCM
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// lock time (~10 us at 400 MHz = ~4000 cycles).
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reg locked_sim;
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reg [12:0] lock_counter;
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initial begin
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locked_sim = 1'b0;
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lock_counter = 13'd0;
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end
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always @(posedge clk_in or negedge reset_n) begin
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if (!reset_n) begin
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locked_sim <= 1'b0;
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lock_counter <= 13'd0;
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end else begin
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if (lock_counter < 13'd4096) begin
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lock_counter <= lock_counter + 1;
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end else begin
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locked_sim <= 1'b1;
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end
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end
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end
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`ifdef SIMULATION_HAS_BUFG
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// If the simulator supports BUFG (e.g., Vivado xsim)
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BUFG bufg_sim (
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.I(clk_in),
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.O(clk_400m_out)
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);
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`else
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// Pure behavioral — iverilog
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assign clk_400m_out = clk_in;
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`endif
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assign mmcm_locked = locked_sim;
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`else
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// ============================================================================
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// SYNTHESIS PATH — MMCME2_ADV with jitter-cleaning feedback loop
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// ============================================================================
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wire clk_mmcm_out0; // MMCM CLKOUT0 (unbuffered)
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wire clk_mmcm_fb_out; // MMCM CLKFBOUT (unbuffered)
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wire clk_mmcm_fb_bufg; // CLKFBOUT after BUFG (feedback)
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wire mmcm_locked_int;
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// ---- MMCME2_ADV Instance ----
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// Configuration for 400 MHz 1:1 with jitter cleaning:
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// VCO = CLKIN1 * CLKFBOUT_MULT_F / DIVCLK_DIVIDE = 400 * 2.0 / 1 = 800 MHz
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// CLKOUT0 = VCO / CLKOUT0_DIVIDE_F = 800 / 2.0 = 400 MHz
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// Bandwidth = "HIGH" for maximum jitter attenuation
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MMCME2_ADV #(
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// Input clock
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.CLKIN1_PERIOD (2.500), // 400 MHz = 2.500 ns period
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.CLKIN2_PERIOD (0.000), // Unused
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.REF_JITTER1 (0.020), // 20 ps reference jitter (conservative)
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.REF_JITTER2 (0.000), // Unused
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// VCO configuration
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.DIVCLK_DIVIDE (1), // Input divider = 1 (no division)
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.CLKFBOUT_MULT_F (2.0), // Feedback multiplier → VCO = 800 MHz
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.CLKFBOUT_PHASE (0.0), // No feedback phase shift
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// Output 0: 400 MHz fabric clock
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.CLKOUT0_DIVIDE_F (2.0), // 800 / 2.0 = 400 MHz
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.CLKOUT0_PHASE (0.0), // Phase-aligned with input
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.CLKOUT0_DUTY_CYCLE (0.5), // 50% duty cycle
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// Unused outputs — disabled
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.CLKOUT1_DIVIDE (1),
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.CLKOUT1_PHASE (0.0),
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.CLKOUT1_DUTY_CYCLE (0.5),
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.CLKOUT2_DIVIDE (1),
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.CLKOUT2_PHASE (0.0),
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.CLKOUT2_DUTY_CYCLE (0.5),
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.CLKOUT3_DIVIDE (1),
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.CLKOUT3_PHASE (0.0),
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.CLKOUT3_DUTY_CYCLE (0.5),
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.CLKOUT4_DIVIDE (1),
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.CLKOUT4_PHASE (0.0),
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.CLKOUT4_DUTY_CYCLE (0.5),
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.CLKOUT5_DIVIDE (1),
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.CLKOUT5_PHASE (0.0),
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.CLKOUT5_DUTY_CYCLE (0.5),
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.CLKOUT6_DIVIDE (1),
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.CLKOUT6_PHASE (0.0),
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.CLKOUT6_DUTY_CYCLE (0.5),
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// PLL filter bandwidth — HIGH for maximum jitter attenuation
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.BANDWIDTH ("HIGH"),
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// Compensation mode — BUFG on feedback path
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.COMPENSATION ("BUF_IN"),
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// Startup wait for configuration clock
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.STARTUP_WAIT ("FALSE")
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) mmcm_adc_400m (
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// Clock inputs
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.CLKIN1 (clk_in), // 400 MHz from IBUFDS
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.CLKIN2 (1'b0), // Unused second input
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.CLKINSEL (1'b1), // Select CLKIN1
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// Feedback
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.CLKFBOUT (clk_mmcm_fb_out), // Feedback output (unbuffered)
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.CLKFBIN (clk_mmcm_fb_bufg), // Feedback input (from BUFG)
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// Clock outputs
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.CLKOUT0 (clk_mmcm_out0), // 400 MHz output (unbuffered)
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.CLKOUT0B (), // Unused inverted
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.CLKOUT1 (),
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.CLKOUT1B (),
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.CLKOUT2 (),
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.CLKOUT2B (),
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.CLKOUT3 (),
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.CLKOUT3B (),
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.CLKOUT4 (),
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.CLKOUT5 (),
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.CLKOUT6 (),
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.CLKFBOUTB (), // Unused inverted feedback
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// Control
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.RST (~reset_n), // Active-high reset
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.PWRDWN (1'b0), // Never power down
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// Status
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.LOCKED (mmcm_locked_int),
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// Dynamic reconfiguration (unused — tie off)
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.DADDR (7'd0),
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.DCLK (1'b0),
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.DEN (1'b0),
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.DI (16'd0),
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.DWE (1'b0),
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.DO (),
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.DRDY (),
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// Phase shift (unused — tie off)
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.PSCLK (1'b0),
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.PSEN (1'b0),
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.PSINCDEC (1'b0),
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.PSDONE ()
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);
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// ---- Feedback BUFG ----
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// Routes CLKFBOUT through a BUFG back to CLKFBIN.
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// This is the standard "internal feedback" topology for best jitter performance.
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// Vivado's clock network insertion delay is compensated by the MMCM feedback loop.
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BUFG bufg_feedback (
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.I(clk_mmcm_fb_out),
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.O(clk_mmcm_fb_bufg)
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);
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// ---- Output BUFG ----
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// Routes the jitter-cleaned 400 MHz CLKOUT0 onto a global clock network.
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// DONT_TOUCH prevents phys_opt_design AggressiveExplore from replicating this
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// BUFG into a cascaded chain (4 BUFGs in series observed in Build 26), which
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// added ~243ps of clock insertion delay and caused -187ps clock skew on the
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// NCO→DSP mixer critical path.
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(* DONT_TOUCH = "TRUE" *)
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BUFG bufg_clk400m (
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.I(clk_mmcm_out0),
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.O(clk_400m_out)
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);
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assign mmcm_locked = mmcm_locked_int;
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`endif
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endmodule
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