# Verilog simulation artifacts
*.vvp
*.vcd

# Debug / scratch RTL (not part of the design)
9_Firmware/9_2_FPGA/debug_*.v
9_Firmware/9_2_FPGA/tb/tb_fft_debug*.v
9_Firmware/9_2_FPGA/tb/tb_fft_mini*.v
9_Firmware/9_2_FPGA/tb/tb_bram_debug.v

# Local simulation artifacts and CSV outputs
9_Firmware/9_2_FPGA/cic_*.csv
9_Firmware/9_2_FPGA/fir_*.csv
9_Firmware/9_2_FPGA/nco_*.csv
9_Firmware/9_2_FPGA/ddc_*.csv
9_Firmware/9_2_FPGA/mf_pipeline_output.csv
9_Firmware/9_2_FPGA/mf_chain_autocorr.csv
9_Firmware/9_2_FPGA/rbd_mode00_ramp.csv
9_Firmware/9_2_FPGA/rbd_mode01_peak.csv
9_Firmware/9_2_FPGA/rbd_mode10_avg.csv
9_Firmware/9_2_FPGA/rbd_mode10_ramp.csv
9_Firmware/9_2_FPGA/rmc_autoscan.csv
9_Firmware/9_2_FPGA/tb/mf_chain_autocorr.csv
9_Firmware/9_2_FPGA/tb/rbd_mode00_ramp.csv
9_Firmware/9_2_FPGA/tb/rbd_mode01_peak.csv
9_Firmware/9_2_FPGA/tb/rbd_mode10_avg.csv
9_Firmware/9_2_FPGA/tb/rbd_mode10_ramp.csv
9_Firmware/9_2_FPGA/tb/rmc_autoscan.csv
9_Firmware/9_2_FPGA/tb_usb_data_interface.csv

# Co-sim intermediate CSVs (regenerated by scripts)
9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv

# macOS
.DS_Store

# Python
__pycache__/
*.pyc

# Local organization/archival folders (not part of repo source)
10_docs/

# Local simulation workspaces and generated outputs
5_Simulations/generated/
5_Simulations/aeris10_antenna_sim.py
5_Simulations/aeris10_radar_sim.py

# Local FPGA report dumps and scratch constraints
9_Firmware/9_2_FPGA/reports/
9_Firmware/9_2_FPGA/synth_only.xdc

# Local timing closure report snapshots
build*_reports/

# UART capture logs (generated by tools/uart_capture.py)
logs/