Added BOM and Gerbers

BOM and Gerbers, ready to be sent to PCB manufacturer
Remove radar system image from README
2026-04-22 01:04:28 +01:00 · 2026-04-20 19:04:08 +01:00 · 2026-04-19 19:06:44 +01:00 · 2026-04-19 19:04:48 +01:00 · 2026-04-19 01:27:15 +01:00
64 changed files with 967484 additions and 855115 deletions
@@ -0,0 +1,105 @@
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+"1";"56R";"R-EU_R0201";"R0201";"R22";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"R";"";"";
+"3";"5R";"RR0201";"R0201";"R132, R150, R152";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
+"2";"7.8pF";"CC0201";"C0201";"C61, C62";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
+"1";"830R";"R-EU_R0402";"R0402";"R36";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"R";"";"";
+"4";"840R";"RR0201";"R0201";"R78, R79, R80, R81";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
+"2";"AD8352ACPZ-R7";"AD8352ACPZ-R7";"CP_16_3_ADI";"U4, U8";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/ad8352.pdf";"2 GHz Ultralow Distortion Differential RF/IF Amplifier";"";"Analog Devices Inc";"AD8352ACPZ-R7";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"AD9484BCPZ-500";"AD9484BCPZ-500";"CP_56_5_ADI";"U1";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/AD9484.pdf";"8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter";"";"Analog Devices Inc";"AD9484BCPZ-500";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"AD9708AR";"AD9708AR";"RW_28_ADI";"U3";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"AD9708AR";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"ADAR1000ACCZN";"ADAR1000ACCZN";"CC-88-1_ADI";"ADAR1_, ADAR2_, ADAR3_, ADAR4_";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"ADAR1000ACCZN";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"RF";"";
+"3";"ADS7830IPWR";"ADS7830IPWR";"PW16";"U10, U88, U89";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/ads7830";"8-Bit, 8-Channel Sampling A/D Converter with I2C Interface 16-TSSOP -40 to 85";"";"Texas Instruments";"ADS7830IPWR";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"16";"ADTR1107ACCZ";"ADTR1107ACCZ";"CC-24-8_ADI";"ADTR1107_1, ADTR1107_2, ADTR1107_3, ADTR1107_4, ADTR1107_5, ADTR1107_6, ADTR1107_7, ADTR1107_8, ADTR1107_9, ADTR1107_10, ADTR1107_11, ADTR1107_12, ADTR1107_13, ADTR1107_14, ADTR1107_15, ADTR1107_16";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"ADTR1107ACCZ";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"RF";"";
+"1";"AT93C46A-10SQ-2.7";"AT93C46A-10SQ-2.7";"SOIC8";"IC1";"Three-wire Automotive Temperature Serial EEPROM 1K (64 x 16)";"";"";"";"";"";"";"";"";"";"";"";"";"";"AT93C46DN-SH-B";"1455086";"58M3879";"";"0";"";"";"";"";"";"";"";"";
+"5";"BLM15HB121SN1";"BLM15HB121SN1";"0402";"L5, L6, L7, L19, L20";"EMIFIL (R) Chip Ferrite Bead for GHz Noise";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"";"";"";
+"2";"BPF2";"BPF2";"BPF2";"U$2, U$3";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"Blue";"LED-BLUE0603";"LED-0603";"D2, D3, D4, D5";"Blue SMD LED";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"DIO-08575";"";"";"";"";"";"Blue";
+"2";"CJT-T-P-HH-ST-TH1";"CJT-T-P-HH-ST-TH1";"CJTTPHHSTTH1";"J19, J21";"Conn Twinax F 0Hz to 4GHz 100Ohm Solder ST Thru-Hole Gold";"";"";"";"";"Conn Twinax F 0Hz to 4GHz 100Ohm Solder ST Thru-Hole Gold";"7.31mm";"SAMTEC";"CJT-T-P-HH-ST-TH1";"";"";"200-CJTTPHHSTTH1";"https://www.mouser.co.uk/ProductDetail/Samtec/CJT-T-P-HH-ST-TH1?qs=PB6%2FjmICvI3dfW8RDpxn0g%3D%3D";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"DAC5578SRGET";"DAC5578SRGET";"RGE24_2P7X2P7";"U7, U69";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/dac5578";"8-bit, Octal Channel, Ultra-Low Glitch, Voltage Output, 2-Wire Interface DAC 24-VQFN -40 to 125";"";"Texas Instruments";"DAC5578SRGET";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"ECS-120-10-36B2-JTN-TR";"CRYSTAL-12MHZ";"CRYSTAL-SMD-2X2.5MM";"Y1";"12.0MHz Crystal";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"XTAL-15540";"";"";"";"";"";"";
+"1";"EP4RKU+";"EP4RKU+";"DG1677-2_MNC";"U16";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"EP4RKU+";"";"Mini Circuits";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"FT2232HQ";"FT2232HQ";"64QFN_FT2232HQ_FTD";"U6";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"";"";"FT2232HQ";"";"FTDI, Future Technology Devices International Ltd";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"16";"INA241A3IDGKRDGK0008A-MFG";"INA241A3IDGKRDGK0008A-MFG";"DGK0008A-MFG";"U11, U73, U74, U75, U76, U77, U78, U79, U80, U81, U82, U83, U84, U85, U86, U87";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"-5-V to 110-V bidirectional ultraprecise current sense amplifier with enhanced PWM rejection 8-VSSOP -40 to 125";"";"Texas Instruments";"INA241A3IDGKR";"";"";"";"";"";"";"";"";"";"";"";"";"RefDes";"";"";"";"TYPE";"";
+"2";"LTC5552IUDBTRMPBF";"LTC5552IUDBTRMPBF";"UDB_12_ADI";"U5, U13";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"LTC5552IUDB#TRMPBF";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"17";"M3SWA2-34DR+";"M3SWA2-34DR+";"16_QFN";"RF_SW_1, RF_SW_2, RF_SW_3, RF_SW_4, RF_SW_5, RF_SW_6, RF_SW_7, RF_SW_8, RF_SW_9, RF_SW_10, RF_SW_11, RF_SW_12, RF_SW_13, RF_SW_14, RF_SW_15, RF_SW_16, U$1";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"MINI-USB-32005-201";"MINI-USB-32005-201";"32005-201";"X2, X53";"MINI USB-B Conector";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"";"5";"";"";"";"";"";"";"";"";
+"1";"MOMENTARY-SWITCH-SPST-SMD-4.6X2.8MM";"MOMENTARY-SWITCH-SPST-SMD-4.6X2.8MM";"TACTILE_SWITCH_SMD_4.6X2.8MM";"S1";"Momentary Switch (Pushbutton) - SPST";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"SWCH-15606";"";"";"";"";"";"";
+"1";"MT25QL01GBBB8E12-0AUT";"MT25QL01GBBB8E12-0AUT";"BGA24_MT25QL_MRN";"U9";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"MT25QL01GBBB8E12-0AUT";"";"Micron";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"NX3215SA-32.768KHz";"NX3225GD-8MHZ-STD-CRA-3";"XTAL_NX3225GD-8MHZ-STD-CRA-3_N";"XTAL3";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"NX3225GD-8MHZ-STD-CRA-3";"";"NDK";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"NX3225GD-8MHZ-STD-CRA-3";"NX3225GD-8MHZ-STD-CRA-3";"XTAL_NX3225GD-8MHZ-STD-CRA-3_N";"XTAL1";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"NX3225GD-8MHZ-STD-CRA-3";"";"NDK";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"OPA4703EA/250";"OPA4703EA/250";"PW14";"OPA_1, OPA_2, OPA_3, OPA_4";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/opa4703";"Quad, 12-V, 1-MHz, low-offset operational amplifier 14-TSSOP -40 to 85";"";"Texas Instruments";"OPA4703EA/250";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"STM32F746ZGT7";"STM32F746ZGT7";"LQFP-144_STM";"U2";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"STM32F746ZGT7";"";"STMicroelectronics";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"34";"SZMMSZ5232BT1G";"SZMMSZ5232BT1G";"SOD-123_ONS";"U14, U15, U17, U37, U38, U39, U40, U41, U43, U44, U45, U46, U47, U48, U49, U50, U51, U52, U53, U54, U55, U56, U57, U58, U59, U60, U61, U62, U63, U64, U65, U66, U67, U68";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"SZMMSZ5232BT1G";"";"onsemi";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"XC7A50T-2FTG256I";"XC7A50T-2FTG256I";"BGA256C100P16X16_1700X1700X155";"U42";"Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA  Check availability";"In Stock";"https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=eda";"";"";"                                                      Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA                                              ";"";"";"";"Xilinx Inc.";"";"";"";"XC7A50T-2FTG256I";"";"";"";"LBGA-256 Xilinx Inc.";"";"None";"";"";"https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=snap";"";"";"";"";
@@ -1,8 +1,8 @@
 Generated by EAGLE CAM Processor 7.4.0

-Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.dri
+Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.dri

- Date              : 06/04/2026 22:10
+ Date              : 19/04/2026 23:21
 Drills            : generated
 Device            : Excellon drill station, coordinate format 2.5 inch

@@ -27,8 +27,8 @@ Drills used:

 Code  Size       used

- T01   0.0059inch  1609
- T02   0.0079inch  1892
+ T01   0.0059inch  1604
+ T02   0.0079inch  2243
 T03   0.0100inch    18
 T04   0.0118inch   355
 T05   0.0138inch   113
@@ -43,8 +43,8 @@ Drills used:
 T14   0.0472inch     4
 T15   0.1260inch     8

-Total number of drills: 4438
+Total number of drills: 4784

 Plotfiles:

- C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.drd
+ C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.drd
@@ -1,9 +1,9 @@
 Generated by EAGLE CAM Processor 7.4.0

-Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.gpi
+Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.gpi

- Date              : 06/04/2026 22:41
- Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.bsk
+ Date              : 19/04/2026 23:50
+ Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.bsk
 Apertures         : generated: 
 Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch

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 D32*
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-X0059071Y0045291D03*
-X0061039Y0045291D03*
-X0063008Y0045291D03*
 X0054150Y0061630D03*
 X0051787Y0061630D03*
 X0048441Y0061630D03*
@@ -4153,40 +4189,29 @@ X0030724Y0041157D03*
 X0033283Y0041157D03*
 X0035646Y0041157D03*
 X0038205Y0041157D03*
-X0063992Y0079937D03*
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-X0066551Y0083087D03*
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-X0064583Y0086433D03*
-X0066748Y0088992D03*
-X0070094Y0088598D03*
-X0071276Y0085449D03*
-X0069307Y0082693D03*
-X0066551Y0079937D03*
-X0074228Y0088402D03*
 D16*
-X0076000Y0051197D03*
-X0079937Y0051197D03*
-X0083874Y0051197D03*
-X0087811Y0051197D03*
-X0091748Y0051197D03*
-X0095685Y0051197D03*
-X0095685Y0044685D03*
-X0091748Y0045276D03*
-X0087811Y0045276D03*
-X0083874Y0045276D03*
-X0079937Y0045276D03*
-X0076000Y0045276D03*
-X0054150Y0045079D03*
-X0050213Y0045079D03*
-X0046276Y0045079D03*
-X0042339Y0045079D03*
 X0038402Y0045079D03*
-X0034465Y0045079D03*
-X0034465Y0051000D03*
-X0038402Y0051000D03*
-X0042339Y0051000D03*
-X0046276Y0051000D03*
-X0050213Y0051000D03*
+X0042339Y0045079D03*
+X0046276Y0045079D03*
+X0050213Y0045079D03*
+X0054150Y0045079D03*
 X0054150Y0051000D03*
+X0050213Y0051000D03*
+X0046276Y0051000D03*
+X0042339Y0051000D03*
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+X0083874Y0045276D03*
+X0087811Y0045276D03*
+X0091748Y0045276D03*
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+X0091748Y0051197D03*
+X0087811Y0051197D03*
+X0083874Y0051197D03*
+X0079937Y0051197D03*
+X0076000Y0051197D03*
 M02*
@@ -33,60 +33,30 @@ X56315Y57299
 X56315Y54937
 X56315Y52772
 X56315Y50606
-X57102Y45291
-X57102Y43126
-X57102Y40961
-X57102Y38992
-X57102Y37024
-X57102Y35055
-X59071Y35055
-X61039Y35055
-X61039Y37024
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-X59071Y38992
-X59071Y37024
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-X61039Y40961
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-X63008Y35055
-X64976Y35055
-X64976Y37024
-X64976Y38992
-X64976Y40961
-X66945Y40961
-X68913Y40961
-X68913Y38992
-X66945Y38992
-X66945Y37024
-X68913Y37024
-X68913Y35055
-X66945Y35055
-X70882Y35055
-X72850Y35055
-X72850Y37024
-X70882Y37024
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-X72850Y38992
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-X70882Y43126
-X72850Y43126
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-X68913Y45291
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-X64976Y45291
-X64976Y43126
-X66945Y43126
-X68913Y43126
-X63008Y43126
-X61039Y43126
-X59071Y43126
-X59071Y45291
-X61039Y45291
-X63008Y45291
+X59477Y51237
+X59526Y53881
+X59526Y56672
+X59477Y59365
+X62171Y59316
+X62122Y56672
+X62219Y53881
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+X62268Y48495
+X65060Y48446
+X64913Y51188
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+X64913Y56623
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+X67753Y48544
+X70300Y48593
+X70251Y51041
 X73835Y50606
 X73835Y52772
 X73835Y55134
@@ -113,19 +83,62 @@ X71276Y85449
 X69307Y82693
 X66551Y79937
 X74228Y88402
+X59428Y48446
+X59071Y45291
+X61039Y45291
+X63008Y45291
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+X61039Y43126
+X59071Y43126
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+X61039Y40961
+X61039Y38992
+X59071Y38992
+X59071Y37024
+X61039Y37024
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+X63008Y40961
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+X64976Y38992
+X64976Y37024
+X64976Y35055
+X66945Y35055
+X68913Y35055
+X68913Y37024
+X68913Y38992
+X66945Y38992
+X66945Y37024
+X66945Y40961
+X68913Y40961
+X68913Y43126
+X66945Y43126
+X64976Y43126
+X64976Y45291
+X66945Y45291
+X68913Y45291
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+X72850Y45291
+X72850Y43126
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+X70882Y40961
+X72850Y40961
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+X70882Y35055
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+X61039Y35055
+X59071Y35055
+X57102Y35055
+X57102Y37024
+X57102Y38992
+X57102Y40961
+X57102Y43126
+X57102Y45291
 T02
-X76000Y51197
-X79937Y51197
-X83874Y51197
-X87811Y51197
-X91748Y51197
-X95685Y51197
-X95685Y44685
-X91748Y45276
-X87811Y45276
-X83874Y45276
-X79937Y45276
-X76000Y45276
 X54150Y45079
 X50213Y45079
 X46276Y45079
@@ -138,24 +151,25 @@ X42339Y51000
 X46276Y51000
 X50213Y51000
 X54150Y51000
+X76000Y51197
+X79937Y51197
+X83874Y51197
+X87811Y51197
+X91748Y51197
+X95685Y51197
+X95685Y44685
+X91748Y45276
+X87811Y45276
+X83874Y45276
+X79937Y45276
+X76000Y45276
 T03
-X50409Y39386
-X49819Y33874
-X50409Y26787
-X55724Y29150
-X59661Y25409
-X63992Y30331
-X66748Y24819
-X70094Y30134
-X72850Y26000
-X76000Y30331
-X78559Y24425
+X78756Y38205
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+X80921Y33283
 X82299Y27969
 X84661Y24622
 X85252Y31118
-X80921Y33283
-X78756Y38205
-X80724Y41354
 X91551Y31709
 X91945Y27181
 X97063Y28756
@@ -317,6 +331,17 @@ X8087Y52969
 X40567Y25016
 X43520Y28756
 X42929Y31709
+X49819Y33874
+X50409Y39386
+X55724Y29150
+X59661Y25409
+X63992Y30331
+X66748Y24819
+X70094Y30134
+X72850Y26000
+X76000Y30331
+X78559Y24425
+X50409Y26787
 X110055Y25016
 X110646Y29346
 X110449Y32299
@@ -2,14 +2,14 @@ Generated by EAGLE CAM Processor 7.4.0

 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.dri

- Date              : 05/04/2026 00:08
+ Date              : 19/04/2026 01:42
 Drills            : generated
 Device            : Excellon drill station, coordinate format 2.5 inch

 Parameter settings:

- Tolerance Drill + :  2.50 %
- Tolerance Drill - :  2.50 %
+ Tolerance Drill + :  0.00 %
+ Tolerance Drill - :  0.00 %
 Rotate            : no
 Mirror            : no
 Optimize          : yes
@@ -27,7 +27,7 @@ Drills used:

 Code  Size       used

- T01   0.0059inch   103
+ T01   0.0059inch   128
 T02   0.0079inch    24
 T03   0.0138inch   215
 T04   0.0394inch     5
@@ -35,7 +35,7 @@ Drills used:
 T06   0.0520inch     2
 T07   0.1260inch     7

-Total number of drills: 364
+Total number of drills: 389

 Plotfiles:

@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0

 Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.gpi

- Date              : 05/04/2026 00:07
+ Date              : 19/04/2026 01:42
 Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.fab
 Apertures         : generated: 
 Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
@@ -0,0 +1,10 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+M02*
@@ -0,0 +1,10 @@
+G75*
+%MOIN*%
+%OFA0B0*%
+%FSLAX25Y25*%
+%IPPOS*%
+%LPD*%
+%AMOC8*
+5,1,8,0,0,1.08239X$1,22.5*
+%
+M02*
@@ -0,0 +1,29 @@
+"Qty";"Value";"Device";"Package";"Parts";"Description";"COPYRIGHT";"DATASHEET";"DESCRIPTION";"HEIGHT";"MANUFACTURER_NAME";"MANUFACTURER_PART_NUMBER";"MF";"MFR_NAME";"MOUSER_PART_NUMBER";"MOUSER_PRICE-STOCK";"MPN";"OC_FARNELL";"OC_NEWARK";"POPULARITY";"REFDES";"SPICEPREFIX";"TYPE";
+"1";"";"AK300/2";"AK300/2";"X1";"CONNECTOR";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"16";"";"";"";
+"1";"";"MA10-2";"MA10-2";"SV1";"PIN HEADER";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"3";"";"";"";
+"21";"0.1µF";"C-EUC0805";"C0805";"C1, C6, C12, C18, C29, C30, C36, C42, C54, C60, C66, C71, C76, C77, C83, C89, C109, C119, C129, C144, C154";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"27";"10k";"R-EU_M0805";"M0805";"R2, R4, R6, R8, R10, R12, R14, R16, R18, R20, R22, R24, R26, R28, R30, R32, R34, R36, R38, R40, R42, R44, R46, R48, R50, R52, R56";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"4";"10nF";"C-EUC0603";"C0603";"C150, C152, C160, C162";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"4";"10µF";"C-EUC0603";"C0603";"C151, C153, C161, C163";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"60";"10µF";"C-EUC0805";"C0805";"C4, C5, C9, C10, C15, C16, C21, C22, C24, C25, C28, C33, C34, C39, C40, C45, C46, C50, C51, C52, C53, C57, C58, C63, C64, C69, C70, C74, C75, C80, C81, C86, C87, C92, C93, C94, C95, C108, C112, C113, C114, C115, C118, C122, C123, C124, C125, C128, C132, C133, C134, C135, C138, C139, C140, C143, C147, C148, C157, C158";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"2";"11.5k";"R-EU_M0805";"M0805";"R54, R58";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"4";"12k";"R-EU_M0805";"M0805";"R9, R35, R43, R47";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"13.7k";"R-EU_M0805";"M0805";"R3";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"12";"1µF";"C-EUC0805";"C0805";"C26, C27, C106, C107, C116, C117, C126, C127, C136, C137, C141, C142";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"2";"2.2µH";"POWER_INDUCTOR";"IND_VLP8040T-1R0N_TDK";"U$1, U$2";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"35";"22-23-2021";"22-23-2021";"22-23-2021";"X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32, X33, X34, X35, X36";".100" (2.54mm) Center Header - 2 Pin";"";"";"";"";"";"";"MOLEX";"";"";"";"22-23-2021";"1462926";"25C3832";"40";"";"";"";
+"52";"22µF";"C-EUC0603";"C0603";"C2, C3, C7, C8, C11, C13, C14, C17, C19, C20, C23, C31, C32, C35, C37, C38, C41, C43, C44, C47, C48, C49, C55, C56, C59, C61, C62, C65, C67, C68, C72, C73, C78, C79, C82, C84, C85, C88, C90, C91, C110, C111, C120, C121, C130, C131, C145, C146, C149, C155, C156, C159";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"1";"23.4k";"R-EU_M0805";"M0805";"R49";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"2k";"R-EU_M0805";"M0805";"R39";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"3.09k";"R-EU_M0805";"M0805";"R1";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"19";"3.3µH";"POWER_INDUCTOR";"IND_VLP8040T-1R0N_TDK";"U$3, U$4, U$5, U$6, U$7, U$8, U$9, U$10, U$11, U$12, U$13, U$14, U$15, U$16, U$17, U$18, U$19, U$20, U$21";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"6";"32.2k";"R-EU_M0805";"M0805";"R5, R7, R11, R13, R15, R19";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"34.8k";"R-EU_M0805";"M0805";"R21";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"2";"35.7k";"R-EU_M0805";"M0805";"R53, R57";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"11";"56.2k";"R-EU_M0805";"M0805";"R17, R23, R25, R27, R29, R31, R37, R41, R45, R51, R55";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"61.9k";"R-EU_M0805";"M0805";"R33";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"6";"ADM7151ACPZ-04-R7";"ADM7151ACPZ-04-R7";"CP_8_11_ADI";"U5, U23, U25, U27, U29, U30";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/ADM7151.pdf";"800 mA Ultralow Noise, High PSRR, RF Linear Regulator";"";"Analog Devices Inc";"ADM7151ACPZ-04-R7";"";"";"";"";"";"";"";"";"";"";"";
+"5";"LM2662MX/NOPB";"LM2662MX/NOPB";"M08A";"U18, U19, U20, U21, U22";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"LM2662MX/NOPB";"";"Texas Instruments";"";"";"";"";"";"";"";"";"LM2662M";
+"10";"T521W476M020ATE045";"T521W476M020ATE045";"T521W";"C96, C97, C98, C99, C100, C101, C102, C103, C104, C105";"T521, Tantalum, Polymer Tantalum, Commercial Grade, 47 uF, 20%, 20 VDC, 105C, -55C, 105C, SMD, Polymer, Molded, Low Profile/ESR, NonCombustible, 2,000 Hrs, 9 % , 45 mOhms, 94 uA, 222.95 mg, 7343, 1.4mm, Height Max = 1.5mm, 1000, 52  Weeks";"";"";"T521, Tantalum, Polymer Tantalum, Commercial Grade, 47 uF, 20%, 20 VDC, 105C, -55C, 105C, SMD, Polymer, Molded, Low Profile/ESR, NonCombustible, 2,000 Hrs, 9 % , 45 mOhms, 94 uA, 222.95 mg, 7343, 1.4mm, Height Max = 1.5mm, 1000, 52  Weeks";"1.5mm";"KEMET";"T521W476M020ATE045";"";"";"80-T521W476M20ATE045";"https://www.mouser.co.uk/ProductDetail/KEMET/T521W476M020ATE045?qs=Ad%252Bh9aq9FyVtchBw1jwoFA%3D%3D";"";"";"";"";"";"";"";
+"21";"TPS562208DDCT";"TPS562208DDCT";"DDC0006A_N";"U1, U2, U3, U4, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, U17, U24, U26, U28, U31, U33";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/tps562208";"4.5 V to 17 V input, 2 A output, synchronous step-down converter in FCCM mode 6-SOT-23-THIN -40 to 125";"";"Texas Instruments";"TPS562208DDCT";"";"";"";"";"";"";"";"";"RefDes";"";"TYPE";
+"2";"TPS7A8300RGRR";"TPS7A8300RGRR";"RGR20_2P05X2P05_TEX";"U32, U34";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/tps7a8300";"2-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi 20-VQFN -40 to 125";"";"Texas Instruments";"TPS7A8300RGRR";"";"";"";"";"";"";"";"";"";"";"";
@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0

 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.dri

- Date              : 04/04/2026 22:46
+ Date              : 19/04/2026 19:18
 Drills            : generated
 Device            : Excellon drill station, coordinate format 2.5 inch

@@ -0,0 +1,36 @@
+Generated by EAGLE CAM Processor 7.4.0
+
+Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.gpi
+
+ Date              : 19/04/2026 19:21
+ Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.bsp
+ Apertures         : generated: 
+ Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
+
+Parameter settings:
+
+ Emulate Apertures : no
+ Tolerance Draw  + :  0.00 %
+ Tolerance Draw  - :  0.00 %
+ Tolerance Flash + :  0.00 %
+ Tolerance Flash - :  0.00 %
+ Rotate            : no
+ Mirror            : no
+ Optimize          : yes
+ Auto fit          : yes
+ OffsetX           : 0inch
+ OffsetY           : 0inch
+
+Plotfile Info:
+
+ Coordinate Format : 2.5
+ Coordinate Units  : Inch
+ Data Mode         : Absolute
+ Zero Suppression  : None
+ End Of Block      : *
+
+Apertures used:
+
+ Code     Shape     Size                  used
+
+
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@@ -369,12 +322,24 @@ X0250953Y0209811D03*
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@@ -390,10 +355,24 @@ X0272213Y0227921D03*
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@@ -403,11 +382,30 @@ X0230480Y0145835D03*
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 X0109417Y0061386D03*
 X0061780Y0026543D03*
-X0033236Y0247016D03*
 D16*
 X0140520Y0263551D03*
 D17*
@@ -134,8 +134,10 @@ X0045441Y0113945D03*
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@@ -182,14 +184,10 @@ X0294063Y0355677D03*
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 X0047921Y0382843D03*
-X0086386Y0388748D03*
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 D15*
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@@ -349,13 +349,6 @@ X0061780Y0026543D03*
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@@ -374,6 +367,11 @@ X0139535Y0349378D03*
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@@ -0,0 +1,41 @@
+"Qty";"Value";"Device";"Package";"Parts";"Description";"COPYRIGHT";"DESCRIPTION";"HEIGHT";"MANUFACTURER_NAME";"MANUFACTURER_PART_NUMBER";"MF";"MFR_NAME";"MOUSER_PART_NUMBER";"MOUSER_PRICE-STOCK";"MPN";"OC_FARNELL";"OC_NEWARK";"POPULARITY";"PROD_ID";"SPICEPREFIX";"VALUE";
+"3";"";"C-EUC0201";"C0201";"C4, C5, C7";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"5";"";"L-EUL5650M";"L5650M";"L9, L10, L11, L12, L13";"INDUCTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"L";"";
+"1";"";"PINHD-2X6";"2X06";"JP1";"PIN HEADER";"";"";"";"";"";"";"";"";"";"";"";"";"8";"";"";"";
+"1";"";"PINHD-2X7";"2X07";"JP2";"PIN HEADER";"";"";"";"";"";"";"";"";"";"";"";"";"8";"";"";"";
+"25";"0.1µF";"C-EUC0201";"C0201";"C16, C18, C20, C22, C24, C26, C28, C30, C32, C34, C35, C36, C37, C41, C42, C43, C44, C64, C65, C66, C67, C87, C88, C90, C91";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"1";"0.1µf";"C-EUC0201";"C0201";"C92";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"0.33µF";"C-EUC0201";"C0201";"C2, C6";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"0.47µF";"C-EUC0201";"C0201";"C9, C10";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"1";"0.47µf";"C-EUC0201";"C0201";"C3";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"3";"0.65k";"R-EU_R0201";"R0201";"R6, R8, R10";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"9";"0R";"R-EU_R0201";"R0201";"R5, R14, R15, R19, R20, R27, R28, R32, R33";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"8";"1.3nH";"L-USL0201";"L0201";"L1, L2, L3, L4, L5, L6, L7, L8";"INDUCTOR, American symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"L";"";
+"1";"1000pF";"C-EUC0201";"C0201";"C8";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"4";"100R";"R-EU_R0201";"R0201";"R1, R12, R13, R26";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"2";"10nF";"C-EUC0201";"C0201";"C61, C84";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"3";"10nF";"C-EUC0402";"C0402";"C15, C17, C19";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"18";"";"C";"";
+"6";"10pF";"C-EUC0201";"C0201";"C1, C62, C63, C85, C86, C89";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"5";"10µF";"C-EUC1210";"C1210";"C23, C27, C31, C45, C47";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"11";"142-0731-211";"142-0731-211";"1420731211";"J1, J2, J5, J6, J7, J8, J9, J10, J11, J12, J13";"SMA Connector Jack, Female Socket 50 Ohms Through Hole Solder";"";"SMA Connector Jack, Female Socket 50 Ohms Through Hole Solder";"9.8852mm";"Cinch Connectivity Solutions";"142-0731-211";"";"";"530-142-0731-211";"https://www.mouser.co.uk/ProductDetail/Johnson-Cinch-Connectivity-Solutions/142-0731-211?qs=HFfMDpzxxd0OVzI3hm9tuA%3D%3D";"";"";"";"";"";"";"";
+"6";"1k";"R-EU_R0201";"R0201";"R2, R3, R4, R7, R9, R11";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"10";"1µF";"C-EUC0201";"C0201";"C11, C12, C13, C14, C59, C68, C69, C70, C71, C82";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"8";"200k";"R-EU_R0201";"R0201";"R22, R23, R24, R25, R35, R36, R37, R38";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"6";"22-23-2021";"22-23-2021";"22-23-2021";"X10, X11, X12, X13, X14, X15";".100" (2.54mm) Center Header - 2 Pin";"";"";"";"";"";"MOLEX";"";"";"";"22-23-2021";"1462926";"25C3832";"40";"";"";"";
+"3";"22R";"R-EU_R0201";"R0201";"R39, R40, R41";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"6";"22µF";"C-EUC1210";"C1210";"C21, C25, C29, C33, C46, C51";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"30R";"R-EU_R0201";"R0201";"R17, R30";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"2";"31pF";"C-EUC0201";"C0201";"C60, C83";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"330R";"R-EU_R0201";"R0201";"R18, R31";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"20";"4.7µF";"C-EUC0201";"C0201";"C38, C39, C40, C48, C49, C50, C55, C56, C57, C58, C72, C73, C74, C75, C76, C77, C78, C79, C80, C81";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"500R";"R-EU_R0201";"R0201";"R21, R34";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"2";"931R";"R-EU_R0201";"R0201";"R16, R29";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"1";"AD9523BCPZ";"AD9523BCPZ";"QFN50P1000X1000X100-73N";"IC1";"AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ";"";"AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ";"mm";"Analog Devices";"AD9523BCPZ";"";"";"584-AD9523BCPZ";"https://www.mouser.com/Search/Refine.aspx?Keyword=584-AD9523BCPZ";"";"";"";"";"";"";"";
+"2";"ADF4382ABCCZ";"ADF4382ABCCZ";"CC-48-10_ADI";"U1, U6";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"ADF4382ABCCZ";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";
+"4";"ATS1005-3DB-FD-T05";"ATS1005-3DB-FD-T05";"SMT_DB-FD-T05_SUS";"U4, U5, U8, U10";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Susumu";"ATS1005-3DB-FD-T05";"";"";"";"";"";"";"";"";"";"";"";
+"2";"CJT-T-P-HH-ST-TH1";"CJT-T-P-HH-ST-TH1";"CONN_CJT-T-P-XX-ST-TH1_SAI";"J3, J4";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Samtec Inc";"CJT-T-P-HH-ST-TH1";"";"";"";"";"";"";"";"";"";"";"";
+"2";"CVHD-950-50.000";"CVHD-950-50.000";"SMD4_CVHD-950_CRX";"X5, X6";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Crystek Crystals";"CVHD-950-50.000";"";"";"";"";"";"";"";"";"";"";"";
+"1";"ECOC-2522-100.000-3HC";"ECOC-2522-100.000-3HC";"SMD5_ECOC-2522_25P4X22_ECS";"X4";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"ECS International";"ECOC-2522-100.000-3HC";"";"";"";"";"";"";"";"";"";"";"";
+"4";"FBMH1608HL601-T";"FBMH1608HL601-T";"BEADC1608X90N";"FB1, FB2, FB3, FB4";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"Green";"LED-GREEN-0603-WE";"LED-0603";"D1, D2";"Green SMD LED";"";"";"";"";"";"";"";"";"";"";"";"";"";"DIO-16512";"";"Green";
+"4";"MTX2-143+";"MTX2-143+";"DQ1225_MNC";"U2, U3, U7, U9";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"MTX2-143+";"";"Mini Circuits";"";"";"";"";"";"";"";"";"";
@@ -798,8 +798,6 @@ X127429Y228217
 X118177Y228118
 X109220Y227921
 X100854Y226740
-X102724Y234713
-X102724Y234713
 X102724Y243571
 X102823Y255579
 X102528Y264437
@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0

 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.dri

- Date              : 05/04/2026 01:09
+ Date              : 19/04/2026 21:57
 Drills            : generated
 Device            : Excellon drill station, coordinate format 2.5 inch

@@ -33,13 +33,13 @@ Drills used:
 T04   0.0197inch    34
 T05   0.0250inch     4
 T06   0.0330inch     8
- T07   0.0394inch    84
+ T07   0.0394inch    82
 T08   0.0400inch    26
 T09   0.0470inch    44
 T10   0.0787inch     1
 T11   0.1260inch     4

-Total number of drills: 909
+Total number of drills: 907

 Plotfiles:

@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0

 Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.gpi

- Date              : 05/04/2026 01:12
+ Date              : 19/04/2026 21:58
 Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.bsk
 Apertures         : generated: 
 Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
@@ -0,0 +1,174 @@
+C1 48.37 59.91  90 10pF C0201
+C2 31.74 13.52   0 0.33ｵF C0201
+C3 49.46 45.72   0 0.47ｵf C0201
+C4 49.48 43.39   0  C0201
+C5 49.52 42.39   0  C0201
+C6 49.52 41.92   0 0.33ｵF C0201
+C7 49.51 40.39   0  C0201
+C8 49.51 39.87   0 1000pF C0201
+C9 48.76 37.89  90 0.47ｵF C0201
+C10 48.63 39.42   0 0.47ｵF C0201
+C11 47.37 50.30 270 1ｵF C0201
+C12 46.81 50.30 270 1ｵF C0201
+C13 45.40 50.35 270 1ｵF C0201
+C14 44.82 50.35 270 1ｵF C0201
+C15 86.78 30.16   0 10nF C0402
+C16 49.07 44.65  90 0.1ｵF C0201
+C17 64.58 24.27 270 10nF C0402
+C18 50.57 34.64 180 0.1ｵF C0201
+C19 52.86 24.27 270 10nF C0402
+C20 55.66 34.54   0 0.1ｵF C0201
+C21 10.00 30.60 270 22ｵF C1210
+C22 58.71 34.53   0 0.1ｵF C0201
+C23 21.00 30.50 270 10ｵF C1210
+C24 62.13 37.42   0 0.1ｵF C0201
+C25 35.40  4.90 270 22ｵF C1210
+C26 61.84 40.65  90 0.1ｵF C0201
+C27 45.90  5.30 270 10ｵF C1210
+C28 62.06 43.41   0 0.1ｵF C0201
+C29 81.20  4.90 270 22ｵF C1210
+C30 57.71 46.83   0 0.1ｵF C0201
+C31 70.50  5.00 270 10ｵF C1210
+C32 54.48 46.90  90 0.1ｵF C0201
+C33 18.10 95.10  90 22ｵF C1210
+C34 49.20 38.86 180 0.1ｵF C0201
+C35 57.21 34.54   0 0.1ｵF C0201
+C36 61.16 34.74   0 0.1ｵF C0201
+C37 62.20 38.96   0 0.1ｵF C0201
+C38 42.23 55.44 180 4.7ｵF C0201
+C39 42.56 52.07 270 4.7ｵF C0201
+C40 46.11 50.52   0 4.7ｵF C0201
+C41 62.26 41.88   0 0.1ｵF C0201
+C42 61.85 45.25  90 0.1ｵF C0201
+C43 56.56 46.73   0 0.1ｵF C0201
+C44 52.33 46.82 180 0.1ｵF C0201
+C45 19.40 85.70 180 10ｵF C1210
+C46 34.30 93.80 270 22ｵF C1210
+C47 30.90 86.70   0 10ｵF C1210
+C48 48.11 50.54   0 4.7ｵF C0201
+C49 48.11 50.06   0 4.7ｵF C0201
+C50 51.64 53.12 270 4.7ｵF C0201
+C51 87.70 87.30  90 22ｵF C1210
+C55 44.21 59.60   0 4.7ｵF C0201
+C56 51.86 59.44 180 4.7ｵF C0201
+C57 51.69 57.60  90 4.7ｵF C0201
+C58 51.62 54.17 270 4.7ｵF C0201
+C59 49.65 49.57  90 1ｵF C0201
+C60 52.95 54.60  90 31pF C0201
+C61 53.66 52.04   0 10nF C0201
+C62 49.86 50.62 270 10pF C0201
+C63 45.84 61.00  90 10pF C0201
+C64 46.57 61.00  90 0.1ｵF C0201
+C65 45.15 61.00  90 0.1ｵF C0201
+C66 49.11 59.94  90 0.1ｵF C0201
+C67 47.66 59.94  90 0.1ｵF C0201
+C68 61.74 50.36 270 1ｵF C0201
+C69 61.19 50.33 270 1ｵF C0201
+C70 59.82 50.03 270 1ｵF C0201
+C71 59.19 50.02 270 1ｵF C0201
+C72 66.00 53.21 270 4.7ｵF C0201
+C73 66.10 54.16 270 4.7ｵF C0201
+C74 66.04 57.61  90 4.7ｵF C0201
+C75 64.72 59.83 180 4.7ｵF C0201
+C76 58.07 59.64   0 4.7ｵF C0201
+C77 56.62 55.38 180 4.7ｵF C0201
+C78 56.92 52.33 180 4.7ｵF C0201
+C79 60.47 50.84   0 4.7ｵF C0201
+C80 62.25 50.66 270 4.7ｵF C0201
+C81 62.70 50.66 270 4.7ｵF C0201
+C82 64.80 49.14 180 1ｵF C0201
+C83 67.62 55.61  90 31pF C0201
+C84 68.70 54.96  90 10nF C0201
+C85 63.74 50.66 270 10pF C0201
+C86 60.20 61.00  90 10pF C0201
+C87 60.94 61.00  90 0.1ｵF C0201
+C88 59.44 61.00  90 0.1ｵF C0201
+C89 62.70 59.91  90 10pF C0201
+C90 63.47 59.91  90 0.1ｵF C0201
+C91 61.97 59.91  90 0.1ｵF C0201
+C92 16.93 67.92 180 0.1ｵf C0201
+D1 41.75 59.88  90 Green LED-0603
+D2 56.83 60.61  90 Green LED-0603
+FB1 68.41 56.87 180 FBMH1608HL601-T BEADC1608X90N
+FB2 53.58 56.01 180 FBMH1608HL601-T BEADC1608X90N
+FB3 52.06 49.65   0 FBMH1608HL601-T BEADC1608X90N
+FB4 63.46 48.33 270 FBMH1608HL601-T BEADC1608X90N
+IC1 55.70 40.67   0 AD9523BCPZ QFN50P1000X1000X100-73N
+J1 52.94 90.00   0 142-0731-211 1420731211
+J2 92.86 49.36  90 142-0731-211 1420731211
+J5 64.56 17.84   0 142-0731-211 1420731211
+J6 52.79 18.27   0 142-0731-211 1420731211
+J7 92.71 30.20  90 142-0731-211 1420731211
+J8 92.71 16.28   0 142-0731-211 1420731211
+J9  9.85 82.37 180 142-0731-211 1420731211
+J10 45.93 74.00   0 142-0731-211 1420731211
+J11 60.20 74.00   0 142-0731-211 1420731211
+J12 74.38 71.98  45 142-0731-211 1420731211
+J13 11.67 67.91  90 142-0731-211 1420731211
+L1 48.80 59.32   0 1.3nH L0201
+L2 46.29 60.40   0 1.3nH L0201
+L3 45.44 60.40   0 1.3nH L0201
+L4 47.95 59.32   0 1.3nH L0201
+L5 60.67 60.40   0 1.3nH L0201
+L6 59.77 60.40   0 1.3nH L0201
+L7 63.17 59.31   0 1.3nH L0201
+L8 62.27 59.31   0 1.3nH L0201
+L9 15.40 31.90 180  L5650M
+L10 40.80  6.20 180  L5650M
+L11 75.80  6.30   0  L5650M
+L12 22.20 91.00  90  L5650M
+L13 29.60 92.70  90  L5650M
+R1 61.47 51.11   0 100R R0201
+R2  7.14 58.81 180 1k R0201
+R3  7.38 59.72 270 1k R0201
+R4 31.78 14.16   0 1k R0201
+R5 48.02 38.16   0 0R R0201
+R6 16.38 13.37 270 0.65k R0201
+R7 16.37 12.32 270 1k R0201
+R8 13.86 21.50  90 0.65k R0201
+R9 13.82 22.69  90 1k R0201
+R10 16.36 21.55  90 0.65k R0201
+R11 16.42 22.70  90 1k R0201
+R12 47.11 51.07   0 100R R0201
+R13 45.11 51.07   0 100R R0201
+R14 51.74 56.17 270 0R R0201
+R15 51.96 55.04   0 0R R0201
+R16 52.78 53.71 180 931R R0201
+R17 52.48 52.85  90 30R R0201
+R18 52.71 52.07   0 330R R0201
+R19 51.62 50.89   0 0R R0201
+R20 50.61 50.88   0 0R R0201
+R21 42.53 57.17 270 500R R0201
+R22 41.78 56.69 270 200k R0201
+R23 41.34 55.73  90 200k R0201
+R24 42.32 54.09 270 200k R0201
+R25 41.39 54.64 270 200k R0201
+R26 59.47 51.16   0 100R R0201
+R27 65.87 56.55   0 0R R0201
+R28 65.90 55.35   0 0R R0201
+R29 66.92 55.36 180 931R R0201
+R30 67.63 54.52  90 30R R0201
+R31 68.47 54.26   0 330R R0201
+R32 65.46 50.90   0 0R R0201
+R33 64.54 50.90   0 0R R0201
+R34 56.82 58.21 270 500R R0201
+R35 56.94 56.71 270 200k R0201
+R36 55.84 56.16 270 200k R0201
+R37 56.84 54.16 270 200k R0201
+R38 56.24 54.61 270 200k R0201
+R39 63.22 41.38   0 22R R0201
+R40 59.45 33.47 270 22R R0201
+R41 57.97 33.47 270 22R R0201
+U1 47.12 55.12 180 ADF4382ABCCZ CC-48-10_ADI
+U2 45.91 65.00 270 MTX2-143+ DQ1225_MNC
+U3 52.91 64.38 270 MTX2-143+ DQ1225_MNC
+U4 45.91 68.00 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U5 52.94 68.68 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U6 61.48 55.12 180 ADF4382ABCCZ CC-48-10_ADI
+U7 60.21 65.00 270 MTX2-143+ DQ1225_MNC
+U8 60.20 68.00 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U9 67.91 65.62 225 MTX2-143+ DQ1225_MNC
+U10 70.09 67.84 135 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+X4 23.07 49.95   0 ECOC-2522-100.000-3HC SMD5_ECOC-2522_25P4X22_ECS
+X5 34.12 31.62  90 CVHD-950-50.000 SMD4_CVHD-950_CRX
+X6 33.87 19.97  90 CVHD-950-50.000 SMD4_CVHD-950_CRX
@@ -159,8 +159,6 @@ X0127429Y0228217D03*
 X0118177Y0228118D03*
 X0109220Y0227921D03*
 X0100854Y0226740D03*
-X0102724Y0234713D03*
-X0102724Y0234713D03*
 X0102724Y0243571D03*
 X0102823Y0255579D03*
 X0102528Y0264437D03*
@@ -1334,10 +1334,8 @@ X0102528Y0273197D03*
 X0102528Y0264437D03*
 X0102823Y0255579D03*
 X0102724Y0243571D03*
-X0102724Y0234713D03*
-X0102724Y0234713D03*
-X0100854Y0226740D03*
 X0109220Y0227921D03*
+X0100854Y0226740D03*
 X0118177Y0228118D03*
 X0127429Y0228217D03*
 X0136976Y0228217D03*
@@ -868,22 +868,11 @@ void ADAR1000Manager::adarSetRamBypass(uint8_t deviceIndex, uint8_t broadcast) {
 }

 void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4) per API contract documented in
-    // ADAR1000_AGC.cpp and matching ADI datasheet terminology.
-    // Reject out-of-range early so a stale 0-based caller does not
-    // silently wrap to ((0-1) & 0x03) == 3 and write to CH4.
-    // See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetRxPhase: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
    uint8_t i_val = VM_I[phase % 128];
    uint8_t q_val = VM_Q[phase % 128];

-    // Subtract 1 to convert 1-based channel to 0-based register offset
-    // before masking. See issue #90.
-    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + ((channel - 1) & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + ((channel - 1) & 0x03) * 2;
+    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
+    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;

    adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
    adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -891,16 +880,11 @@ void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 }

 void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetTxPhase: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
    uint8_t i_val = VM_I[phase % 128];
    uint8_t q_val = VM_Q[phase % 128];

-    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + ((channel - 1) & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + ((channel - 1) & 0x03) * 2;
+    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
+    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;

    adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
    adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -908,23 +892,13 @@ void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 }

 void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetRxVgaGain: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
-    uint32_t mem_addr = REG_CH1_RX_GAIN + ((channel - 1) & 0x03);
+    uint32_t mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
    adarWrite(deviceIndex, mem_addr, gain, broadcast);
    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
 }

 void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetTxVgaGain: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
-    uint32_t mem_addr = REG_CH1_TX_GAIN + ((channel - 1) & 0x03);
+    uint32_t mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
    adarWrite(deviceIndex, mem_addr, gain, broadcast);
    adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 }
@@ -32,50 +32,11 @@ localparam COMB_WIDTH = 28;
 // adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
 // on 7-series regardless of speed grade.
 //
-// Active-high reset derived from reset_n (inverted and REGISTERED).
+// Active-high reset derived from reset_n (inverted).
 // CEP (clock enable for P register) gated by data_valid.
-//
-// ----------------------------------------------------------------------------
-// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
-// ----------------------------------------------------------------------------
-// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
-// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
-// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
-// plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
-// Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
-// period. Timing failed by 626 ps on the 400 MHz domain.
-//
-// Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
-// Vivado treats max_fanout on a REG (not a wire) as authoritative and
-// replicates the register into N copies, each placed near its ≈50 loads.
-// Invariants preserved:
-//   I1 (correctness):       reset_h is still active-high, equals ~reset_n
-//                           after one clk edge; CIC reset is a RECEIVER-side
-//                           synchronizer anyway (driven by reset_n_400m which
-//                           is already sync'd in the parent DDC), so adding
-//                           one more clk cycle of latency is safe.
-//   I2 (glitch-free):       Registered output => inherently glitch-free,
-//                           feeding DSP48E1 RST pins (which are synchronous
-//                           to CLK, so they capture on the same edge anyway).
-//   I3 (power-up safety):   reset_h is NOT async-reset itself. On power-up,
-//                           FDRE INIT=0 starts reset_h LOW. First clk edge
-//                           samples ~reset_n which is LOW on power-up (the
-//                           parent DDC holds reset_n_400m low until the 2-
-//                           stage synchronizer releases), so reset_h goes
-//                           HIGH on cycle 1 and all DSPs see reset during
-//                           the following cycles. System is held in reset
-//                           for enough cycles that any initial register
-//                           state garbage is overwritten. ✅
-//   I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
-//                           goes HIGH. Downstream DSPs come out of reset on
-//                           the next clk edge after that. Total latency
-//                           from system reset release to first valid sample:
-//                           2 (sync chain) + 1 (reset_h reg) + 1 (first
-//                           DSP output) = 4 cycles at 400 MHz = 10 ns.
-//                           Negligible vs system reset assertion duration.
-// ----------------------------------------------------------------------------
-(* max_fanout = 50 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
-always @(posedge clk) reset_h <= ~reset_n;
+// ============================================================================
+
+wire reset_h = ~reset_n;  // active-high reset for DSP48E1 RSTP

 // Sign-extended input for integrator_0 C port (48-bit)
 wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -738,11 +699,10 @@ initial begin
 end

 // Decimation control + monitoring (integrators are now DSP48E1 instances)
-// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
-// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
-// DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
+// Sync reset: enables FDRE inference for better timing at 400 MHz.
+// Reset is already synchronous to clk via reset synchronizer in parent module.
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
        integrator_sampled <= 0;
        decimation_counter <= 0;
        data_valid_delayed <= 0;
@@ -795,9 +755,9 @@ always @(posedge clk) begin
 end

 // Pipeline the valid signal for comb section
-// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
+// Sync reset: matches decimation control block reset style.
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
        data_valid_comb <= 0;
        data_valid_comb_pipe <= 0;
        data_valid_comb_0_out <= 0;
@@ -832,7 +792,7 @@ end
 //   - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]

 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
        for (i = 0; i < STAGES; i = i + 1) begin
            comb[i] <= 0;
            for (j = 0; j < COMB_DELAY; j = j + 1) begin
@@ -18,23 +18,8 @@
 #   Bank 35: VCCO = 3.3V (FT2232H USB 2.0 FIFO — 15 signals)
 #
 # DRC Fix History:
-#   - PLIO-9 (REVERTED): Previously moved clk_120m_dac from C13 (N-type) to
-#     D13 (P-type MRCC) to satisfy the MRCC preference. However, a schematic
-#     audit (KiCad netlist export from the Eagle schematic, U42 pad->net map)
-#     revealed that D13 is UNCONNECTED on the physical PCB. The real
-#     /FPGA_DAC_CLOCK net from AD9523 OUT11 lands on C13 (IO_L11N_T1_SRCC_15,
-#     N-type). Moved back to C13 and added CLOCK_DEDICATED_ROUTE FALSE,
-#     matching the ft_clkout treatment on C4 (N-type MRCC).
-#   - Schematic audit added pin constraints for previously-unconstrained
-#     signals connected to the FPGA in hardware: ADC_OR_P/N (M6/N6, AD9484
-#     overflow flag), /FPGA_ADC_CLOCK_P/N (N11/N12, 400 MHz observation tap
-#     of the AD9523->AD9484 sample clock). Added to 50T wrapper as
-#     anchored-but-unused inputs to secure pin assignment and prevent
-#     accidental future contention; full RTL consumers are a follow-up.
-#   - PLIO-9 (original, historical): FT2232H CLKOUT routed to C4
-#     (IO_L12N_T1_MRCC_35, N-type). Clock inputs normally use P-type MRCC
-#     pins, but IBUFG works correctly on N-type. Demote PLIO-9 to warning
-#     in build script.
+#   - PLIO-9: Moved clk_120m_dac from C13 (N-type) to D13 (P-type MRCC).
+#     Clock inputs must use the P-type pin of a Multi-Region Clock-Capable pair.
 #   - BIVC-1 / Place 30-372: Bank 14 must have a single VCCO. LVDS_25 forces
 #     VCCO=2.5V, so adc_pwdn was changed from LVCMOS33 to LVCMOS25 to match.
 #     IBUFDS input buffers are VCCO-independent. BIVC-1 also waived via
@@ -43,6 +28,9 @@
 #   - UCIO/NSTD: Unconstrained ports (FT601 ports inactive with USB_MODE=1,
 #     status/debug outputs have no physical pins). Handled with SEVERITY
 #     demotion + default IOSTANDARD.
+#   - PLIO-9: FT2232H CLKOUT routed to C4 (IO_L12N_T1_MRCC_35, N-type).
+#     Clock inputs normally use P-type MRCC pins, but IBUFG works correctly
+#     on N-type. Demote PLIO-9 to warning in build script.
 # ============================================================================

 # ============================================================================
@@ -78,7 +66,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {clk_100m}]
 create_clock -name clk_100m -period 10.0 [get_ports {clk_100m}]
 set_input_jitter [get_clocks clk_100m] 0.1

-# 120MHz DAC Clock (AD9523 OUT11 → /FPGA_DAC_CLOCK → Bank 15 pin C13)
+# 120MHz DAC Clock (AD9523 OUT11 → FPGA_DAC_CLOCK → Bank 15 MRCC pin D13)
 # NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
 #       AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
 #       uses this clock input for internal DAC data timing only. The RTL port
@@ -86,19 +74,12 @@ set_input_jitter [get_clocks clk_100m] 0.1
 #       physical pin on the 50T board and is left unconnected here. The port
 #       CANNOT be removed from the RTL because the 200T board uses it with
 #       ODDR clock forwarding (pin H17, see xc7a200t_fbg484.xdc).
-#
-# PIN: C13 is IO_L11N_T1_SRCC_15 (N-type SRCC). A prior commit attempted to
-# move this to D13 (MRCC P-type) to satisfy PLIO-9, but the schematic audit
-# showed D13 is UNCONNECTED on the PCB — the /FPGA_DAC_CLOCK net physically
-# lands on C13. Moving to D13 made the DAC clock input float. Restored to
-# C13 and forced CLOCK_DEDICATED_ROUTE FALSE (same mechanism as ft_clkout on
-# C4), which routes the IBUFG output through general fabric to a BUFG.
-set_property PACKAGE_PIN C13 [get_ports {clk_120m_dac}]
+# FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
+#      Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
+set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
 set_property IOSTANDARD LVCMOS33 [get_ports {clk_120m_dac}]
 create_clock -name clk_120m_dac -period 8.333 [get_ports {clk_120m_dac}]
 set_input_jitter [get_clocks clk_120m_dac] 0.1
-# C13 is N-type SRCC (not dedicated-clock-capable); override the DRC check.
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {clk_120m_dac_IBUF}]

 # ADC DCO Clock (400MHz LVDS — AD9523 OUT5 → AD9484 → FPGA, Bank 14 MRCC)
 # NOTE: LVDS_25 is the only valid differential input standard on 7-series HR
@@ -302,45 +283,6 @@ set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
 set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
 set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay

-# --------------------------------------------------------------------------
-# AD9484 Overflow / Out-Of-Range flag (schematic nets ADC_OR_P / ADC_OR_N)
-# --------------------------------------------------------------------------
-# AD9484 differential OR output on FPGA pads M6 (OR_P) / N6 (OR_N), Bank 14.
-# This is the AD9484's full-scale overflow indicator, useful for AGC /
-# gain-ranging feedback. The 50T RTL wrapper anchors this with an IBUFDS
-# (DONT_TOUCH) so the pads cannot be accidentally driven as outputs (which
-# would cause contention with the AD9484 driver). A future PR should wire
-# the buffered signal into the receive-path status flags.
-set_property PACKAGE_PIN M6 [get_ports {adc_or_p}]
-set_property PACKAGE_PIN N6 [get_ports {adc_or_n}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
-set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
-
-# --------------------------------------------------------------------------
-# FPGA observation of AD9523->AD9484 sample clock (/FPGA_ADC_CLOCK_P/N)
-# --------------------------------------------------------------------------
-# AD9523 drives the AD9484 sample clock directly; the same differential
-# pair is tapped to FPGA pads N11 (P) / N12 (N), Bank 14, MRCC-capable.
-# This is an INPUT-ONLY tap (FPGA must never drive these pads — that would
-# contend with the AD9523 driver feeding the ADC). The 50T wrapper anchors
-# with IBUFDS + DONT_TOUCH so the pad assignment is preserved across all
-# synthesis/optimization stages. The buffered net is unconsumed for now;
-# create_clock and clock_groups are deferred until an RTL consumer exists
-# (see commented template below).
-set_property PACKAGE_PIN N11 [get_ports {fpga_adc_clock_p}]
-set_property PACKAGE_PIN N12 [get_ports {fpga_adc_clock_n}]
-set_property IOSTANDARD LVDS_25 [get_ports {fpga_adc_clock_p}]
-set_property IOSTANDARD LVDS_25 [get_ports {fpga_adc_clock_n}]
-set_property DIFF_TERM TRUE [get_ports {fpga_adc_clock_p}]
-# No create_clock here on purpose: the IBUFDS output is unconsumed (anchored
-# via DONT_TOUCH only), so declaring it as a clock would only generate
-# "clock has no registered destinations" warnings. When a follow-up PR adds
-# an actual consumer, add:
-#     create_clock -name fpga_adc_clock -period 2.5 [get_ports {fpga_adc_clock_p}]
-#     set_input_jitter [get_clocks fpga_adc_clock] 0.05
-#     set_clock_groups -asynchronous -group [get_clocks fpga_adc_clock] ...
-
 # ============================================================================
 # FT2232H USB 2.0 INTERFACE (Bank 35, VCCO=3.3V)
 # ============================================================================
@@ -405,49 +347,29 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
 # FPGA Write Path (FPGA drives data, FT2232H samples):
 #   - Data setup before next CLKOUT rising: t_su = 5.0 ns
 #   - Data hold after CLKOUT rising:        t_hd = 0.0 ns
-#   - Board trace skew budget:               ~0.5 ns
-#   - Output delay max = t_su + trace_max = 5.0 + 0.5 = 5.5 ns
-#   - Output delay min = t_hd - trace_min = 0.0 - 0.0 = 0.0 ns
-#
-# NOTE: Historical XDC used 'period - t_su = 11.667 ns' for output_delay -max,
-# which is the wrong interpretation: set_output_delay takes the external setup
-# requirement (+trace), not the remaining timing budget. The old value forced
-# Vivado to close a path assuming FT2232H requires 11.667 ns of setup, which
-# it does not, and caused WNS=-5.350 ns failures on ft_data/ft_rd_n/ft_wr_n/
-# ft_oe_n/ft_siwu paths given the 5.513 ns clock insertion delay on the
-# non-dedicated C4 routing.
+#   - Output delay max = period - t_su = 16.667 - 5.0 = 11.667 ns
+#   - Output delay min = t_hd = 0.0 ns
 # --------------------------------------------------------------------------

 # Input delays: FT2232H → FPGA (data bus and status signals)
-#
-# -min revision (Build N+1): was 0.0 ns, now 1.0 ns.
-# Rationale: set_input_delay -min is the EARLIEST time data can change at the
-# FPGA pin after the launch clock edge, i.e. FT2232H Tco_min + trace_min.
-# Setting -min 0.0 claimed data could change simultaneously with the clock
-# edge, which is pessimistically tight for hold analysis and caused a
-# -0.079 ns hold violation on ft_rxf_n → FSM_sequential_wr_state in Build N
-# (due to 2.895 ns clock insertion delay on non-dedicated C4 routing).
-# FT2232H Sync FIFO Tco is spec'd 1–4 ns; using 1.0 ns is conservative and
-# still covers worst-case silicon. Invariant preserved: hold_margin =
-# Tco_min + trace_min - clk_insertion_delay - Th_fpga ≥ 0.
 set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_data[*]}]
-set_input_delay -clock [get_clocks ft_clkout] -min 1.0   [get_ports {ft_data[*]}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_data[*]}]
 set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_rxf_n}]
-set_input_delay -clock [get_clocks ft_clkout] -min 1.0   [get_ports {ft_rxf_n}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_rxf_n}]
 set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_txe_n}]
-set_input_delay -clock [get_clocks ft_clkout] -min 1.0   [get_ports {ft_txe_n}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_txe_n}]

 # Output delays: FPGA → FT2232H (control strobes and data bus when writing)
-set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_data[*]}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_data[*]}]
-set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_rd_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_rd_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_wr_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_wr_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_oe_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_oe_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 5.5 [get_ports {ft_siwu}]
-set_output_delay -clock [get_clocks ft_clkout] -min 0.0 [get_ports {ft_siwu}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_data[*]}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_data[*]}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_rd_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_rd_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_wr_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_wr_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_oe_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_oe_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_siwu}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_siwu}]

 # ============================================================================
 # STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
@@ -489,42 +411,24 @@ set_false_path -from [get_ports {stm32_mixers_enable}]
 set_false_path -from [get_cells reset_sync_reg[*]] -to [get_pins -filter {REF_PIN_NAME == CLR} -of_objects [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ REGISTER.*.*}]]

 # --------------------------------------------------------------------------
-# Clock Domain Crossing — asynchronous clock groups
-#
-# Rationale: prefer `set_clock_groups -asynchronous` over pairwise
-# `set_false_path -from CLK -to CLK`. The latter is an STA antipattern:
-# it disables *all* paths between the two domains, including the
-# synchronizer paths themselves and any future inadvertent crossings,
-# which can mask real CDC bugs that only show up at temperature/voltage
-# corners. Clock-groups is the idiomatic way to declare domains async
-# while still letting STA flag newly-introduced unrelated paths.
-#
-# Register-level false_paths (e.g. reset_sync_reg above) remain
-# appropriate — those restrict the waiver to specific, audited endpoints.
-#
-# Groups declared here mirror the pairwise false_paths that existed
-# previously; no new pair is declared async.
+# Clock Domain Crossing false paths
 # --------------------------------------------------------------------------

 # clk_100m ↔ adc_dco_p (400 MHz): DDC has internal CDC synchronizers
-set_clock_groups -asynchronous \
-    -group [get_clocks clk_100m] \
-    -group [get_clocks adc_dco_p]
+set_false_path -from [get_clocks clk_100m] -to [get_clocks adc_dco_p]
+set_false_path -from [get_clocks adc_dco_p] -to [get_clocks clk_100m]

 # clk_100m ↔ clk_120m_dac: CDC via synchronizers in radar_system_top
-set_clock_groups -asynchronous \
-    -group [get_clocks clk_100m] \
-    -group [get_clocks clk_120m_dac]
+set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_120m_dac]
+set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_100m]

 # FT2232H CDC: clk_100m ↔ ft_clkout (60 MHz), toggle CDC in RTL
-set_clock_groups -asynchronous \
-    -group [get_clocks clk_100m] \
-    -group [get_clocks ft_clkout]
+set_false_path -from [get_clocks clk_100m] -to [get_clocks ft_clkout]
+set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]

 # FT2232H CDC: clk_120m_dac ↔ ft_clkout (no direct crossing, but belt-and-suspenders)
-set_clock_groups -asynchronous \
-    -group [get_clocks clk_120m_dac] \
-    -group [get_clocks ft_clkout]
+set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
+set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]

 # ============================================================================
 # PHYSICAL CONSTRAINTS
@@ -1,66 +1,106 @@
-`timescale 1ns / 1ps
-
-module ddc_400m_enhanced (
-    input wire clk_400m,           // 400MHz clock from ADC DCO
-    input wire clk_100m,           // 100MHz system clock
-    input wire reset_n,
-    input wire mixers_enable,
-    input wire [7:0] adc_data,     // ADC data at 400MHz
+`timescale 1ns / 1ps
+
+module ddc_400m_enhanced (
+    input wire clk_400m,           // 400MHz clock from ADC DCO
+    input wire clk_100m,           // 100MHz system clock
+    input wire reset_n,
+    input wire mixers_enable,
+    input wire [7:0] adc_data,     // ADC data at 400MHz
    input wire adc_data_valid_i,     // Valid at 400MHz
-	 input wire adc_data_valid_q,
-    output wire signed [17:0] baseband_i,
-    output wire signed [17:0] baseband_q,  
+	 input wire adc_data_valid_q,
+    output wire signed [17:0] baseband_i,
+    output wire signed [17:0] baseband_q,  
    output wire baseband_valid_i,
-	 output wire baseband_valid_q,
-
-    output wire [1:0] ddc_status,
-    // Enhanced interfaces
-    output wire [7:0] ddc_diagnostics,
+	 output wire baseband_valid_q,
+
+    output wire [1:0] ddc_status,
+    // Enhanced interfaces
+    output wire [7:0] ddc_diagnostics,
    output wire mixer_saturation,
    output wire filter_overflow,
 	 
-	 input wire [1:0] test_mode,
-    input wire [15:0] test_phase_inc,
-    input wire force_saturation,
-    input wire reset_monitors,
-    output wire [31:0] debug_sample_count,
-    output wire [17:0] debug_internal_i,
-    output wire [17:0] debug_internal_q
-);
-
-// Parameters for numerical precision
-parameter ADC_WIDTH = 8;
-parameter NCO_WIDTH = 16;
-parameter MIXER_WIDTH = 18;
-parameter OUTPUT_WIDTH = 18;
-
-// IF frequency parameters
-parameter IF_FREQ = 120000000;
-parameter FS = 400000000;
-parameter PHASE_WIDTH = 32;
-
-// Internal signals
-wire signed [15:0] sin_out, cos_out;
-wire nco_ready;
-wire cic_valid;
-wire fir_valid;
-wire [17:0] cic_i_out, cic_q_out;
-wire signed [17:0] fir_i_out, fir_q_out;
-
-
+	 input wire [1:0] test_mode,
+    input wire [15:0] test_phase_inc,
+    input wire force_saturation,
+    input wire reset_monitors,
+    output wire [31:0] debug_sample_count,
+    output wire [17:0] debug_internal_i,
+    output wire [17:0] debug_internal_q
+);
+
+// Parameters for numerical precision
+parameter ADC_WIDTH = 8;
+parameter NCO_WIDTH = 16;
+parameter MIXER_WIDTH = 18;
+parameter OUTPUT_WIDTH = 18;
+
+// IF frequency parameters
+parameter IF_FREQ = 120000000;
+parameter FS = 400000000;
+parameter PHASE_WIDTH = 32;
+
+// Internal signals
+wire signed [15:0] sin_out, cos_out;
+wire nco_ready;
+wire cic_valid;
+wire fir_valid;
+wire [17:0] cic_i_out, cic_q_out;
+wire signed [17:0] fir_i_out, fir_q_out;
+
+
 // Diagnostic registers
 reg [2:0] saturation_count;
 reg overflow_detected;
 reg [7:0] error_counter;

+// ============================================================================
+// 400 MHz Reset Synchronizer
+//
+// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
+// Using it directly as an async reset in the 400 MHz domain causes the reset
+// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
+// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
+// domain, requiring 18.243ns of routing (WNS = -18.081ns).
+//
+// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
+// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
+// path from reset_n to all 400 MHz registers). Reset deassertion is
+// synchronized to clk_400m rising edge, preventing metastability.
+//
+// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
+// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
+// (already synchronized to 100 MHz at radar_system_top level).
+// ============================================================================
+(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
+(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
+
+// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
+(* max_fanout = 50 *) reg reset_400m;
+
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
+        reset_sync_400m <= 2'b00;
+        reset_400m      <= 1'b1;
+    end else begin
+        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
+        reset_400m      <= ~reset_sync_400m[1];
+    end
+end
+
+// CDC synchronization for control signals (2-stage synchronizers)
+(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
+(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
+wire mixers_enable_sync;
+wire force_saturation_sync;
+
 // Debug monitoring signals
 reg [31:0] sample_counter;
 wire signed [17:0] debug_mixed_i_trunc;
 wire signed [17:0] debug_mixed_q_trunc;

 // Real-time status monitoring
-reg [7:0] signal_power_i, signal_power_q;
-
+reg [7:0] signal_power_i, signal_power_q;
+
 // Internal mixing signals
 // Pipeline: NCO fabric reg (1) + DSP48E1 AREG/BREG (1) + MREG (1) + PREG (1) + retiming (1) = 5 cycles
 // The NCO fabric pipeline register was added to break the long NCO→DSP B-port route
@@ -78,112 +118,61 @@ reg [4:0] dsp_valid_pipe;
 // Post-DSP retiming registers — breaks DSP48E1 CLK→P to fabric timing path
 // This extra pipeline stage absorbs the 1.866ns DSP output prop delay + routing,
 // ensuring WNS > 0 at 400 MHz regardless of placement seed
-(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
-
-// Output stage registers
-reg signed [17:0] baseband_i_reg, baseband_q_reg;
-reg baseband_valid_reg;
-
-// ============================================================================
+(* DONT_TOUCH = "TRUE" *) reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_retimed, mult_q_retimed;
+
+// Output stage registers
+reg signed [17:0] baseband_i_reg, baseband_q_reg;
+reg baseband_valid_reg;
+
+// ============================================================================
 // Phase Dithering Signals
 // ============================================================================
 wire [7:0] phase_dither_bits;
-reg [31:0] phase_inc_dithered;
-
+reg [31:0] phase_inc_dithered;
+
+
+
+// ============================================================================
+// Debug Signal Assignments
+// ============================================================================
+assign debug_internal_i = mixed_i[25:8];
+assign debug_internal_q = mixed_q[25:8];
+assign debug_sample_count = sample_counter;
+assign debug_mixed_i_trunc = mixed_i[25:8];
+assign debug_mixed_q_trunc = mixed_q[25:8];
+
+// ============================================================================
+// Clock Domain Crossing for Control Signals (2-stage synchronizers)
 // ============================================================================
-// Debug Signal Assignments
-// ============================================================================
-assign debug_internal_i = mixed_i[25:8];
-assign debug_internal_q = mixed_q[25:8];
-assign debug_sample_count = sample_counter;
-assign debug_mixed_i_trunc = mixed_i[25:8];
-assign debug_mixed_q_trunc = mixed_q[25:8];
-
-// ============================================================================
-// 400 MHz Reset Synchronizer
-//
-// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
-// Using it directly as an async reset in the 400 MHz domain causes the reset
-// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
-// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
-// domain, requiring 18.243ns of routing (WNS = -18.081ns).
-//
-// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
-// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
-// path from reset_n to all 400 MHz registers). Reset deassertion is
-//
-// reset_400m   : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
-//                This is THE signal fed to every synchronous 400 MHz FDRE
-//                and every DSP48E1 RST pin in this module and its children
-//                (NCO, CIC, LFSR). Vivado replicates the register (~14
-//                copies) so each replica drives ≈50 loads regionally,
-//                eliminating the single-LUT1 / 702-load net that caused
-//                WNS=-0.626 ns in Build N.
-//
-// System-level invariants preserved:
-//   I1  Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
-//       (2 sync + 1 replicated-reg fanout).  At 400 MHz = 7.5 ns << any
-//       system-level reset assertion duration.
-//   I2  Reset de-assertion is always synchronous to clk_400m (via
-//       reset_sync_400m), never glitches.
-//   I3  DSP48E1 RST pins are all fed from Q of a register — glitch-free.
-//   I4  No new CDC introduced: reset_400m is entirely in clk_400m domain.
-//   I5  Power-up: reset_n is asserted externally and mmcm_locked is low;
-//       reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
-//       FDREs stay cleared. Safe.
-// ============================================================================
-(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
-(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
-
-// Active-high replicated reset for all synchronous 400 MHz consumers
-(* max_fanout = 50 *) reg reset_400m = 1'b1;
-
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
-        reset_sync_400m <= 2'b00;
-        reset_400m      <= 1'b1;
-    end else begin
-        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
-        reset_400m      <= ~reset_sync_400m[1];
-    end
-end
-
-// CDC synchronization for control signals (2-stage synchronizers)
-(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
-(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
-wire mixers_enable_sync;
-wire force_saturation_sync;
 assign mixers_enable_sync = mixers_enable_sync_chain[1];
 assign force_saturation_sync = force_saturation_sync_chain[1];

-// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
-// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mixers_enable_sync_chain <= 2'b00;
        force_saturation_sync_chain <= 2'b00;
    end else begin
        mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
        force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
    end
-end
-
-// ============================================================================
-// Sample Counter and Debug Monitoring
-// ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_400m || reset_monitors) begin
+end
+
+// ============================================================================
+// Sample Counter and Debug Monitoring
+// ============================================================================
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m || reset_monitors) begin
        sample_counter <= 0;
-        error_counter <= 0;
-    end else if (adc_data_valid_i && adc_data_valid_q ) begin
-        sample_counter <= sample_counter + 1;
-    end
-end
-
-
-// ============================================================================
-// Enhanced Phase Dithering Instance
-// ============================================================================
+        error_counter <= 0;
+    end else if (adc_data_valid_i && adc_data_valid_q ) begin
+        sample_counter <= sample_counter + 1;
+    end
+end
+
+
+// ============================================================================
+// Enhanced Phase Dithering Instance
+// ============================================================================
 lfsr_dither_enhanced #(
    .DITHER_WIDTH(8)
 ) phase_dither_gen (
@@ -191,36 +180,36 @@ lfsr_dither_enhanced #(
    .reset_n(reset_n_400m),
    .enable(nco_ready),
    .dither_out(phase_dither_bits)
-);
-
-// ============================================================================
-// Phase Increment Calculation with Dithering
-// ============================================================================
-// Calculate phase increment for 120MHz IF at 400MHz sampling
-localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
-
+);
+
+// ============================================================================
+// Phase Increment Calculation with Dithering
+// ============================================================================
+// Calculate phase increment for 120MHz IF at 400MHz sampling
+localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
+
 // Apply dithering to reduce spurious tones (registered for 400 MHz timing)
-always @(posedge clk_400m) begin
-    if (reset_400m)
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m)
        phase_inc_dithered <= PHASE_INC_120MHZ;
    else
        phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
-end
-
-// ============================================================================
-// Enhanced NCO with Diagnostics
-// ============================================================================
+end
+
+// ============================================================================
+// Enhanced NCO with Diagnostics
+// ============================================================================
 nco_400m_enhanced nco_core (
    .clk_400m(clk_400m),
-    .reset_n(reset_n_400m),
-    .frequency_tuning_word(phase_inc_dithered),
-    .phase_valid(mixers_enable),
-    .phase_offset(16'h0000),
-    .sin_out(sin_out),
-    .cos_out(cos_out),
-    .dds_ready(nco_ready)
-);
-
+    .reset_n(reset_n_400m),
+    .frequency_tuning_word(phase_inc_dithered),
+    .phase_valid(mixers_enable),
+    .phase_offset(16'h0000),
+    .sin_out(sin_out),
+    .cos_out(cos_out),
+    .dds_ready(nco_ready)
+);
+
 // ============================================================================
 // Enhanced Mixing Stage — DSP48E1 direct instantiation for 400 MHz timing
 //
@@ -240,8 +229,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
                      {1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;

 // Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        dsp_valid_pipe <= 5'b00000;
    end else begin
        dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -257,8 +246,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal;  // Mod
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg;            // Models PREG

 // Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        cos_nco_pipe <= 0;
        sin_nco_pipe <= 0;
    end else begin
@@ -268,8 +257,8 @@ always @(posedge clk_400m) begin
 end

 // Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        adc_signed_reg <= 0;
        cos_pipe_reg <= 0;
        sin_pipe_reg <= 0;
@@ -281,8 +270,8 @@ always @(posedge clk_400m) begin
 end

 // Stage 2: MREG equivalent
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mult_i_internal <= 0;
        mult_q_internal <= 0;
    end else begin
@@ -292,8 +281,8 @@ always @(posedge clk_400m) begin
 end

 // Stage 3: PREG equivalent
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mult_i_reg <= 0;
        mult_q_reg <= 0;
    end else begin
@@ -303,8 +292,8 @@ always @(posedge clk_400m) begin
 end

 // Stage 4: Post-DSP retiming register (matches synthesis path)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mult_i_retimed <= 0;
        mult_q_retimed <= 0;
    end else begin
@@ -322,8 +311,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
 // (1.505ns routing observed in Build 26). These fabric registers are placed
 // near the DSP by the placer, splitting the route into two shorter segments.
 // DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        cos_nco_pipe <= 0;
        sin_nco_pipe <= 0;
    end else begin
@@ -340,10 +329,11 @@ DSP48E1 #(
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_SIMD("ONE48"),
+    // Pipeline register attributes — all enabled for max timing
    .AREG(1),
    .BREG(1),
    .MREG(1),
-    .PREG(1),
+    .PREG(1),           // P register enabled — absorbs CLK→P delay for timing closure
    .ADREG(0),
    .ACASCREG(1),
    .BCASCREG(1),
@@ -354,6 +344,7 @@ DSP48E1 #(
    .DREG(0),
    .INMODEREG(0),
    .OPMODEREG(0),
+    // Pattern detector (unused)
    .AUTORESET_PATDET("NO_RESET"),
    .MASK(48'h3fffffffffff),
    .PATTERN(48'h000000000000),
@@ -505,8 +496,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
 // Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
 // Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
 // the 2.500ns clock period at slow process corner
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mult_i_retimed <= 0;
        mult_q_retimed <= 0;
    end else begin
@@ -522,8 +513,8 @@ end
 // force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
 // polluting the critical input path with extra logic
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mixed_i <= 0;
        mixed_q <= 0;
        mixed_valid <= 0;
@@ -565,31 +556,31 @@ always @(posedge clk_400m) begin
        mixer_overflow_q <= 0;
        overflow_detected <= 1'b0;
    end
-end
-
-// ============================================================================
-// Enhanced CIC Decimators
-// ============================================================================
-wire cic_valid_i, cic_valid_q;
-
+end
+
+// ============================================================================
+// Enhanced CIC Decimators
+// ============================================================================
+wire cic_valid_i, cic_valid_q;
+
 cic_decimator_4x_enhanced cic_i_inst (
    .clk(clk_400m),
-    .reset_n(reset_n_400m),
-    .data_in(mixed_i[33:16]),
-    .data_valid(mixed_valid),
-    .data_out(cic_i_out),
-    .data_out_valid(cic_valid_i)
-);
-
+    .reset_n(reset_n_400m),
+    .data_in(mixed_i[33:16]),
+    .data_valid(mixed_valid),
+    .data_out(cic_i_out),
+    .data_out_valid(cic_valid_i)
+);
+
 cic_decimator_4x_enhanced cic_q_inst (
    .clk(clk_400m),
-    .reset_n(reset_n_400m),
-    .data_in(mixed_q[33:16]),
-    .data_valid(mixed_valid),
-    .data_out(cic_q_out),
-    .data_out_valid(cic_valid_q)
-);
-
+    .reset_n(reset_n_400m),
+    .data_in(mixed_q[33:16]),
+    .data_valid(mixed_valid),
+    .data_out(cic_q_out),
+    .data_out_valid(cic_valid_q)
+);
+
 assign cic_valid = cic_valid_i & cic_valid_q;

 // ============================================================================
@@ -602,96 +593,96 @@ wire fir_valid_i, fir_valid_q;
 wire fir_i_ready, fir_q_ready;
 wire [17:0] fir_d_in_i, fir_d_in_q; 

-cdc_adc_to_processing #(
-    .WIDTH(18),
-    .STAGES(3)
+cdc_adc_to_processing #(
+    .WIDTH(18),
+    .STAGES(3)
 )CDC_FIR_i(
    .src_clk(clk_400m),
    .dst_clk(clk_100m),
    .src_reset_n(reset_n_400m),
-    .dst_reset_n(reset_n),
-    .src_data(cic_i_out),
-    .src_valid(cic_valid_i),
-    .dst_data(fir_d_in_i),
-    .dst_valid(fir_in_valid_i)
+    .dst_reset_n(reset_n),
+    .src_data(cic_i_out),
+    .src_valid(cic_valid_i),
+    .dst_data(fir_d_in_i),
+    .dst_valid(fir_in_valid_i)
 );

-cdc_adc_to_processing #(
-    .WIDTH(18),
-    .STAGES(3)
+cdc_adc_to_processing #(
+    .WIDTH(18),
+    .STAGES(3)
 )CDC_FIR_q(
    .src_clk(clk_400m),
    .dst_clk(clk_100m),
    .src_reset_n(reset_n_400m),
-    .dst_reset_n(reset_n),
-    .src_data(cic_q_out),
-    .src_valid(cic_valid_q),
-    .dst_data(fir_d_in_q),
-    .dst_valid(fir_in_valid_q)
-);
-
+    .dst_reset_n(reset_n),
+    .src_data(cic_q_out),
+    .src_valid(cic_valid_q),
+    .dst_data(fir_d_in_q),
+    .dst_valid(fir_in_valid_q)
+);
+
 // ============================================================================
 // FIR Filter Instances
 // ============================================================================

-// FIR I channel
-fir_lowpass_parallel_enhanced fir_i_inst (
-    .clk(clk_100m),
-    .reset_n(reset_n),
-    .data_in(fir_d_in_i),  // Use synchronized data
-    .data_valid(fir_in_valid_i),  // Use synchronized valid
-    .data_out(fir_i_out),
-    .data_out_valid(fir_valid_i),
-    .fir_ready(fir_i_ready),
-    .filter_overflow()
-);
-
-// FIR Q channel  
-fir_lowpass_parallel_enhanced fir_q_inst (
-    .clk(clk_100m),
-    .reset_n(reset_n),
-    .data_in(fir_d_in_q),  // Use synchronized data
-    .data_valid(fir_in_valid_q),  // Use synchronized valid
-    .data_out(fir_q_out),
-    .data_out_valid(fir_valid_q),
-    .fir_ready(fir_q_ready),
-    .filter_overflow()
-);
-
-assign fir_valid = fir_valid_i & fir_valid_q;
-
-// ============================================================================
-// Enhanced Output Stage
-// ============================================================================
-always @(posedge clk_100m or negedge reset_n) begin
-    if (!reset_n) begin
-        baseband_i_reg <= 0;
-        baseband_q_reg <= 0;
-        baseband_valid_reg <= 0;
-    end else if (fir_valid) begin
-        baseband_i_reg <= fir_i_out;
-        baseband_q_reg <= fir_q_out;
-        baseband_valid_reg <= 1;
-    end else begin
-        baseband_valid_reg <= 0;
-    end
-end
-
-
-// ============================================================================
-// Output Assignments
-// ============================================================================
-assign baseband_i = baseband_i_reg;
-assign baseband_q = baseband_q_reg;
+// FIR I channel
+fir_lowpass_parallel_enhanced fir_i_inst (
+    .clk(clk_100m),
+    .reset_n(reset_n),
+    .data_in(fir_d_in_i),  // Use synchronized data
+    .data_valid(fir_in_valid_i),  // Use synchronized valid
+    .data_out(fir_i_out),
+    .data_out_valid(fir_valid_i),
+    .fir_ready(fir_i_ready),
+    .filter_overflow()
+);
+
+// FIR Q channel  
+fir_lowpass_parallel_enhanced fir_q_inst (
+    .clk(clk_100m),
+    .reset_n(reset_n),
+    .data_in(fir_d_in_q),  // Use synchronized data
+    .data_valid(fir_in_valid_q),  // Use synchronized valid
+    .data_out(fir_q_out),
+    .data_out_valid(fir_valid_q),
+    .fir_ready(fir_q_ready),
+    .filter_overflow()
+);
+
+assign fir_valid = fir_valid_i & fir_valid_q;
+
+// ============================================================================
+// Enhanced Output Stage
+// ============================================================================
+always @(posedge clk_100m or negedge reset_n) begin
+    if (!reset_n) begin
+        baseband_i_reg <= 0;
+        baseband_q_reg <= 0;
+        baseband_valid_reg <= 0;
+    end else if (fir_valid) begin
+        baseband_i_reg <= fir_i_out;
+        baseband_q_reg <= fir_q_out;
+        baseband_valid_reg <= 1;
+    end else begin
+        baseband_valid_reg <= 0;
+    end
+end
+
+
+// ============================================================================
+// Output Assignments
+// ============================================================================
+assign baseband_i = baseband_i_reg;
+assign baseband_q = baseband_q_reg;
 assign baseband_valid_i = baseband_valid_reg;
-assign baseband_valid_q = baseband_valid_reg;
-assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
-assign mixer_saturation = overflow_detected;
-assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
-
-// ============================================================================
-// Enhanced Debug and Monitoring
-// ============================================================================
+assign baseband_valid_q = baseband_valid_reg;
+assign ddc_status = {mixer_overflow_i | mixer_overflow_q, nco_ready};
+assign mixer_saturation = overflow_detected;
+assign ddc_diagnostics = {saturation_count, error_counter[4:0]};
+
+// ============================================================================
+// Enhanced Debug and Monitoring
+// ============================================================================
 reg [31:0] debug_cic_count, debug_fir_count, debug_bb_count;

 `ifdef SIMULATION
@@ -708,10 +699,10 @@ always @(posedge clk_100m) begin
                 baseband_i, baseband_q, debug_bb_count);
    end
 end
-`endif
-
-// In ddc_400m.v, add these debug signals:
-
+`endif
+
+// In ddc_400m.v, add these debug signals:
+
 // Debug monitoring (simulation only)
 `ifdef SIMULATION
 reg [31:0] debug_adc_count = 0;
@@ -732,67 +723,58 @@ always @(posedge clk_100m) begin
                 baseband_i, baseband_q, debug_baseband_count, $time);
    end
 end
-`endif
-
-
-endmodule
-
-// ============================================================================
-// Enhanced Phase Dithering Module
-// ============================================================================
-`timescale 1ns / 1ps
-
-module lfsr_dither_enhanced #(
-    parameter DITHER_WIDTH = 8  // Increased for better dithering
-)(
-    input wire clk,
-    input wire reset_n,
-    input wire enable,
-    output wire [DITHER_WIDTH-1:0] dither_out
-);
-
-reg [DITHER_WIDTH-1:0] lfsr_reg;
-reg [15:0] cycle_counter;
-reg lock_detected;
-
-// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
-wire feedback;
-
-generate
-    if (DITHER_WIDTH == 4) begin
-        assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
-    end else if (DITHER_WIDTH == 8) begin
-        assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
-    end else begin
-        assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
-    end
-endgenerate
-
-// ============================================================================
-// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
-// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
-// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
-// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
-// ============================================================================
-(* max_fanout = 50 *) reg reset_h = 1'b1;
-always @(posedge clk) reset_h <= ~reset_n;
-
-always @(posedge clk) begin
-    if (reset_h) begin
-        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
-        cycle_counter <= 0;
-        lock_detected <= 0;
-    end else if (enable) begin
-        lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
-        cycle_counter <= cycle_counter + 1;
-        
-        // Detect LFSR lock after sufficient cycles
-        if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
-            lock_detected <= 1'b1;
-        end
-    end
-end
-
-assign dither_out = lfsr_reg;
-
-endmodule
+`endif
+
+
+endmodule
+
+// ============================================================================
+// Enhanced Phase Dithering Module
+// ============================================================================
+`timescale 1ns / 1ps
+
+module lfsr_dither_enhanced #(
+    parameter DITHER_WIDTH = 8  // Increased for better dithering
+)(
+    input wire clk,
+    input wire reset_n,
+    input wire enable,
+    output wire [DITHER_WIDTH-1:0] dither_out
+);
+
+reg [DITHER_WIDTH-1:0] lfsr_reg;
+reg [15:0] cycle_counter;
+reg lock_detected;
+
+// Polynomial for better randomness: x^8 + x^6 + x^5 + x^4 + 1
+wire feedback;
+
+generate
+    if (DITHER_WIDTH == 4) begin
+        assign feedback = lfsr_reg[3] ^ lfsr_reg[2];
+    end else if (DITHER_WIDTH == 8) begin
+        assign feedback = lfsr_reg[7] ^ lfsr_reg[5] ^ lfsr_reg[4] ^ lfsr_reg[3];
+    end else begin
+        assign feedback = lfsr_reg[DITHER_WIDTH-1] ^ lfsr_reg[DITHER_WIDTH-2];
+    end
+endgenerate
+
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n) begin
+        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
+        cycle_counter <= 0;
+        lock_detected <= 0;
+    end else if (enable) begin
+        lfsr_reg <= {lfsr_reg[DITHER_WIDTH-2:0], feedback};
+        cycle_counter <= cycle_counter + 1;
+        
+        // Detect LFSR lock after sufficient cycles
+        if (cycle_counter > (2**DITHER_WIDTH * 8)) begin
+            lock_detected <= 1'b1;
+        end
+    end
+end
+
+assign dither_out = lfsr_reg;
+
+endmodule
@@ -59,25 +59,6 @@ reg [1:0] quadrant_reg2;                 // Pass-through for Stage 5 MUX
 // Valid pipeline: tracks 6-stage latency
 reg [5:0] valid_pipe;

-// ============================================================================
-// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
-// ============================================================================
-// reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
-// Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
-// regionally, avoiding the single-LUT1 / 702-load net that caused timing
-// failure in Build N. It feeds:
-//   - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
-//   - All pipeline-stage fabric FDREs (synchronous reset)
-// Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
-//   I1 correctness:      reset_h == ~reset_n one cycle later
-//   I2 glitch-free:      registered output
-//   I3 power-up safe:    INIT=1'b1 holds all downstream in reset until first
-//                        valid clock edge; reset_n is low on power-up anyway
-//   I4 de-assert lat.:   +1 cycle vs. direct async; negligible at 400 MHz
-// ============================================================================
-(* max_fanout = 50 *) reg reset_h = 1'b1;
-always @(posedge clk_400m) reset_h <= ~reset_n;
-
 // Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
 wire [7:0] lut_address = phase_with_offset[31:24];

@@ -154,8 +135,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
 // Stage 2: phase_with_offset adds phase offset
 reg [31:0] phase_accumulator;

-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        phase_accumulator <= 32'h00000000;
        phase_accum_reg   <= 32'h00000000;
        phase_with_offset <= 32'h00000000;
@@ -209,8 +190,8 @@ DSP48E1 #(
    .RSTA(1'b0),
    .RSTB(1'b0),
    .RSTM(1'b0),
-    .RSTP(reset_h),              // Reset P register (phase accumulator) — registered, max_fanout=50
-    .RSTC(reset_h),              // Reset C register (tuning word)       — registered, max_fanout=50
+    .RSTP(!reset_n),             // Reset P register (phase accumulator) on !reset_n
+    .RSTC(!reset_n),             // Reset C register (tuning word) on !reset_n
    .RSTALLCARRYIN(1'b0),
    .RSTALUMODE(1'b0),
    .RSTCTRL(1'b0),
@@ -264,8 +245,8 @@ DSP48E1 #(
 // Stage 1: Capture DSP48E1 P output into fabric register
 // Stage 2: Add phase offset to captured value
 // Split into two registered stages to break DSP48E1.P→CARRY4 critical path
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        phase_accum_reg   <= 32'h00000000;
        phase_with_offset <= 32'h00000000;
    end else if (phase_valid) begin
@@ -283,8 +264,8 @@ end
 //           Only 2 registers driven (lut_index_pipe + quadrant_pipe)
 //           Minimal fanout → short routes → easy timing
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        lut_index_pipe_sin <= 6'b000000;
        lut_index_pipe_cos <= 6'b000000;
        quadrant_pipe      <= 2'b00;
@@ -300,8 +281,8 @@ end
 //           Registered address → combinational LUT6 read → register
 //           Only 1 logic level (LUT6), trivial timing
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        sin_abs_reg <= 16'h0000;
        cos_abs_reg <= 16'h7FFF;
        quadrant_reg <= 2'b00;
@@ -317,8 +298,8 @@ end
 //          CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
 //          Also pass through abs values and quadrant for Stage 5
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        sin_neg_reg <= 16'h0000;
        cos_neg_reg <= -16'h7FFF;
        sin_abs_reg2 <= 16'h0000;
@@ -337,8 +318,8 @@ end
 // Stage 5: Quadrant sign application → final sin/cos output
 //          Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        sin_out <= 16'h0000;
        cos_out <= 16'h7FFF;
    end else if (valid_pipe[4]) begin
@@ -366,8 +347,8 @@ end
 // ============================================================================
 // Valid pipeline and dds_ready (6-stage latency)
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        valid_pipe <= 6'b000000;
        dds_ready <= 1'b0;
    end else begin
@@ -62,20 +62,6 @@ module radar_system_top_50t (
    input wire adc_dco_n,
    output wire adc_pwdn,

-    // ----- AD9484 overflow flag (differential) -----
-    // Schematic pads M6 (OR_P) / N6 (OR_N). Anchored-only for now; a future
-    // PR will wire this into the receive-path status flags for AGC feedback.
-    input wire adc_or_p,
-    input wire adc_or_n,
-
-    // ----- Tap of AD9523 -> AD9484 sample clock (differential) -----
-    // Schematic pads N11 (P) / N12 (N). Must remain input-only — driving
-    // these pads as outputs would contend with the AD9523 driver feeding
-    // the ADC. Anchored with an IBUFDS (DONT_TOUCH) below; buffered net is
-    // unconsumed pending a follow-up PR.
-    input wire fpga_adc_clock_p,
-    input wire fpga_adc_clock_n,
-
    // ===== STM32 Control (Bank 15: 3.3V) =====
    input wire stm32_new_chirp,
    input wire stm32_new_elevation,
@@ -98,38 +84,6 @@ module radar_system_top_50t (
    output wire gpio_dig7             // DIG_7 (H12→PD15): reserved
 );

-    // =====================================================================
-    // Anchored-but-unused schematic inputs (secured via IBUFDS + DONT_TOUCH)
-    // =====================================================================
-    // Without these buffer instantiations, synthesis would remove the
-    // orphan input ports (UCIO / NSTD warnings) and the XDC pin constraints
-    // would fail to bind. DONT_TOUCH forces Vivado to retain the buffer
-    // primitives and their package-pin connections across all optimization
-    // stages. The buffered nets are intentionally left unconsumed here;
-    // they will be wired into the RTL in a follow-up PR once the ADC
-    // status-flag and sample-clock-tap features are implemented.
-    (* DONT_TOUCH = "TRUE" *) wire adc_or_buf;
-    (* DONT_TOUCH = "TRUE" *) IBUFDS #(
-        .DIFF_TERM   ("TRUE"),
-        .IBUF_LOW_PWR("FALSE"),
-        .IOSTANDARD  ("LVDS_25")
-    ) u_ibufds_adc_or (
-        .O  (adc_or_buf),
-        .I  (adc_or_p),
-        .IB (adc_or_n)
-    );
-
-    (* DONT_TOUCH = "TRUE" *) wire fpga_adc_clock_buf;
-    (* DONT_TOUCH = "TRUE" *) IBUFDS #(
-        .DIFF_TERM   ("TRUE"),
-        .IBUF_LOW_PWR("FALSE"),
-        .IOSTANDARD  ("LVDS_25")
-    ) u_ibufds_fpga_adc_clk (
-        .O  (fpga_adc_clock_buf),
-        .I  (fpga_adc_clock_p),
-        .IB (fpga_adc_clock_n)
-    );
-
    // ===== Tie-off wires for unconstrained FT601 inputs (inactive with USB_MODE=1) =====
    wire        ft601_txe_tied    = 1'b0;
    wire        ft601_rxf_tied    = 1'b0;
@@ -26,14 +26,12 @@ layers agree (because both could be wrong).

 from __future__ import annotations

-import ast
 import os
 import re
 import struct
 import subprocess
 import tempfile
 from pathlib import Path
-from typing import ClassVar

 import pytest

@@ -627,420 +625,6 @@ class TestTier1AgcCrossLayerInvariant:
        )


-# ===================================================================
-# ADAR1000 channel→register round-trip invariant (issue #90)
-# ===================================================================
-#
-# Ground-truth invariant crossing three system layers:
-#   Chip (datasheet) -> Driver (MCU helpers) -> Application (callers).
-#
-# For every logical element ch in {0,1,2,3} (hardware channels CH1..CH4),
-# the round-trip
-#     caller_expr(ch) --> helper_offset(channel) * stride --> base + off
-# must land on the physical register REG_CH{ch+1}_* defined in the ADI
-# ADAR1000 register map parsed from ADAR1000_Manager.h.
-#
-# Catches:
-#   * #90 channel rotation regardless of which side is fixed (caller OR helper).
-#   * Wrong stride (e.g. phase written with stride 1 instead of 2).
-#   * Bad mask (e.g. `channel & 0x07`, `channel & 0x01`).
-#   * Wrong base register in a helper.
-#   * New setter added with mismatched convention.
-#   * Caller moved to a file the test no longer scans (fails loudly).
-#
-# Cannot be defeated by:
-#   * Renaming/refactoring helper layout: the setter coverage test
-#     (`test_helper_sites_exist_for_all_setters`) catches missing parse.
-#   * Changing 0x03 to 3 or adding a named constant: the offset is
-#     evaluated symbolically via AST, not matched by regex.
-
-
-def _parse_adar_register_map(header_text):
-    """Extract `#define REG_CHn_(RX|TX)_(GAIN|PHS_I|PHS_Q)` values."""
-    regs = {}
-    for m in re.finditer(
-        r"^#define\s+(REG_CH[1-4]_(?:RX|TX)_(?:GAIN|PHS_I|PHS_Q))\s+(0x[0-9A-Fa-f]+)",
-        header_text,
-        re.MULTILINE,
-    ):
-        regs[m.group(1)] = int(m.group(2), 16)
-    return regs
-
-
-def _safe_eval_int_expr(expr, **variables):
-    """
-    Evaluate a small integer expression with +, -, *, &, |, ^, ~, <<, >>.
-    Python's & / | / ^ / ~ / << / >> have the same semantics as C for the
-    operand widths we care about here (uint8_t after the mask makes the
-    result fit in 0..3). No floating point, no function calls, no names
-    outside ``variables``.
-
-    SECURITY: ``expr`` MUST come from a trusted source -- specifically,
-    C/C++ source text under version control in this repository (e.g.
-    arguments parsed out of ``main.cpp``/``ADAR1000_AGC.cpp``).  Although
-    the AST whitelist below rejects function calls, attribute access,
-    subscripts, and any name not in ``variables``, ``eval`` is still
-    invoked on the compiled tree.  Do NOT pass user-supplied / network /
-    GUI input here.
-    """
-    tree = ast.parse(expr, mode="eval")
-    allowed = (
-        ast.Expression, ast.BinOp, ast.UnaryOp, ast.Constant,
-        ast.Name, ast.Load,
-        ast.Add, ast.Sub, ast.Mult, ast.Mod, ast.FloorDiv,
-        ast.BitAnd, ast.BitOr, ast.BitXor,
-        ast.USub, ast.UAdd, ast.Invert,
-        ast.LShift, ast.RShift,
-    )
-    for node in ast.walk(tree):
-        if not isinstance(node, allowed):
-            raise ValueError(
-                f"disallowed AST node {type(node).__name__!s} in `{expr}`"
-            )
-    return eval(
-        compile(tree, "<expr>", "eval"),
-        {"__builtins__": {}},
-        variables,
-    )
-
-
-def _extract_adar_helper_sites(manager_cpp, setter_names):
-    """
-    For each setter, locate the body of ``void ADAR1000Manager::<setter>``
-    and return a list of (setter, base_register, offset_expr_c, stride)
-    for every ``REG_CHn_XXX + <expr>`` memory-address assignment.
-    """
-    sites = []
-    for setter in setter_names:
-        m = re.search(
-            rf"void\s+ADAR1000Manager::{setter}\s*\([^)]*\)\s*\{{(.+?)^\}}",
-            manager_cpp,
-            re.MULTILINE | re.DOTALL,
-        )
-        if not m:
-            continue
-        body = m.group(1)
-        for access in re.finditer(
-            r"=\s*(REG_CH[1-4]_(?:RX|TX)_(?:GAIN|PHS_I|PHS_Q))\s*\+\s*([^;]+);",
-            body,
-        ):
-            base = access.group(1)
-            rhs = access.group(2).strip()
-            # Trailing `* <integer>` = stride multiplier (2 for phase I/Q).
-            stride_match = re.match(r"(.+?)\s*\*\s*(\d+)\s*$", rhs)
-            if stride_match:
-                offset_expr = stride_match.group(1).strip()
-                stride = int(stride_match.group(2))
-            else:
-                offset_expr = rhs
-                stride = 1
-            sites.append((setter, base, offset_expr, stride))
-    return sites
-
-
-# Method-definition line pattern: `[qualifier...] <ret-type> <Class>::<setter>(`
-# Covers: plain `void X::f(`, `inline void X::f(`, `static bool X::f(`, etc.
-_DEFN_RE = re.compile(
-    r"^\s*(?:inline\s+|static\s+|virtual\s+|constexpr\s+|explicit\s+)*"
-    r"(?:void|bool|uint\w+|int\w*|auto)\s+\S+::\w+\s*\("
-)
-
-
-def _extract_adar_caller_sites(sources, setter):
-    """
-    Find every call ``<obj>.<setter>(dev, <channel_expr>, ...)`` across
-    ``sources = [(filename, text), ...]``. Returns (filename, line_no,
-    channel_expr) for each. Skips function declarations/definitions.
-
-    Arg list up to matching `)`: restricted to a single line. All existing
-    call sites fit on one line; a future multi-line refactor would drop
-    callers from the scan, which the round-trip test surfaces loudly via
-    `assert callers` (rather than silently missing a site).
-    """
-    out = []
-    call_re = re.compile(rf"\b{setter}\s*\(([^;]*?)\)\s*;")
-    for filename, text in sources:
-        for line_no, line in enumerate(text.splitlines(), start=1):
-            # Skip method definition / declaration lines.
-            if _DEFN_RE.match(line):
-                continue
-            cm = call_re.search(line)
-            if not cm:
-                continue
-            args = _split_top_level_commas(cm.group(1))
-            if len(args) < 2:
-                continue
-            channel_expr = args[1].strip()
-            out.append((filename, line_no, channel_expr))
-    return out
-
-
-def _split_top_level_commas(text):
-    """Split on commas that sit at paren-depth 0 (ignores nested calls)."""
-    parts, depth, cur = [], 0, []
-    for ch in text:
-        if ch == "(":
-            depth += 1
-            cur.append(ch)
-        elif ch == ")":
-            depth -= 1
-            cur.append(ch)
-        elif ch == "," and depth == 0:
-            parts.append("".join(cur))
-            cur = []
-        else:
-            cur.append(ch)
-    if cur:
-        parts.append("".join(cur))
-    return parts
-
-
-class TestTier1Adar1000ChannelRegisterRoundTrip:
-    """
-    Cross-layer round-trip: caller channel expr -> helper offset formula
-    -> physical register address must equal REG_CH{ch+1}_* for every
-    caller and every ch in {0,1,2,3}.
-
-    See module-level block comment above and upstream issue #90.
-    """
-
-    _SETTERS = (
-        "adarSetRxPhase",
-        "adarSetTxPhase",
-        "adarSetRxVgaGain",
-        "adarSetTxVgaGain",
-    )
-
-    # Register base -> stride override. Parsed values of stride are
-    # trusted; this table is the independent ground truth for cross-check.
-    _EXPECTED_STRIDE: ClassVar[dict[str, int]] = {
-        "REG_CH1_RX_GAIN": 1,
-        "REG_CH1_TX_GAIN": 1,
-        "REG_CH1_RX_PHS_I": 2,
-        "REG_CH1_RX_PHS_Q": 2,
-        "REG_CH1_TX_PHS_I": 2,
-        "REG_CH1_TX_PHS_Q": 2,
-    }
-
-    @classmethod
-    def setup_class(cls):
-        cls.header_txt = (cp.MCU_LIB_DIR / "ADAR1000_Manager.h").read_text()
-        cls.manager_txt = (cp.MCU_LIB_DIR / "ADAR1000_Manager.cpp").read_text()
-        cls.reg_map = _parse_adar_register_map(cls.header_txt)
-        cls.helper_sites = _extract_adar_helper_sites(
-            cls.manager_txt, cls._SETTERS,
-        )
-        # Auto-discover every C++ TU under the MCU tree so a new caller
-        # added to e.g. a future ``ADAR1000_Calibration.cpp`` cannot
-        # silently escape the round-trip check (issue #90 reviewer note).
-        # Exclude any path containing a ``tests`` segment so this test
-        # does not parse its own fixtures.  The resulting list is
-        # deterministic (sorted) for reproducible parametrization.
-        scanned = []
-        seen = set()
-        for root in (cp.MCU_LIB_DIR, cp.MCU_CODE_DIR):
-            for path in sorted(root.rglob("*.cpp")):
-                if "tests" in path.parts:
-                    continue
-                if path in seen:
-                    continue
-                seen.add(path)
-                scanned.append((path.name, path.read_text()))
-        cls.sources = scanned
-        # Sanity: the two TUs known to call ADAR1000 setters at the time
-        # of issue #90 must be in scope.  If a future refactor renames or
-        # moves them this assert fires loudly rather than silently
-        # passing an empty round-trip.
-        scanned_names = {n for (n, _) in scanned}
-        for required in ("ADAR1000_AGC.cpp", "main.cpp", "ADAR1000_Manager.cpp"):
-            assert required in scanned_names, (
-                f"Auto-discovery missed `{required}`; check MCU_LIB_DIR / "
-                f"MCU_CODE_DIR roots in contract_parser.py."
-            )
-
-    # ---------- Tier A: chip ground truth ----------------------------
-
-    def test_register_map_gain_stride_is_one_per_channel(self):
-        """Datasheet invariant: RX/TX VGA gain registers are 1 byte apart."""
-        for kind in ("RX_GAIN", "TX_GAIN"):
-            for n in range(1, 4):
-                delta = (
-                    self.reg_map[f"REG_CH{n+1}_{kind}"]
-                    - self.reg_map[f"REG_CH{n}_{kind}"]
-                )
-                assert delta == 1, (
-                    f"ADAR1000 register map invariant broken: "
-                    f"REG_CH{n+1}_{kind} - REG_CH{n}_{kind} = {delta}, "
-                    f"datasheet says 1. Either the header was mis-edited "
-                    f"or ADI released a part with a different map."
-                )
-
-    def test_register_map_phase_stride_is_two_per_channel(self):
-        """Datasheet invariant: phase I/Q pairs occupy 2 bytes per channel."""
-        for kind in ("RX_PHS_I", "RX_PHS_Q", "TX_PHS_I", "TX_PHS_Q"):
-            for n in range(1, 4):
-                delta = (
-                    self.reg_map[f"REG_CH{n+1}_{kind}"]
-                    - self.reg_map[f"REG_CH{n}_{kind}"]
-                )
-                assert delta == 2, (
-                    f"ADAR1000 register map invariant broken: "
-                    f"REG_CH{n+1}_{kind} - REG_CH{n}_{kind} = {delta}, "
-                    f"datasheet says 2."
-                )
-
-    # ---------- Tier B: driver parses cleanly -------------------------
-
-    def test_helper_sites_exist_for_all_setters(self):
-        """Every channel-indexed setter must parse at least one register access."""
-        found = {s for (s, _, _, _) in self.helper_sites}
-        missing = set(self._SETTERS) - found
-        assert not missing, (
-            f"Helper parse failed for: {sorted(missing)}. "
-            f"Either a setter was renamed (update _SETTERS), moved out of "
-            f"ADAR1000_Manager.cpp (extend scan scope), or the register-"
-            f"access form changed beyond `REG_CHn_XXX + <expr>`. "
-            f"DO NOT weaken this test without reviewing issue #90."
-        )
-
-    def test_helper_parsed_stride_matches_datasheet(self):
-        """Parsed helper strides must match the datasheet register spacing."""
-        for setter, base, offset_expr, stride in self.helper_sites:
-            expected = self._EXPECTED_STRIDE.get(base)
-            assert expected is not None, (
-                f"{setter} writes to unrecognised base `{base}`. "
-                f"If ADI added a new channel-indexed register block, "
-                f"extend _EXPECTED_STRIDE with its datasheet stride."
-            )
-            assert stride == expected, (
-                f"{setter} helper uses stride {stride} for `{base}` "
-                f"(`{offset_expr} * {stride}`), datasheet says {expected}. "
-                f"Writes will overlap or skip channels."
-            )
-
-    # ---------- Tier C: round-trip to physical register ---------------
-
-    def test_all_callers_pass_one_based_channel(self):
-        """
-        INVARIANT: every caller's channel argument must, for ch in
-        {0,1,2,3}, evaluate to a 1-based ADI channel index in {1,2,3,4}.
-
-        The bug fixed in #90 was that helpers used ``channel & 0x03``
-        directly, so a caller passing bare ``ch`` (0..3) appeared to
-        work for ch=0..2 and silently aliased ch=3 onto CH4-then-CH1.
-        After the fix, helpers do ``(channel - 1) & 0x03`` and reject
-        ``channel < 1 || channel > 4``.  A future caller written as
-        ``adarSetRxPhase(dev, ch, ...)`` (bare 0-based) or
-        ``adarSetRxPhase(dev, 0, ...)`` (literal 0) would silently be
-        dropped by the bounds-check at runtime; this test catches it at
-        CI time instead.
-
-        The check intentionally lives one tier above the round-trip test
-        so the failure message points the reader at the API contract
-        (1-based per ADI datasheet & ADAR1000_AGC.cpp:76) rather than at
-        a register-arithmetic mismatch.
-        """
-        offenders = []
-        for setter in self._SETTERS:
-            callers = _extract_adar_caller_sites(self.sources, setter)
-            for filename, line_no, ch_expr in callers:
-                for ch in range(4):
-                    try:
-                        channel_val = _safe_eval_int_expr(ch_expr, ch=ch)
-                    except (NameError, KeyError, ValueError) as e:
-                        offenders.append(
-                            f"  - {filename}:{line_no} {setter}("
-                            f"…, `{ch_expr}`, …) -- ch={ch}: "
-                            f"unparseable ({e})"
-                        )
-                        continue
-                    if channel_val not in (1, 2, 3, 4):
-                        offenders.append(
-                            f"  - {filename}:{line_no} {setter}("
-                            f"…, `{ch_expr}`, …) -- ch={ch}: "
-                            f"channel={channel_val}, expected 1..4"
-                        )
-        assert not offenders, (
-            "ADAR1000 1-based channel API contract violated. The fix "
-            "for issue #90 requires every caller to pass channel in "
-            "{1,2,3,4} (CH1..CH4 per ADI datasheet). Bare 0-based ch "
-            "or a literal 0 will be silently dropped by the helper's "
-            "bounds check.  Offenders:\n" + "\n".join(offenders)
-        )
-
-    @pytest.mark.parametrize(
-        "setter",
-        [
-            "adarSetRxPhase",
-            "adarSetTxPhase",
-            "adarSetRxVgaGain",
-            "adarSetTxVgaGain",
-        ],
-    )
-    def test_round_trip_lands_on_intended_physical_channel(self, setter):
-        """
-        INVARIANT: for every caller of ``<setter>`` and every logical ch
-        in {0,1,2,3}, the effective register address equals
-        REG_CH{ch+1}_*. Catches #90 regardless of fix direction.
-        """
-        callers = _extract_adar_caller_sites(self.sources, setter)
-        assert callers, (
-            f"No callers of `{setter}` found. Either the test scope is "
-            f"incomplete (extend `setup_class.sources`) or the symbol was "
-            f"inlined/removed. A blind test is a dangerous test — "
-            f"investigate before weakening."
-        )
-        helpers = [
-            (b, e, s) for (nm, b, e, s) in self.helper_sites if nm == setter
-        ]
-        assert helpers, f"helper body for `{setter}` not parseable"
-
-        errors = []
-        for filename, line_no, ch_expr in callers:
-            for ch in range(4):
-                try:
-                    channel_val = _safe_eval_int_expr(ch_expr, ch=ch)
-                except (NameError, KeyError, ValueError) as e:
-                    pytest.fail(
-                        f"{filename}:{line_no}: caller channel expression "
-                        f"`{ch_expr}` uses symbol outside {{ch}} or a "
-                        f"disallowed operator ({e}). Extend "
-                        f"_safe_eval_int_expr variables or rewrite the "
-                        f"call site with a supported expression."
-                    )
-                for base_sym, offset_expr, stride in helpers:
-                    try:
-                        offset = _safe_eval_int_expr(
-                            offset_expr, channel=channel_val,
-                        )
-                    except (NameError, KeyError, ValueError) as e:
-                        pytest.fail(
-                            f"helper `{setter}` offset expr "
-                            f"`{offset_expr}` uses symbol outside "
-                            f"{{channel}} or a disallowed operator ({e}). "
-                            f"Extend _safe_eval_int_expr variables if new "
-                            f"driver state is introduced."
-                        )
-                    final = self.reg_map[base_sym] + offset * stride
-                    expected_sym = base_sym.replace("CH1", f"CH{ch + 1}")
-                    expected = self.reg_map[expected_sym]
-                    if final != expected:
-                        errors.append(
-                            f"  - {filename}:{line_no} {setter} "
-                            f"caller `{ch_expr}` | ch={ch} -> "
-                            f"channel={channel_val} -> "
-                            f"`{base_sym} + ({offset_expr})"
-                            f"{' * ' + str(stride) if stride != 1 else ''}`"
-                            f" = 0x{final:03X} "
-                            f"(expected {expected_sym} = 0x{expected:03X})"
-                        )
-        assert not errors, (
-            f"ADAR1000 channel round-trip FAILED for {setter} "
-            f"({len(errors)} mismatches) — writes routed to wrong physical "
-            f"channel. This is issue #90.\n" + "\n".join(errors)
-        )
-
-
 class TestTier1DataPacketLayout:
    """Verify data packet byte layout matches between Python and Verilog."""

@@ -7,7 +7,6 @@
 [![Frequency: 10.5GHz](https://img.shields.io/badge/Frequency-10.5GHz-blue)](https://github.com/NawfalMotii79/PLFM_RADAR)
 [![PRs Welcome](https://img.shields.io/badge/PRs-welcome-brightgreen.svg)](https://github.com/NawfalMotii79/PLFM_RADAR/pulls)

-![AERIS-10 Radar System](https://raw.githubusercontent.com/NawfalMotii79/PLFM_RADAR/main/8_Utils/3fb1dabf-2c6d-4b5d-b471-48bc461ce914.jpg)

 AERIS-10 is an open-source, low-cost 10.5 GHz phased array radar system featuring Pulse Linear Frequency Modulated (LFM) modulation. Available in two versions (3km and 20km range), it's designed for researchers, drone developers, and serious SDR enthusiasts who want to explore and experiment with phased array radar technology.

@@ -47,7 +46,7 @@ The AERIS-10 main sub-systems are:

 - **Main Board** containing:
  - **DAC** - Generates the RADAR Chirps
-  - **2x Microwave Mixers (LT5552)** - For up-conversion and IF-down-conversion
+  - **2x Microwave Mixers (LTC5552)** - For up-conversion and IF-down-conversion
  - **4x 4-Channel Phase Shifters (ADAR1000)** - For RX and TX chain beamforming
  - **16x Front End Chips (ADTR1107)** - Used for both Low Noise Amplifying (RX) and Power Amplifying (TX) stages
  - **XC7A50T FPGA** - Handles RADAR Signal Processing on the upstream FTG256 board:
@@ -92,7 +91,7 @@ The AERIS-10 main sub-systems are:
 ### Processing Pipeline

 1. **Waveform Generation** - DAC creates LFM chirps
-2. **Up/Down Conversion** - LT5552 mixers handle frequency translation
+2. **Up/Down Conversion** - LTC5552 mixers handle frequency translation
 3. **Beam Steering** - ADAR1000 phase shifters control 16 elements
 4. **Signal Processing (FPGA)**:
   - Raw ADC data capture
Author	SHA1	Message	Date
NawfalMotii79	8bd880ce4c	Added BOM and Gerbers AERIS-10 CI / MCU Firmware Tests (push) Successful in 55s Details AERIS-10 CI / Cross-Layer Contract Tests (push) Has been cancelled Details AERIS-10 CI / FPGA Regression (push) Has been cancelled Details AERIS-10 CI / Python Lint + Tests (push) Has been cancelled Details BOM and Gerbers, ready to be sent to PCB manufacturer	2026-04-22 01:04:28 +01:00
NawfalMotii79	33d21da7f2	Remove radar system image from README Removed the AERIS-10 Radar System image from the README.	2026-04-20 19:04:08 +01:00
NawfalMotii79	18901be04a	Fix image link and update mixer model in README Updated image link and corrected mixer model in specifications.	2026-04-19 19:06:44 +01:00
NawfalMotii79	9f899b96e9	Add files via upload	2026-04-19 19:04:48 +01:00
NawfalMotii79	88ca1910ec	Merge pull request #109 from NawfalMotii79/develop Release: merge develop into main	2026-04-19 01:27:15 +01:00