Added BOM and Gerbers

BOM and Gerbers, ready to be sent to PCB manufacturer
2026-04-22 01:04:28 +01:00
81 changed files with 967800 additions and 856197 deletions
@@ -0,0 +1,105 @@
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+"1";"56R";"R-EU_R0201";"R0201";"R22";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"R";"";"";
+"3";"5R";"RR0201";"R0201";"R132, R150, R152";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
+"2";"7.8pF";"CC0201";"C0201";"C61, C62";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"C";"";"";
+"1";"830R";"R-EU_R0402";"R0402";"R36";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"R";"";"";
+"4";"840R";"RR0201";"R0201";"R78, R79, R80, R81";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"NONE";"R";"";"";
+"2";"AD8352ACPZ-R7";"AD8352ACPZ-R7";"CP_16_3_ADI";"U4, U8";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/ad8352.pdf";"2 GHz Ultralow Distortion Differential RF/IF Amplifier";"";"Analog Devices Inc";"AD8352ACPZ-R7";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"AD9484BCPZ-500";"AD9484BCPZ-500";"CP_56_5_ADI";"U1";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/AD9484.pdf";"8-Bit, 500 MSPS, 1.8 V Analog-to-Digital Converter";"";"Analog Devices Inc";"AD9484BCPZ-500";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"AD9708AR";"AD9708AR";"RW_28_ADI";"U3";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"AD9708AR";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"ADAR1000ACCZN";"ADAR1000ACCZN";"CC-88-1_ADI";"ADAR1_, ADAR2_, ADAR3_, ADAR4_";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"ADAR1000ACCZN";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"RF";"";
+"3";"ADS7830IPWR";"ADS7830IPWR";"PW16";"U10, U88, U89";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/ads7830";"8-Bit, 8-Channel Sampling A/D Converter with I2C Interface 16-TSSOP -40 to 85";"";"Texas Instruments";"ADS7830IPWR";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"16";"ADTR1107ACCZ";"ADTR1107ACCZ";"CC-24-8_ADI";"ADTR1107_1, ADTR1107_2, ADTR1107_3, ADTR1107_4, ADTR1107_5, ADTR1107_6, ADTR1107_7, ADTR1107_8, ADTR1107_9, ADTR1107_10, ADTR1107_11, ADTR1107_12, ADTR1107_13, ADTR1107_14, ADTR1107_15, ADTR1107_16";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"ADTR1107ACCZ";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"RF";"";
+"1";"AT93C46A-10SQ-2.7";"AT93C46A-10SQ-2.7";"SOIC8";"IC1";"Three-wire Automotive Temperature Serial EEPROM 1K (64 x 16)";"";"";"";"";"";"";"";"";"";"";"";"";"";"AT93C46DN-SH-B";"1455086";"58M3879";"";"0";"";"";"";"";"";"";"";"";
+"5";"BLM15HB121SN1";"BLM15HB121SN1";"0402";"L5, L6, L7, L19, L20";"EMIFIL (R) Chip Ferrite Bead for GHz Noise";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"";"";"";"";"";"";"";
+"2";"BPF2";"BPF2";"BPF2";"U$2, U$3";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"Blue";"LED-BLUE0603";"LED-0603";"D2, D3, D4, D5";"Blue SMD LED";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"DIO-08575";"";"";"";"";"";"Blue";
+"2";"CJT-T-P-HH-ST-TH1";"CJT-T-P-HH-ST-TH1";"CJTTPHHSTTH1";"J19, J21";"Conn Twinax F 0Hz to 4GHz 100Ohm Solder ST Thru-Hole Gold";"";"";"";"";"Conn Twinax F 0Hz to 4GHz 100Ohm Solder ST Thru-Hole Gold";"7.31mm";"SAMTEC";"CJT-T-P-HH-ST-TH1";"";"";"200-CJTTPHHSTTH1";"https://www.mouser.co.uk/ProductDetail/Samtec/CJT-T-P-HH-ST-TH1?qs=PB6%2FjmICvI3dfW8RDpxn0g%3D%3D";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"DAC5578SRGET";"DAC5578SRGET";"RGE24_2P7X2P7";"U7, U69";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/dac5578";"8-bit, Octal Channel, Ultra-Low Glitch, Voltage Output, 2-Wire Interface DAC 24-VQFN -40 to 125";"";"Texas Instruments";"DAC5578SRGET";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"ECS-120-10-36B2-JTN-TR";"CRYSTAL-12MHZ";"CRYSTAL-SMD-2X2.5MM";"Y1";"12.0MHz Crystal";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"XTAL-15540";"";"";"";"";"";"";
+"1";"EP4RKU+";"EP4RKU+";"DG1677-2_MNC";"U16";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"EP4RKU+";"";"Mini Circuits";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"FT2232HQ";"FT2232HQ";"64QFN_FT2232HQ_FTD";"U6";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"";"";"FT2232HQ";"";"FTDI, Future Technology Devices International Ltd";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"16";"INA241A3IDGKRDGK0008A-MFG";"INA241A3IDGKRDGK0008A-MFG";"DGK0008A-MFG";"U11, U73, U74, U75, U76, U77, U78, U79, U80, U81, U82, U83, U84, U85, U86, U87";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"-5-V to 110-V bidirectional ultraprecise current sense amplifier with enhanced PWM rejection 8-VSSOP -40 to 125";"";"Texas Instruments";"INA241A3IDGKR";"";"";"";"";"";"";"";"";"";"";"";"";"RefDes";"";"";"";"TYPE";"";
+"2";"LTC5552IUDBTRMPBF";"LTC5552IUDBTRMPBF";"UDB_12_ADI";"U5, U13";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"LTC5552IUDB#TRMPBF";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"17";"M3SWA2-34DR+";"M3SWA2-34DR+";"16_QFN";"RF_SW_1, RF_SW_2, RF_SW_3, RF_SW_4, RF_SW_5, RF_SW_6, RF_SW_7, RF_SW_8, RF_SW_9, RF_SW_10, RF_SW_11, RF_SW_12, RF_SW_13, RF_SW_14, RF_SW_15, RF_SW_16, U$1";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"MINI-USB-32005-201";"MINI-USB-32005-201";"32005-201";"X2, X53";"MINI USB-B Conector";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"";"5";"";"";"";"";"";"";"";"";
+"1";"MOMENTARY-SWITCH-SPST-SMD-4.6X2.8MM";"MOMENTARY-SWITCH-SPST-SMD-4.6X2.8MM";"TACTILE_SWITCH_SMD_4.6X2.8MM";"S1";"Momentary Switch (Pushbutton) - SPST";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"SWCH-15606";"";"";"";"";"";"";
+"1";"MT25QL01GBBB8E12-0AUT";"MT25QL01GBBB8E12-0AUT";"BGA24_MT25QL_MRN";"U9";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"MT25QL01GBBB8E12-0AUT";"";"Micron";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"NX3215SA-32.768KHz";"NX3225GD-8MHZ-STD-CRA-3";"XTAL_NX3225GD-8MHZ-STD-CRA-3_N";"XTAL3";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"NX3225GD-8MHZ-STD-CRA-3";"";"NDK";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"NX3225GD-8MHZ-STD-CRA-3";"NX3225GD-8MHZ-STD-CRA-3";"XTAL_NX3225GD-8MHZ-STD-CRA-3_N";"XTAL1";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"NX3225GD-8MHZ-STD-CRA-3";"";"NDK";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"4";"OPA4703EA/250";"OPA4703EA/250";"PW14";"OPA_1, OPA_2, OPA_3, OPA_4";"";"";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/opa4703";"Quad, 12-V, 1-MHz, low-offset operational amplifier 14-TSSOP -40 to 85";"";"Texas Instruments";"OPA4703EA/250";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"STM32F746ZGT7";"STM32F746ZGT7";"LQFP-144_STM";"U2";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"STM32F746ZGT7";"";"STMicroelectronics";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"34";"SZMMSZ5232BT1G";"SZMMSZ5232BT1G";"SOD-123_ONS";"U14, U15, U17, U37, U38, U39, U40, U41, U43, U44, U45, U46, U47, U48, U49, U50, U51, U52, U53, U54, U55, U56, U57, U58, U59, U60, U61, U62, U63, U64, U65, U66, U67, U68";"";"";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"SZMMSZ5232BT1G";"";"onsemi";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"1";"XC7A50T-2FTG256I";"XC7A50T-2FTG256I";"BGA256C100P16X16_1700X1700X155";"U42";"Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA  Check availability";"In Stock";"https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=eda";"";"";"                                                      Artix-7 Field Programmable Gate Array (FPGA) IC 170 2764800 52160 256-LBGA                                              ";"";"";"";"Xilinx Inc.";"";"";"";"XC7A50T-2FTG256I";"";"";"";"LBGA-256 Xilinx Inc.";"";"None";"";"";"https://www.snapeda.com/parts/XC7A50T-2FTG256I/Xilinx/view-part/?ref=snap";"";"";"";"";
@@ -1,8 +1,8 @@
 Generated by EAGLE CAM Processor 7.4.0

-Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.dri
+Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.dri

- Date              : 06/04/2026 22:10
+ Date              : 19/04/2026 23:21
 Drills            : generated
 Device            : Excellon drill station, coordinate format 2.5 inch

@@ -27,8 +27,8 @@ Drills used:

 Code  Size       used

- T01   0.0059inch  1609
- T02   0.0079inch  1892
+ T01   0.0059inch  1604
+ T02   0.0079inch  2243
 T03   0.0100inch    18
 T04   0.0118inch   355
 T05   0.0138inch   113
@@ -43,8 +43,8 @@ Drills used:
 T14   0.0472inch     4
 T15   0.1260inch     8

-Total number of drills: 4438
+Total number of drills: 4784

 Plotfiles:

- C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.drd
+ C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.drd
@@ -1,9 +1,9 @@
 Generated by EAGLE CAM Processor 7.4.0

-Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.gpi
+Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.gpi

- Date              : 06/04/2026 22:41
- Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Test/RADAR_Main_Board.bsk
+ Date              : 19/04/2026 23:50
+ Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/MainBoard_Prod_V2/RADAR_Main_Board.bsk
 Apertures         : generated: 
 Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch

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 D32*
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-X0063008Y0045291D03*
 X0054150Y0061630D03*
 X0051787Y0061630D03*
 X0048441Y0061630D03*
@@ -4153,40 +4189,29 @@ X0030724Y0041157D03*
 X0033283Y0041157D03*
 X0035646Y0041157D03*
 X0038205Y0041157D03*
-X0063992Y0079937D03*
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-X0069307Y0082693D03*
-X0066551Y0079937D03*
-X0074228Y0088402D03*
 D16*
-X0076000Y0051197D03*
-X0079937Y0051197D03*
-X0083874Y0051197D03*
-X0087811Y0051197D03*
-X0091748Y0051197D03*
-X0095685Y0051197D03*
-X0095685Y0044685D03*
-X0091748Y0045276D03*
-X0087811Y0045276D03*
-X0083874Y0045276D03*
-X0079937Y0045276D03*
-X0076000Y0045276D03*
-X0054150Y0045079D03*
-X0050213Y0045079D03*
-X0046276Y0045079D03*
-X0042339Y0045079D03*
 X0038402Y0045079D03*
-X0034465Y0045079D03*
-X0034465Y0051000D03*
-X0038402Y0051000D03*
-X0042339Y0051000D03*
-X0046276Y0051000D03*
-X0050213Y0051000D03*
+X0042339Y0045079D03*
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 X0054150Y0051000D03*
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+X0087811Y0051197D03*
+X0083874Y0051197D03*
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 M02*
@@ -33,60 +33,30 @@ X56315Y57299
 X56315Y54937
 X56315Y52772
 X56315Y50606
-X57102Y45291
-X57102Y43126
-X57102Y40961
-X57102Y38992
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 X73835Y50606
 X73835Y52772
 X73835Y55134
@@ -113,19 +83,62 @@ X71276Y85449
 X69307Y82693
 X66551Y79937
 X74228Y88402
+X59428Y48446
+X59071Y45291
+X61039Y45291
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+X61039Y40961
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+X66945Y38992
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+X59071Y35055
+X57102Y35055
+X57102Y37024
+X57102Y38992
+X57102Y40961
+X57102Y43126
+X57102Y45291
 T02
-X76000Y51197
-X79937Y51197
-X83874Y51197
-X87811Y51197
-X91748Y51197
-X95685Y51197
-X95685Y44685
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-X87811Y45276
-X83874Y45276
-X79937Y45276
-X76000Y45276
 X54150Y45079
 X50213Y45079
 X46276Y45079
@@ -138,24 +151,25 @@ X42339Y51000
 X46276Y51000
 X50213Y51000
 X54150Y51000
+X76000Y51197
+X79937Y51197
+X83874Y51197
+X87811Y51197
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+X95685Y44685
+X91748Y45276
+X87811Y45276
+X83874Y45276
+X79937Y45276
+X76000Y45276
 T03
-X50409Y39386
-X49819Y33874
-X50409Y26787
-X55724Y29150
-X59661Y25409
-X63992Y30331
-X66748Y24819
-X70094Y30134
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 X82299Y27969
 X84661Y24622
 X85252Y31118
-X80921Y33283
-X78756Y38205
-X80724Y41354
 X91551Y31709
 X91945Y27181
 X97063Y28756
@@ -317,6 +331,17 @@ X8087Y52969
 X40567Y25016
 X43520Y28756
 X42929Y31709
+X49819Y33874
+X50409Y39386
+X55724Y29150
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 X110055Y25016
 X110646Y29346
 X110449Y32299
@@ -2,14 +2,14 @@ Generated by EAGLE CAM Processor 7.4.0

 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.dri

- Date              : 05/04/2026 00:08
+ Date              : 19/04/2026 01:42
 Drills            : generated
 Device            : Excellon drill station, coordinate format 2.5 inch

 Parameter settings:

- Tolerance Drill + :  2.50 %
- Tolerance Drill - :  2.50 %
+ Tolerance Drill + :  0.00 %
+ Tolerance Drill - :  0.00 %
 Rotate            : no
 Mirror            : no
 Optimize          : yes
@@ -27,7 +27,7 @@ Drills used:

 Code  Size       used

- T01   0.0059inch   103
+ T01   0.0059inch   128
 T02   0.0079inch    24
 T03   0.0138inch   215
 T04   0.0394inch     5
@@ -35,7 +35,7 @@ Drills used:
 T06   0.0520inch     2
 T07   0.1260inch     7

-Total number of drills: 364
+Total number of drills: 389

 Plotfiles:

@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0

 Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.gpi

- Date              : 05/04/2026 00:07
+ Date              : 19/04/2026 01:42
 Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerAmplifierBoard/RF_PA.fab
 Apertures         : generated: 
 Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
@@ -0,0 +1,10 @@
+G75*
+%MOIN*%
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+%AMOC8*
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@@ -0,0 +1,10 @@
+G75*
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@@ -0,0 +1,29 @@
+"Qty";"Value";"Device";"Package";"Parts";"Description";"COPYRIGHT";"DATASHEET";"DESCRIPTION";"HEIGHT";"MANUFACTURER_NAME";"MANUFACTURER_PART_NUMBER";"MF";"MFR_NAME";"MOUSER_PART_NUMBER";"MOUSER_PRICE-STOCK";"MPN";"OC_FARNELL";"OC_NEWARK";"POPULARITY";"REFDES";"SPICEPREFIX";"TYPE";
+"1";"";"AK300/2";"AK300/2";"X1";"CONNECTOR";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"16";"";"";"";
+"1";"";"MA10-2";"MA10-2";"SV1";"PIN HEADER";"";"";"";"";"";"";"";"";"";"";"";"unknown";"unknown";"3";"";"";"";
+"21";"0.1µF";"C-EUC0805";"C0805";"C1, C6, C12, C18, C29, C30, C36, C42, C54, C60, C66, C71, C76, C77, C83, C89, C109, C119, C129, C144, C154";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"27";"10k";"R-EU_M0805";"M0805";"R2, R4, R6, R8, R10, R12, R14, R16, R18, R20, R22, R24, R26, R28, R30, R32, R34, R36, R38, R40, R42, R44, R46, R48, R50, R52, R56";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"4";"10nF";"C-EUC0603";"C0603";"C150, C152, C160, C162";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"4";"10µF";"C-EUC0603";"C0603";"C151, C153, C161, C163";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"60";"10µF";"C-EUC0805";"C0805";"C4, C5, C9, C10, C15, C16, C21, C22, C24, C25, C28, C33, C34, C39, C40, C45, C46, C50, C51, C52, C53, C57, C58, C63, C64, C69, C70, C74, C75, C80, C81, C86, C87, C92, C93, C94, C95, C108, C112, C113, C114, C115, C118, C122, C123, C124, C125, C128, C132, C133, C134, C135, C138, C139, C140, C143, C147, C148, C157, C158";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"2";"11.5k";"R-EU_M0805";"M0805";"R54, R58";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"4";"12k";"R-EU_M0805";"M0805";"R9, R35, R43, R47";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"13.7k";"R-EU_M0805";"M0805";"R3";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"12";"1µF";"C-EUC0805";"C0805";"C26, C27, C106, C107, C116, C117, C126, C127, C136, C137, C141, C142";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"88";"";"C";"";
+"2";"2.2µH";"POWER_INDUCTOR";"IND_VLP8040T-1R0N_TDK";"U$1, U$2";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"35";"22-23-2021";"22-23-2021";"22-23-2021";"X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, X32, X33, X34, X35, X36";".100" (2.54mm) Center Header - 2 Pin";"";"";"";"";"";"";"MOLEX";"";"";"";"22-23-2021";"1462926";"25C3832";"40";"";"";"";
+"52";"22µF";"C-EUC0603";"C0603";"C2, C3, C7, C8, C11, C13, C14, C17, C19, C20, C23, C31, C32, C35, C37, C38, C41, C43, C44, C47, C48, C49, C55, C56, C59, C61, C62, C65, C67, C68, C72, C73, C78, C79, C82, C84, C85, C88, C90, C91, C110, C111, C120, C121, C130, C131, C145, C146, C149, C155, C156, C159";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"73";"";"C";"";
+"1";"23.4k";"R-EU_M0805";"M0805";"R49";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"2k";"R-EU_M0805";"M0805";"R39";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"3.09k";"R-EU_M0805";"M0805";"R1";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"19";"3.3µH";"POWER_INDUCTOR";"IND_VLP8040T-1R0N_TDK";"U$3, U$4, U$5, U$6, U$7, U$8, U$9, U$10, U$11, U$12, U$13, U$14, U$15, U$16, U$17, U$18, U$19, U$20, U$21";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"6";"32.2k";"R-EU_M0805";"M0805";"R5, R7, R11, R13, R15, R19";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"34.8k";"R-EU_M0805";"M0805";"R21";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"2";"35.7k";"R-EU_M0805";"M0805";"R53, R57";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"11";"56.2k";"R-EU_M0805";"M0805";"R17, R23, R25, R27, R29, R31, R37, R41, R45, R51, R55";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"1";"61.9k";"R-EU_M0805";"M0805";"R33";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"";"45";"";"R";"";
+"6";"ADM7151ACPZ-04-R7";"ADM7151ACPZ-04-R7";"CP_8_11_ADI";"U5, U23, U25, U27, U29, U30";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.analog.com/media/en/technical-documentation/data-sheets/ADM7151.pdf";"800 mA Ultralow Noise, High PSRR, RF Linear Regulator";"";"Analog Devices Inc";"ADM7151ACPZ-04-R7";"";"";"";"";"";"";"";"";"";"";"";
+"5";"LM2662MX/NOPB";"LM2662MX/NOPB";"M08A";"U18, U19, U20, U21, U22";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"";"LM2662MX/NOPB";"";"Texas Instruments";"";"";"";"";"";"";"";"";"LM2662M";
+"10";"T521W476M020ATE045";"T521W476M020ATE045";"T521W";"C96, C97, C98, C99, C100, C101, C102, C103, C104, C105";"T521, Tantalum, Polymer Tantalum, Commercial Grade, 47 uF, 20%, 20 VDC, 105C, -55C, 105C, SMD, Polymer, Molded, Low Profile/ESR, NonCombustible, 2,000 Hrs, 9 % , 45 mOhms, 94 uA, 222.95 mg, 7343, 1.4mm, Height Max = 1.5mm, 1000, 52  Weeks";"";"";"T521, Tantalum, Polymer Tantalum, Commercial Grade, 47 uF, 20%, 20 VDC, 105C, -55C, 105C, SMD, Polymer, Molded, Low Profile/ESR, NonCombustible, 2,000 Hrs, 9 % , 45 mOhms, 94 uA, 222.95 mg, 7343, 1.4mm, Height Max = 1.5mm, 1000, 52  Weeks";"1.5mm";"KEMET";"T521W476M020ATE045";"";"";"80-T521W476M20ATE045";"https://www.mouser.co.uk/ProductDetail/KEMET/T521W476M020ATE045?qs=Ad%252Bh9aq9FyVtchBw1jwoFA%3D%3D";"";"";"";"";"";"";"";
+"21";"TPS562208DDCT";"TPS562208DDCT";"DDC0006A_N";"U1, U2, U3, U4, U6, U7, U8, U9, U10, U11, U12, U13, U14, U15, U16, U17, U24, U26, U28, U31, U33";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/tps562208";"4.5 V to 17 V input, 2 A output, synchronous step-down converter in FCCM mode 6-SOT-23-THIN -40 to 125";"";"Texas Instruments";"TPS562208DDCT";"";"";"";"";"";"";"";"";"RefDes";"";"TYPE";
+"2";"TPS7A8300RGRR";"TPS7A8300RGRR";"RGR20_2P05X2P05_TEX";"U32, U34";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"https://www.ti.com/lit/gpn/tps7a8300";"2-A, low-VIN, low-2-A, low-VIN, low-noise, ultra-low-dropout voltage regulator with power good wi 20-VQFN -40 to 125";"";"Texas Instruments";"TPS7A8300RGRR";"";"";"";"";"";"";"";"";"";"";"";
@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0

 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.dri

- Date              : 04/04/2026 22:46
+ Date              : 19/04/2026 19:18
 Drills            : generated
 Device            : Excellon drill station, coordinate format 2.5 inch

@@ -0,0 +1,36 @@
+Generated by EAGLE CAM Processor 7.4.0
+
+Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.gpi
+
+ Date              : 19/04/2026 19:21
+ Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/PowerBoard/PowerBoard.bsp
+ Apertures         : generated: 
+ Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
+
+Parameter settings:
+
+ Emulate Apertures : no
+ Tolerance Draw  + :  0.00 %
+ Tolerance Draw  - :  0.00 %
+ Tolerance Flash + :  0.00 %
+ Tolerance Flash - :  0.00 %
+ Rotate            : no
+ Mirror            : no
+ Optimize          : yes
+ Auto fit          : yes
+ OffsetX           : 0inch
+ OffsetY           : 0inch
+
+Plotfile Info:
+
+ Coordinate Format : 2.5
+ Coordinate Units  : Inch
+ Data Mode         : Absolute
+ Zero Suppression  : None
+ End Of Block      : *
+
+Apertures used:
+
+ Code     Shape     Size                  used
+
+
@@ -1288,13 +1288,6 @@ X0061780Y0026543D03*
 X0033236Y0247016D03*
 D44*
 X0102724Y0243571D03*
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 X0102823Y0255579D03*
 X0102528Y0264437D03*
 X0102528Y0273197D03*
@@ -1313,6 +1306,11 @@ X0139535Y0349378D03*
 X0139142Y0363551D03*
 X0086386Y0388748D03*
 X0065913Y0348197D03*
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 X0213551Y0178118D03*
 X0223000Y0177921D03*
 X0223197Y0167882D03*
@@ -134,8 +134,10 @@ X0045441Y0113945D03*
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 X0023000Y0133906D03*
 X0100854Y0226740D03*
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 X0102724Y0243571D03*
 X0102823Y0255579D03*
 X0102528Y0264437D03*
@@ -182,14 +184,10 @@ X0294063Y0355677D03*
 X0348787Y0374969D03*
 X0374181Y0345717D03*
 X0374181Y0335717D03*
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 X0057921Y0382843D03*
 X0047921Y0382843D03*
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 D15*
 X0005717Y0400126D02*
 X0005717Y0009654D01*
@@ -136,8 +136,10 @@ X0045441Y0113945D03*
 X0023000Y0123906D03*
 X0023000Y0133906D03*
 X0100854Y0226740D03*
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@@ -184,96 +186,48 @@ X0294063Y0355677D03*
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 X0199575Y0200756D03*
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@@ -291,55 +245,54 @@ X0191110Y0144260D03*
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 X0200756Y0161189D03*
 X0186780Y0173787D03*
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@@ -366,12 +319,24 @@ X0250953Y0209811D03*
 X0248984Y0209811D03*
 X0243079Y0209811D03*
 X0241110Y0209811D03*
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@@ -387,10 +352,24 @@ X0272213Y0227921D03*
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 X0109417Y0061386D03*
 X0061780Y0026543D03*
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 D16*
 X0140520Y0263551D03*
 D17*
@@ -1037,14 +1035,6 @@ X0099181Y0242866D01*
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 X0100717Y0240567D01*
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@@ -1616,12 +1606,6 @@ X0106217Y0229928D01*
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@@ -5096,12 +5080,12 @@ X0162102Y0226502D01*
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 X0109417Y0061386D03*
 X0061780Y0026543D03*
-X0033236Y0247016D03*
 D16*
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 D17*
@@ -134,8 +134,10 @@ X0045441Y0113945D03*
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@@ -182,14 +184,10 @@ X0294063Y0355677D03*
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@@ -349,13 +349,6 @@ X0061780Y0026543D03*
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@@ -0,0 +1,41 @@
+"Qty";"Value";"Device";"Package";"Parts";"Description";"COPYRIGHT";"DESCRIPTION";"HEIGHT";"MANUFACTURER_NAME";"MANUFACTURER_PART_NUMBER";"MF";"MFR_NAME";"MOUSER_PART_NUMBER";"MOUSER_PRICE-STOCK";"MPN";"OC_FARNELL";"OC_NEWARK";"POPULARITY";"PROD_ID";"SPICEPREFIX";"VALUE";
+"3";"";"C-EUC0201";"C0201";"C4, C5, C7";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"5";"";"L-EUL5650M";"L5650M";"L9, L10, L11, L12, L13";"INDUCTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"L";"";
+"1";"";"PINHD-2X6";"2X06";"JP1";"PIN HEADER";"";"";"";"";"";"";"";"";"";"";"";"";"8";"";"";"";
+"1";"";"PINHD-2X7";"2X07";"JP2";"PIN HEADER";"";"";"";"";"";"";"";"";"";"";"";"";"8";"";"";"";
+"25";"0.1µF";"C-EUC0201";"C0201";"C16, C18, C20, C22, C24, C26, C28, C30, C32, C34, C35, C36, C37, C41, C42, C43, C44, C64, C65, C66, C67, C87, C88, C90, C91";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"1";"0.1µf";"C-EUC0201";"C0201";"C92";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"0.33µF";"C-EUC0201";"C0201";"C2, C6";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"0.47µF";"C-EUC0201";"C0201";"C9, C10";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"1";"0.47µf";"C-EUC0201";"C0201";"C3";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"3";"0.65k";"R-EU_R0201";"R0201";"R6, R8, R10";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"9";"0R";"R-EU_R0201";"R0201";"R5, R14, R15, R19, R20, R27, R28, R32, R33";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"8";"1.3nH";"L-USL0201";"L0201";"L1, L2, L3, L4, L5, L6, L7, L8";"INDUCTOR, American symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"L";"";
+"1";"1000pF";"C-EUC0201";"C0201";"C8";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"4";"100R";"R-EU_R0201";"R0201";"R1, R12, R13, R26";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"2";"10nF";"C-EUC0201";"C0201";"C61, C84";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"3";"10nF";"C-EUC0402";"C0402";"C15, C17, C19";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"18";"";"C";"";
+"6";"10pF";"C-EUC0201";"C0201";"C1, C62, C63, C85, C86, C89";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"5";"10µF";"C-EUC1210";"C1210";"C23, C27, C31, C45, C47";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"11";"142-0731-211";"142-0731-211";"1420731211";"J1, J2, J5, J6, J7, J8, J9, J10, J11, J12, J13";"SMA Connector Jack, Female Socket 50 Ohms Through Hole Solder";"";"SMA Connector Jack, Female Socket 50 Ohms Through Hole Solder";"9.8852mm";"Cinch Connectivity Solutions";"142-0731-211";"";"";"530-142-0731-211";"https://www.mouser.co.uk/ProductDetail/Johnson-Cinch-Connectivity-Solutions/142-0731-211?qs=HFfMDpzxxd0OVzI3hm9tuA%3D%3D";"";"";"";"";"";"";"";
+"6";"1k";"R-EU_R0201";"R0201";"R2, R3, R4, R7, R9, R11";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"10";"1µF";"C-EUC0201";"C0201";"C11, C12, C13, C14, C59, C68, C69, C70, C71, C82";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"8";"200k";"R-EU_R0201";"R0201";"R22, R23, R24, R25, R35, R36, R37, R38";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"6";"22-23-2021";"22-23-2021";"22-23-2021";"X10, X11, X12, X13, X14, X15";".100" (2.54mm) Center Header - 2 Pin";"";"";"";"";"";"MOLEX";"";"";"";"22-23-2021";"1462926";"25C3832";"40";"";"";"";
+"3";"22R";"R-EU_R0201";"R0201";"R39, R40, R41";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"6";"22µF";"C-EUC1210";"C1210";"C21, C25, C29, C33, C46, C51";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"30R";"R-EU_R0201";"R0201";"R17, R30";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"2";"31pF";"C-EUC0201";"C0201";"C60, C83";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"330R";"R-EU_R0201";"R0201";"R18, R31";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"20";"4.7µF";"C-EUC0201";"C0201";"C38, C39, C40, C48, C49, C50, C55, C56, C57, C58, C72, C73, C74, C75, C76, C77, C78, C79, C80, C81";"CAPACITOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"C";"";
+"2";"500R";"R-EU_R0201";"R0201";"R21, R34";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"2";"931R";"R-EU_R0201";"R0201";"R16, R29";"RESISTOR, European symbol";"";"";"";"";"";"";"";"";"";"";"";"";"0";"";"R";"";
+"1";"AD9523BCPZ";"AD9523BCPZ";"QFN50P1000X1000X100-73N";"IC1";"AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ";"";"AD9523BCPZ, PLL Clock Driver Dual, 72-Pin LFCSP VQ";"mm";"Analog Devices";"AD9523BCPZ";"";"";"584-AD9523BCPZ";"https://www.mouser.com/Search/Refine.aspx?Keyword=584-AD9523BCPZ";"";"";"";"";"";"";"";
+"2";"ADF4382ABCCZ";"ADF4382ABCCZ";"CC-48-10_ADI";"U1, U6";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"ADF4382ABCCZ";"";"Analog Devices Inc";"";"";"";"";"";"";"";"";"";
+"4";"ATS1005-3DB-FD-T05";"ATS1005-3DB-FD-T05";"SMT_DB-FD-T05_SUS";"U4, U5, U8, U10";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Susumu";"ATS1005-3DB-FD-T05";"";"";"";"";"";"";"";"";"";"";"";
+"2";"CJT-T-P-HH-ST-TH1";"CJT-T-P-HH-ST-TH1";"CONN_CJT-T-P-XX-ST-TH1_SAI";"J3, J4";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Samtec Inc";"CJT-T-P-HH-ST-TH1";"";"";"";"";"";"";"";"";"";"";"";
+"2";"CVHD-950-50.000";"CVHD-950-50.000";"SMD4_CVHD-950_CRX";"X5, X6";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"Crystek Crystals";"CVHD-950-50.000";"";"";"";"";"";"";"";"";"";"";"";
+"1";"ECOC-2522-100.000-3HC";"ECOC-2522-100.000-3HC";"SMD5_ECOC-2522_25P4X22_ECS";"X4";"";"Copyright (C) 2025 Ultra Librarian. All rights reserved.";"";"";"ECS International";"ECOC-2522-100.000-3HC";"";"";"";"";"";"";"";"";"";"";"";
+"4";"FBMH1608HL601-T";"FBMH1608HL601-T";"BEADC1608X90N";"FB1, FB2, FB3, FB4";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";"";
+"2";"Green";"LED-GREEN-0603-WE";"LED-0603";"D1, D2";"Green SMD LED";"";"";"";"";"";"";"";"";"";"";"";"";"";"DIO-16512";"";"Green";
+"4";"MTX2-143+";"MTX2-143+";"DQ1225_MNC";"U2, U3, U7, U9";"";"Copyright (C) 2024 Ultra Librarian. All rights reserved.";"";"";"";"MTX2-143+";"";"Mini Circuits";"";"";"";"";"";"";"";"";"";
@@ -798,8 +798,6 @@ X127429Y228217
 X118177Y228118
 X109220Y227921
 X100854Y226740
-X102724Y234713
-X102724Y234713
 X102724Y243571
 X102823Y255579
 X102528Y264437
@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0

 Drill Station Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.dri

- Date              : 05/04/2026 01:09
+ Date              : 19/04/2026 21:57
 Drills            : generated
 Device            : Excellon drill station, coordinate format 2.5 inch

@@ -33,13 +33,13 @@ Drills used:
 T04   0.0197inch    34
 T05   0.0250inch     4
 T06   0.0330inch     8
- T07   0.0394inch    84
+ T07   0.0394inch    82
 T08   0.0400inch    26
 T09   0.0470inch    44
 T10   0.0787inch     1
 T11   0.1260inch     4

-Total number of drills: 909
+Total number of drills: 907

 Plotfiles:

@@ -2,7 +2,7 @@ Generated by EAGLE CAM Processor 7.4.0

 Photoplotter Info File: C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.gpi

- Date              : 05/04/2026 01:12
+ Date              : 19/04/2026 21:58
 Plotfile          : C:/Users/dell/Desktop/CrowdSupply/RADAR_V6/4_Schematics and Boards Layout/4_6_Schematics/FrequencySynthesizerBoard/Clocks_Freq_Synth_board.bsk
 Apertures         : generated: 
 Device            : Gerber RS-274-X photoplotter, coordinate format 2.5 inch
@@ -0,0 +1,174 @@
+C1 48.37 59.91  90 10pF C0201
+C2 31.74 13.52   0 0.33ｵF C0201
+C3 49.46 45.72   0 0.47ｵf C0201
+C4 49.48 43.39   0  C0201
+C5 49.52 42.39   0  C0201
+C6 49.52 41.92   0 0.33ｵF C0201
+C7 49.51 40.39   0  C0201
+C8 49.51 39.87   0 1000pF C0201
+C9 48.76 37.89  90 0.47ｵF C0201
+C10 48.63 39.42   0 0.47ｵF C0201
+C11 47.37 50.30 270 1ｵF C0201
+C12 46.81 50.30 270 1ｵF C0201
+C13 45.40 50.35 270 1ｵF C0201
+C14 44.82 50.35 270 1ｵF C0201
+C15 86.78 30.16   0 10nF C0402
+C16 49.07 44.65  90 0.1ｵF C0201
+C17 64.58 24.27 270 10nF C0402
+C18 50.57 34.64 180 0.1ｵF C0201
+C19 52.86 24.27 270 10nF C0402
+C20 55.66 34.54   0 0.1ｵF C0201
+C21 10.00 30.60 270 22ｵF C1210
+C22 58.71 34.53   0 0.1ｵF C0201
+C23 21.00 30.50 270 10ｵF C1210
+C24 62.13 37.42   0 0.1ｵF C0201
+C25 35.40  4.90 270 22ｵF C1210
+C26 61.84 40.65  90 0.1ｵF C0201
+C27 45.90  5.30 270 10ｵF C1210
+C28 62.06 43.41   0 0.1ｵF C0201
+C29 81.20  4.90 270 22ｵF C1210
+C30 57.71 46.83   0 0.1ｵF C0201
+C31 70.50  5.00 270 10ｵF C1210
+C32 54.48 46.90  90 0.1ｵF C0201
+C33 18.10 95.10  90 22ｵF C1210
+C34 49.20 38.86 180 0.1ｵF C0201
+C35 57.21 34.54   0 0.1ｵF C0201
+C36 61.16 34.74   0 0.1ｵF C0201
+C37 62.20 38.96   0 0.1ｵF C0201
+C38 42.23 55.44 180 4.7ｵF C0201
+C39 42.56 52.07 270 4.7ｵF C0201
+C40 46.11 50.52   0 4.7ｵF C0201
+C41 62.26 41.88   0 0.1ｵF C0201
+C42 61.85 45.25  90 0.1ｵF C0201
+C43 56.56 46.73   0 0.1ｵF C0201
+C44 52.33 46.82 180 0.1ｵF C0201
+C45 19.40 85.70 180 10ｵF C1210
+C46 34.30 93.80 270 22ｵF C1210
+C47 30.90 86.70   0 10ｵF C1210
+C48 48.11 50.54   0 4.7ｵF C0201
+C49 48.11 50.06   0 4.7ｵF C0201
+C50 51.64 53.12 270 4.7ｵF C0201
+C51 87.70 87.30  90 22ｵF C1210
+C55 44.21 59.60   0 4.7ｵF C0201
+C56 51.86 59.44 180 4.7ｵF C0201
+C57 51.69 57.60  90 4.7ｵF C0201
+C58 51.62 54.17 270 4.7ｵF C0201
+C59 49.65 49.57  90 1ｵF C0201
+C60 52.95 54.60  90 31pF C0201
+C61 53.66 52.04   0 10nF C0201
+C62 49.86 50.62 270 10pF C0201
+C63 45.84 61.00  90 10pF C0201
+C64 46.57 61.00  90 0.1ｵF C0201
+C65 45.15 61.00  90 0.1ｵF C0201
+C66 49.11 59.94  90 0.1ｵF C0201
+C67 47.66 59.94  90 0.1ｵF C0201
+C68 61.74 50.36 270 1ｵF C0201
+C69 61.19 50.33 270 1ｵF C0201
+C70 59.82 50.03 270 1ｵF C0201
+C71 59.19 50.02 270 1ｵF C0201
+C72 66.00 53.21 270 4.7ｵF C0201
+C73 66.10 54.16 270 4.7ｵF C0201
+C74 66.04 57.61  90 4.7ｵF C0201
+C75 64.72 59.83 180 4.7ｵF C0201
+C76 58.07 59.64   0 4.7ｵF C0201
+C77 56.62 55.38 180 4.7ｵF C0201
+C78 56.92 52.33 180 4.7ｵF C0201
+C79 60.47 50.84   0 4.7ｵF C0201
+C80 62.25 50.66 270 4.7ｵF C0201
+C81 62.70 50.66 270 4.7ｵF C0201
+C82 64.80 49.14 180 1ｵF C0201
+C83 67.62 55.61  90 31pF C0201
+C84 68.70 54.96  90 10nF C0201
+C85 63.74 50.66 270 10pF C0201
+C86 60.20 61.00  90 10pF C0201
+C87 60.94 61.00  90 0.1ｵF C0201
+C88 59.44 61.00  90 0.1ｵF C0201
+C89 62.70 59.91  90 10pF C0201
+C90 63.47 59.91  90 0.1ｵF C0201
+C91 61.97 59.91  90 0.1ｵF C0201
+C92 16.93 67.92 180 0.1ｵf C0201
+D1 41.75 59.88  90 Green LED-0603
+D2 56.83 60.61  90 Green LED-0603
+FB1 68.41 56.87 180 FBMH1608HL601-T BEADC1608X90N
+FB2 53.58 56.01 180 FBMH1608HL601-T BEADC1608X90N
+FB3 52.06 49.65   0 FBMH1608HL601-T BEADC1608X90N
+FB4 63.46 48.33 270 FBMH1608HL601-T BEADC1608X90N
+IC1 55.70 40.67   0 AD9523BCPZ QFN50P1000X1000X100-73N
+J1 52.94 90.00   0 142-0731-211 1420731211
+J2 92.86 49.36  90 142-0731-211 1420731211
+J5 64.56 17.84   0 142-0731-211 1420731211
+J6 52.79 18.27   0 142-0731-211 1420731211
+J7 92.71 30.20  90 142-0731-211 1420731211
+J8 92.71 16.28   0 142-0731-211 1420731211
+J9  9.85 82.37 180 142-0731-211 1420731211
+J10 45.93 74.00   0 142-0731-211 1420731211
+J11 60.20 74.00   0 142-0731-211 1420731211
+J12 74.38 71.98  45 142-0731-211 1420731211
+J13 11.67 67.91  90 142-0731-211 1420731211
+L1 48.80 59.32   0 1.3nH L0201
+L2 46.29 60.40   0 1.3nH L0201
+L3 45.44 60.40   0 1.3nH L0201
+L4 47.95 59.32   0 1.3nH L0201
+L5 60.67 60.40   0 1.3nH L0201
+L6 59.77 60.40   0 1.3nH L0201
+L7 63.17 59.31   0 1.3nH L0201
+L8 62.27 59.31   0 1.3nH L0201
+L9 15.40 31.90 180  L5650M
+L10 40.80  6.20 180  L5650M
+L11 75.80  6.30   0  L5650M
+L12 22.20 91.00  90  L5650M
+L13 29.60 92.70  90  L5650M
+R1 61.47 51.11   0 100R R0201
+R2  7.14 58.81 180 1k R0201
+R3  7.38 59.72 270 1k R0201
+R4 31.78 14.16   0 1k R0201
+R5 48.02 38.16   0 0R R0201
+R6 16.38 13.37 270 0.65k R0201
+R7 16.37 12.32 270 1k R0201
+R8 13.86 21.50  90 0.65k R0201
+R9 13.82 22.69  90 1k R0201
+R10 16.36 21.55  90 0.65k R0201
+R11 16.42 22.70  90 1k R0201
+R12 47.11 51.07   0 100R R0201
+R13 45.11 51.07   0 100R R0201
+R14 51.74 56.17 270 0R R0201
+R15 51.96 55.04   0 0R R0201
+R16 52.78 53.71 180 931R R0201
+R17 52.48 52.85  90 30R R0201
+R18 52.71 52.07   0 330R R0201
+R19 51.62 50.89   0 0R R0201
+R20 50.61 50.88   0 0R R0201
+R21 42.53 57.17 270 500R R0201
+R22 41.78 56.69 270 200k R0201
+R23 41.34 55.73  90 200k R0201
+R24 42.32 54.09 270 200k R0201
+R25 41.39 54.64 270 200k R0201
+R26 59.47 51.16   0 100R R0201
+R27 65.87 56.55   0 0R R0201
+R28 65.90 55.35   0 0R R0201
+R29 66.92 55.36 180 931R R0201
+R30 67.63 54.52  90 30R R0201
+R31 68.47 54.26   0 330R R0201
+R32 65.46 50.90   0 0R R0201
+R33 64.54 50.90   0 0R R0201
+R34 56.82 58.21 270 500R R0201
+R35 56.94 56.71 270 200k R0201
+R36 55.84 56.16 270 200k R0201
+R37 56.84 54.16 270 200k R0201
+R38 56.24 54.61 270 200k R0201
+R39 63.22 41.38   0 22R R0201
+R40 59.45 33.47 270 22R R0201
+R41 57.97 33.47 270 22R R0201
+U1 47.12 55.12 180 ADF4382ABCCZ CC-48-10_ADI
+U2 45.91 65.00 270 MTX2-143+ DQ1225_MNC
+U3 52.91 64.38 270 MTX2-143+ DQ1225_MNC
+U4 45.91 68.00 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U5 52.94 68.68 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U6 61.48 55.12 180 ADF4382ABCCZ CC-48-10_ADI
+U7 60.21 65.00 270 MTX2-143+ DQ1225_MNC
+U8 60.20 68.00 180 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+U9 67.91 65.62 225 MTX2-143+ DQ1225_MNC
+U10 70.09 67.84 135 ATS1005-3DB-FD-T05 SMT_DB-FD-T05_SUS
+X4 23.07 49.95   0 ECOC-2522-100.000-3HC SMD5_ECOC-2522_25P4X22_ECS
+X5 34.12 31.62  90 CVHD-950-50.000 SMD4_CVHD-950_CRX
+X6 33.87 19.97  90 CVHD-950-50.000 SMD4_CVHD-950_CRX
@@ -159,8 +159,6 @@ X0127429Y0228217D03*
 X0118177Y0228118D03*
 X0109220Y0227921D03*
 X0100854Y0226740D03*
-X0102724Y0234713D03*
-X0102724Y0234713D03*
 X0102724Y0243571D03*
 X0102823Y0255579D03*
 X0102528Y0264437D03*
@@ -1334,10 +1334,8 @@ X0102528Y0273197D03*
 X0102528Y0264437D03*
 X0102823Y0255579D03*
 X0102724Y0243571D03*
-X0102724Y0234713D03*
-X0102724Y0234713D03*
-X0100854Y0226740D03*
 X0109220Y0227921D03*
+X0100854Y0226740D03*
 X0118177Y0228118D03*
 X0127429Y0228217D03*
 X0136976Y0228217D03*
@@ -163,10 +163,8 @@ void ADAR1000Manager::switchToTXMode() {
    DIAG("BF", "Step 3: PA bias ON");
    setPABias(true);
    delayUs(50);
-    // Step 4 (former setADTR1107Control(true)) removed: TR pin is FPGA-owned.
-    // Chip follows adar_tr_x; TX path is asserted by the FPGA chirp FSM, not
-    // by SPI here. Write per-channel TX enables so the FPGA TR override has
-    // something to gate.
+    DIAG("BF", "Step 4: ADTR1107 -> TX");
+    setADTR1107Control(true);

    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
        adarWrite(dev, REG_RX_ENABLES, 0x00, BROADCAST_OFF);
@@ -187,7 +185,8 @@ void ADAR1000Manager::switchToRXMode() {
    DIAG("BF", "Step 2: Disable PA supplies");
    disablePASupplies();
    delayUs(10);
-    // Step 3 (former setADTR1107Control(false)) removed: FPGA owns TR pin.
+    DIAG("BF", "Step 3: ADTR1107 -> RX");
+    setADTR1107Control(false);
    DIAG("BF", "Step 4: Enable LNA supplies");
    enableLNASupplies();
    delayUs(50);
@@ -205,11 +204,39 @@ void ADAR1000Manager::switchToRXMode() {
    DIAG("BF", "switchToRXMode() complete");
 }

-// fastTXMode, fastRXMode, pulseTXMode, pulseRXMode: REMOVED.
-// The chirp hot path owns T/R switching via the FPGA adar_tr_x pins
-// (see 9_Firmware/9_2_FPGA/plfm_chirp_controller.v). The old SPI-RMW per
-// chirp was architecturally redundant, raced the FPGA, and toggled the
-// wrong bit of REG_SW_CONTROL (TR_SOURCE instead of TR_SPI).
+void ADAR1000Manager::fastTXMode() {
+    DIAG("BF", "fastTXMode(): ADTR1107 -> TX (no bias sequencing)");
+    setADTR1107Control(true);
+    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
+        adarWrite(dev, REG_RX_ENABLES, 0x00, BROADCAST_OFF);
+        adarWrite(dev, REG_TX_ENABLES, 0x0F, BROADCAST_OFF);
+        devices_[dev]->current_mode = BeamDirection::TX;
+    }
+    current_mode_ = BeamDirection::TX;
+}
+
+void ADAR1000Manager::fastRXMode() {
+    DIAG("BF", "fastRXMode(): ADTR1107 -> RX (no bias sequencing)");
+    setADTR1107Control(false);
+    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
+        adarWrite(dev, REG_TX_ENABLES, 0x00, BROADCAST_OFF);
+        adarWrite(dev, REG_RX_ENABLES, 0x0F, BROADCAST_OFF);
+        devices_[dev]->current_mode = BeamDirection::RX;
+    }
+    current_mode_ = BeamDirection::RX;
+}
+
+void ADAR1000Manager::pulseTXMode() {
+    DIAG("BF", "pulseTXMode(): TR switch only");
+    setADTR1107Control(true);
+    last_switch_time_us_ = HAL_GetTick() * 1000;
+}
+
+void ADAR1000Manager::pulseRXMode() {
+    DIAG("BF", "pulseRXMode(): TR switch only");
+    setADTR1107Control(false);
+    last_switch_time_us_ = HAL_GetTick() * 1000;
+}

 // Beam Steering
 bool ADAR1000Manager::setBeamAngle(float angle_degrees, BeamDirection direction) {
@@ -341,10 +368,25 @@ void ADAR1000Manager::writeRegister(uint8_t deviceIndex, uint32_t address, uint8
 }

 // Configuration
-// setSwitchSettlingTime, setFastSwitchMode: REMOVED.
-// Their only reader was the deleted setADTR1107Control; setFastSwitchMode(true)
-// also violated the ADTR1107 datasheet bias sequence (PA + LNA biased to
-// operational simultaneously). Per-chirp T/R is FPGA-owned now.
+void ADAR1000Manager::setSwitchSettlingTime(uint32_t us) {
+    switch_settling_time_us_ = us;
+}
+
+void ADAR1000Manager::setFastSwitchMode(bool enable) {
+    DIAG("BF", "setFastSwitchMode(%s)", enable ? "ON" : "OFF");
+    fast_switch_mode_ = enable;
+    if (enable) {
+        switch_settling_time_us_ = 10;
+        DIAG("BF", "  settling time = 10 us, enabling PA+LNA supplies and bias simultaneously");
+        enablePASupplies();
+        enableLNASupplies();
+        setPABias(true);
+        setLNABias(true);
+    } else {
+        switch_settling_time_us_ = 50;
+        DIAG("BF", "  settling time = 50 us");
+    }
+}

 void ADAR1000Manager::setBeamDwellTime(uint32_t ms) {
    beam_dwell_time_ms_ = ms;
@@ -386,30 +428,15 @@ bool ADAR1000Manager::initializeSingleDevice(uint8_t deviceIndex) {
    DIAG("BF", "  dev[%u] set RAM bypass (bias+beam)", deviceIndex);
    adarSetRamBypass(deviceIndex, BROADCAST_OFF);

-    // Hand per-chirp T/R switching to the FPGA.
-    // Set TR_SOURCE (REG_SW_CONTROL bit 2) = 1 so the chip's internal
-    // RX_EN_OVERRIDE / TX_EN_OVERRIDE follow the external TR pin (driven by
-    // plfm_chirp_controller's adar_tr_x output). See ADAR1000 datasheet
-    // "Theory of Operation" -- SPI Control vs TR Pin Control.
-    // Without this write, the FPGA's TR pin is ignored and the chip stays
-    // in RX state (TR_SPI POR default).
-    DIAG("BF", "  dev[%u] SW_CONTROL: TR_SOURCE=1 (FPGA owns TR pin)", deviceIndex);
-    adarWrite(deviceIndex, REG_SW_CONTROL, (1 << 2), BROADCAST_OFF);
-
    // Initialize ADC
    DIAG("BF", "  dev[%u] enable ADC (2MHz clk)", deviceIndex);
    adarWrite(deviceIndex, REG_ADC_CONTROL, ADAR1000_ADC_2MHZ_CLK | ADAR1000_ADC_EN, BROADCAST_OFF);

    // Verify communication with scratchpad test
-    // Audit F-4.4: on SPI failure, previously marked the device initialized
-    // anyway, so downstream (e.g. PA enable) could drive PA gates out-of-spec
-    // on a dead bus. Now propagate the failure so initializeAllDevices aborts.
    DIAG("BF", "  dev[%u] verifying SPI communication...", deviceIndex);
    bool comms_ok = verifyDeviceCommunication(deviceIndex);
    if (!comms_ok) {
-        DIAG_ERR("BF", "  dev[%u] scratchpad verify FAILED -- device NOT marked initialized", deviceIndex);
-        devices_[deviceIndex]->initialized = false;
-        return false;
+        DIAG_WARN("BF", "  dev[%u] scratchpad verify FAILED but marking initialized anyway", deviceIndex);
    }

    devices_[deviceIndex]->initialized = true;
@@ -437,11 +464,9 @@ bool ADAR1000Manager::initializeADTR1107Sequence() {
    HAL_GPIO_WritePin(EN_P_3V3_SW_GPIO_Port, EN_P_3V3_SW_Pin, GPIO_PIN_SET);
    HAL_Delay(1);

-    // Step 4: CTRL_SW safe-default is RX.
-    // FPGA-owned path: with TR_SOURCE=1 (set in initializeSingleDevice) the
-    // chip follows adar_tr_x, which is 0 in the FPGA FSM's IDLE state = RX.
-    // No SPI write needed here.
-    DIAG("BF", "Step 4: CTRL_SW -> RX (FPGA adar_tr_x idle-low == RX)");
+    // Step 4: Set CTRL_SW to RX mode initially via GPIO
+    DIAG("BF", "Step 4: CTRL_SW -> RX (initial safe mode)");
+    setADTR1107Control(false); // RX mode
    HAL_Delay(1);

    // Step 5: Set VGG_LNA to 0
@@ -543,7 +568,7 @@ bool ADAR1000Manager::setAllDevicesRXMode() {
 void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
    if (direction == BeamDirection::TX) {
        DIAG_SECTION("ADTR1107 -> TX MODE");
-        // setADTR1107Control(true) removed: TR pin is FPGA-driven.
+        setADTR1107Control(true); // TX mode

        // Step 1: Disable LNA power first
        DIAG("BF", "  Disable LNA supplies");
@@ -573,11 +598,10 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
        }
        HAL_Delay(5);

-        // Step 5: TR switch state is FPGA-driven. TR_SOURCE=1 is set once in
-        // initializeSingleDevice, so the chip already follows adar_tr_x.
-        // Only BIAS_EN needs to be asserted here.
-        DIAG("BF", "  BIAS_EN (TR source still = FPGA adar_tr_x)");
+        // Step 5: Set TR switch to TX mode
+        DIAG("BF", "  TR switch -> TX (TR_SOURCE=1, BIAS_EN)");
        for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
+            adarSetBit(dev, REG_SW_CONTROL, 2, BROADCAST_OFF); // TR_SOURCE = 1 (TX)
            adarSetBit(dev, REG_MISC_ENABLES, 5, BROADCAST_OFF); // BIAS_EN
        }
        DIAG("BF", "  ADTR1107 TX mode complete");
@@ -585,7 +609,7 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
    } else {
        // RECEIVE MODE: Enable LNA, Disable PA
        DIAG_SECTION("ADTR1107 -> RX MODE");
-        // setADTR1107Control(false) removed: TR pin is FPGA-driven.
+        setADTR1107Control(false); // RX mode

        // Step 1: Disable PA power first
        DIAG("BF", "  Disable PA supplies");
@@ -616,21 +640,34 @@ void ADAR1000Manager::setADTR1107Mode(BeamDirection direction) {
        }
        HAL_Delay(5);

-        // Step 5: TR switch state is FPGA-driven (TR_SOURCE left at 1).
-        // Only LNA_BIAS_OUT_EN needs to be asserted here.
-        DIAG("BF", "  LNA_BIAS_OUT_EN (TR source still = FPGA adar_tr_x)");
+        // Step 5: Set TR switch to RX mode
+        DIAG("BF", "  TR switch -> RX (TR_SOURCE=0, LNA_BIAS_OUT_EN)");
        for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
+            adarResetBit(dev, REG_SW_CONTROL, 2, BROADCAST_OFF); // TR_SOURCE = 0 (RX)
            adarSetBit(dev, REG_MISC_ENABLES, 4, BROADCAST_OFF); // LNA_BIAS_OUT_EN
        }
        DIAG("BF", "  ADTR1107 RX mode complete");
    }
 }

-// setADTR1107Control, setTRSwitchPosition: REMOVED.
-// The per-device SPI RMW of REG_SW_CONTROL bit 2 (TR_SOURCE) was both wrong
-// (it toggled the *control source*, not the TX/RX state -- TR_SPI is bit 1)
-// and redundant with the FPGA's plfm_chirp_controller adar_tr_x output.
-// TR_SOURCE is now set to 1 exactly once in initializeSingleDevice.
+void ADAR1000Manager::setADTR1107Control(bool tx_mode) {
+    DIAG("BF", "setADTR1107Control(%s): setting TR switch on all %u devices, settling %lu us",
+         tx_mode ? "TX" : "RX", (unsigned)devices_.size(), (unsigned long)switch_settling_time_us_);
+    for (uint8_t dev = 0; dev < devices_.size(); ++dev) {
+        setTRSwitchPosition(dev, tx_mode);
+    }
+    delayUs(switch_settling_time_us_);
+}
+
+void ADAR1000Manager::setTRSwitchPosition(uint8_t deviceIndex, bool tx_mode) {
+    if (tx_mode) {
+        // TX mode: Set TR_SOURCE = 1
+        adarSetBit(deviceIndex, REG_SW_CONTROL, 2, BROADCAST_OFF);
+    } else {
+        // RX mode: Set TR_SOURCE = 0
+        adarResetBit(deviceIndex, REG_SW_CONTROL, 2, BROADCAST_OFF);
+    }
+}

 // Add the new public method
 bool ADAR1000Manager::setCustomBeamPattern16(const uint8_t phase_pattern[16], BeamDirection direction) {
@@ -693,21 +730,10 @@ void ADAR1000Manager::setLNABias(bool enable) {
 }

 void ADAR1000Manager::delayUs(uint32_t microseconds) {
-    // Audit F-4.7: the prior implementation was a calibrated __NOP() busy-loop
-    // that silently drifted with compiler optimization, cache state, and flash
-    // wait-states. The ADAR1000 PLL/TX settling times require a real clock, so
-    // we poll the DWT cycle counter instead. One-time TRCENA/CYCCNTENA enable
-    // is idempotent; subsequent calls skip the init branch via DWT->CTRL read.
-    if ((DWT->CTRL & DWT_CTRL_CYCCNTENA_Msk) == 0U) {
-        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
-        DWT->CYCCNT       = 0U;
-        DWT->CTRL        |= DWT_CTRL_CYCCNTENA_Msk;
-    }
-    const uint32_t cycles_per_us = SystemCoreClock / 1000000U;
-    const uint32_t start         = DWT->CYCCNT;
-    const uint32_t target        = microseconds * cycles_per_us;
-    while ((DWT->CYCCNT - start) < target) {
-        /* CYCCNT wraps cleanly modulo 2^32 — subtraction stays correct. */
+    // Simple implementation - for F7 @ 216MHz, each loop ~7 cycles ≈ 0.032us
+    volatile uint32_t cycles = microseconds * 10; // Adjust this multiplier for your clock
+    while (cycles--) {
+        __NOP();
    }
 }

@@ -769,25 +795,14 @@ void ADAR1000Manager::setChipSelect(uint8_t deviceIndex, bool state) {
 }

 void ADAR1000Manager::adarWrite(uint8_t deviceIndex, uint32_t mem_addr, uint8_t data, uint8_t broadcast) {
-    // Audit F-4.1: the broadcast SPI opcode path (`instruction[0] = 0x08`)
-    // has never been exercised on silicon and is structurally questionable —
-    // setChipSelect() only toggles ONE device's CS line, so even if a caller
-    // opts into the broadcast opcode today, only the single selected chip
-    // actually sees the frame. Until a HIL test confirms multi-CS semantics,
-    // route every broadcast write through a per-device unicast loop. This
-    // preserves caller intent (all four devices take the write) and makes
-    // the dead opcode-0x08 path unreachable at runtime.
-    if (broadcast == BROADCAST_ON) {
-        DIAG_WARN("BF", "adarWrite: broadcast=1 lowered to per-device unicast (addr=0x%03lX data=0x%02X)",
-                  (unsigned long)mem_addr, data);
-        for (uint8_t d = 0; d < devices_.size(); ++d) {
-            adarWrite(d, mem_addr, data, BROADCAST_OFF);
-        }
-        return;
+    uint8_t instruction[3];
+
+    if (broadcast) {
+        instruction[0] = 0x08;
+    } else {
+        instruction[0] = ((devices_[deviceIndex]->dev_addr & 0x03) << 5);
    }

-    uint8_t instruction[3];
-    instruction[0] = ((devices_[deviceIndex]->dev_addr & 0x03) << 5);
    instruction[0] |= (0x1F00 & mem_addr) >> 8;
    instruction[1] = (0xFF & mem_addr);
    instruction[2] = data;
@@ -820,26 +835,12 @@ uint8_t ADAR1000Manager::adarRead(uint8_t deviceIndex, uint32_t mem_addr) {
 }

 void ADAR1000Manager::adarSetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
-    // Audit F-4.2: broadcast-RMW is unsafe. The read samples a single device
-    // but the write fans out to all four, overwriting the other three with
-    // deviceIndex's state. Reject and surface the mistake.
-    if (broadcast == BROADCAST_ON) {
-        DIAG_ERR("BF", "adarSetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
-                 deviceIndex, (unsigned long)mem_addr, bit);
-        return;
-    }
    uint8_t temp = adarRead(deviceIndex, mem_addr);
    uint8_t data = temp | (1 << bit);
    adarWrite(deviceIndex, mem_addr, data, broadcast);
 }

 void ADAR1000Manager::adarResetBit(uint8_t deviceIndex, uint32_t mem_addr, uint8_t bit, uint8_t broadcast) {
-    // Audit F-4.2: see adarSetBit.
-    if (broadcast == BROADCAST_ON) {
-        DIAG_ERR("BF", "adarResetBit: broadcast RMW is unsafe, ignored (dev=%u addr=0x%03lX bit=%u)",
-                 deviceIndex, (unsigned long)mem_addr, bit);
-        return;
-    }
    uint8_t temp = adarRead(deviceIndex, mem_addr);
    uint8_t data = temp & ~(1 << bit);
    adarWrite(deviceIndex, mem_addr, data, broadcast);
@@ -867,22 +868,11 @@ void ADAR1000Manager::adarSetRamBypass(uint8_t deviceIndex, uint8_t broadcast) {
 }

 void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4) per API contract documented in
-    // ADAR1000_AGC.cpp and matching ADI datasheet terminology.
-    // Reject out-of-range early so a stale 0-based caller does not
-    // silently wrap to ((0-1) & 0x03) == 3 and write to CH4.
-    // See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetRxPhase: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
    uint8_t i_val = VM_I[phase % 128];
    uint8_t q_val = VM_Q[phase % 128];

-    // Subtract 1 to convert 1-based channel to 0-based register offset
-    // before masking. See issue #90.
-    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + ((channel - 1) & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + ((channel - 1) & 0x03) * 2;
+    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
+    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;

    adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
    adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -890,40 +880,25 @@ void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 }

 void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetTxPhase: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
    uint8_t i_val = VM_I[phase % 128];
    uint8_t q_val = VM_Q[phase % 128];

-    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + ((channel - 1) & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + ((channel - 1) & 0x03) * 2;
+    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
+    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;

    adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
    adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
-    adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
+    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
 }

 void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetRxVgaGain: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
-    uint32_t mem_addr = REG_CH1_RX_GAIN + ((channel - 1) & 0x03);
+    uint32_t mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
    adarWrite(deviceIndex, mem_addr, gain, broadcast);
    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
 }

 void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    // channel is 1-based (CH1..CH4). See issue #90.
-    if (channel < 1 || channel > 4) {
-        DIAG("BF", "adarSetTxVgaGain: channel %u out of range [1..4], ignored", channel);
-        return;
-    }
-    uint32_t mem_addr = REG_CH1_TX_GAIN + ((channel - 1) & 0x03);
+    uint32_t mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
    adarWrite(deviceIndex, mem_addr, gain, broadcast);
    adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 }
@@ -48,11 +48,10 @@ public:
    // Mode Switching
    void switchToTXMode();
    void switchToRXMode();
-    // fastTXMode/fastRXMode/pulseTXMode/pulseRXMode were removed: per-chirp T/R
-    // switching is owned by the FPGA (plfm_chirp_controller -> adar_tr_x pins,
-    // requires TR_SOURCE=1 in REG_SW_CONTROL, set in initializeSingleDevice).
-    // The old SPI RMW path was architecturally redundant and also toggled the
-    // wrong bit (TR_SOURCE instead of TR_SPI). See PR for details.
+    void fastTXMode();
+    void fastRXMode();
+    void pulseTXMode();
+    void pulseRXMode();

    // Beam Steering
    bool setBeamAngle(float angle_degrees, BeamDirection direction);
@@ -70,8 +69,7 @@ public:
    bool setAllDevicesTXMode();
    bool setAllDevicesRXMode();
    void setADTR1107Mode(BeamDirection direction);
-    // setADTR1107Control removed -- it only wrapped the now-deleted
-    // setTRSwitchPosition SPI path. FPGA drives the TR pin directly.
+    void setADTR1107Control(bool tx_mode);

    // Monitoring and Diagnostics
    float readTemperature(uint8_t deviceIndex);
@@ -80,11 +78,8 @@ public:
    void writeRegister(uint8_t deviceIndex, uint32_t address, uint8_t value);

    // Configuration
-    // setSwitchSettlingTime / setFastSwitchMode removed: their only reader was
-    // the deleted setADTR1107Control SPI path, and setFastSwitchMode(true)
-    // also bundled a datasheet-violating PA+LNA-biased-simultaneously side
-    // effect. Per-chirp settling is now FPGA-owned. Callers that need a
-    // warm-up bias state should use switchToTXMode / switchToRXMode instead.
+    void setSwitchSettlingTime(uint32_t us);
+    void setFastSwitchMode(bool enable);
    void setBeamDwellTime(uint32_t ms);

    // Getters
@@ -105,8 +100,8 @@ public:
    };

    // Configuration
-    // fast_switch_mode_ / switch_settling_time_us_ removed: both had no
-    // readers after the FPGA-owned TR refactor.
+    bool fast_switch_mode_ = false;
+    uint32_t switch_settling_time_us_ = 50;
    uint32_t beam_dwell_time_ms_ = 100;
    uint32_t last_switch_time_us_ = 0;

@@ -172,7 +167,7 @@ public:
    void adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast);
    void adarSetTxBias(uint8_t deviceIndex, uint8_t broadcast);
    uint8_t adarAdcRead(uint8_t deviceIndex, uint8_t broadcast);
-    // setTRSwitchPosition removed -- FPGA owns TR pin. See PR.
+    void setTRSwitchPosition(uint8_t deviceIndex, bool tx_mode);

 private:

@@ -483,14 +483,11 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
    DIAG("SYS", "executeChirpSequence: num_chirps=%d T1=%.2f PRI1=%.2f T2=%.2f PRI2=%.2f",
         num_chirps, T1, PRI1, T2, PRI2);
    // First chirp sequence (microsecond timing)
-    // T/R switching is owned by the FPGA plfm_chirp_controller: its chirp
-    // FSM drives adar_tr_x high during LONG_CHIRP/SHORT_CHIRP and low during
-    // listen/guard. new_chirp (GPIOD_8) triggers the FSM out of IDLE.
-    // The MCU's old pulseTXMode/pulseRXMode SPI path was redundant and raced
-    // the FPGA -- removed.
    for(int i = 0; i < num_chirps; i++) {
        HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_8); // New chirp signal to FPGA
+        adarManager.pulseTXMode();
        delay_us((uint32_t)T1);
+        adarManager.pulseRXMode();
        delay_us((uint32_t)(PRI1 - T1));
    }

@@ -499,8 +496,11 @@ void executeChirpSequence(int num_chirps, float T1, float PRI1, float T2, float
    // Second chirp sequence (nanosecond timing)
    for(int i = 0; i < num_chirps; i++) {
    	HAL_GPIO_TogglePin(GPIOD, GPIO_PIN_8); // New chirp signal to FPGA
+        adarManager.pulseTXMode();
        delay_ns((uint32_t)(T2 * 1000));
+        adarManager.pulseRXMode();
        delay_ns((uint32_t)((PRI2 - T2) * 1000));
+
    }
 }

@@ -513,9 +513,9 @@ void runRadarPulseSequence() {
    DIAG("SYS", "runRadarPulseSequence #%d: m_max=%d n_max=%d y_max=%d",
         sequence_count, m_max, n_max, y_max);

-    // Fast per-chirp switching is now FPGA-owned (plfm_chirp_controller
-    // adar_tr_x), not MCU-driven. setFastSwitchMode(true) call removed.
-    DIAG("BF", "Beam sweep start (FPGA owns per-chirp T/R switching)");
+    // Configure for fast switching
+    DIAG("BF", "Enabling fast-switch mode for beam sweep");
+    adarManager.setFastSwitchMode(true);

    int m = 1; // Chirp counter
    int n = 1; // Beam Elevation position counter
@@ -406,11 +406,3 @@ static int mock_spi_init_stub(void) { return 0; }
 const struct no_os_spi_platform_ops stm32_spi_ops = {
    .init = mock_spi_init_stub,
 };
-
-/* ========================= CMSIS-Core stub storage ======================= */
-/* See stm32_hal_mock.h for rationale. SystemCoreClock = 0 forces delayUs() to
- * return immediately under host test builds. DWT->CTRL pre-enabled so the
- * one-time-init branch is skipped deterministically. */
-struct _DWT_Mock_Type       _dwt_mock       = { .CTRL = DWT_CTRL_CYCCNTENA_Msk, .CYCCNT = 0 };
-struct _CoreDebug_Mock_Type _coredebug_mock = { .DEMCR = 0 };
-uint32_t                    SystemCoreClock = 0U;
@@ -242,26 +242,6 @@ uint8_t ADS7830_Measure_SingleEnded(ADC_HandleTypeDef *hadc, uint8_t channel);
 * if desired via a global flag. */
 extern int mock_printf_enabled;

-/* ========================= CMSIS-Core stubs ======================= */
-/* Minimum surface to let F-4.7's DWT-based delayUs() in ADAR1000_Manager.cpp
- * compile under the host mock build. SystemCoreClock is intentionally 0 so
- * target = microseconds * (SystemCoreClock / 1000000) is also 0, making the
- * busy-wait loop exit immediately regardless of argument. Pre-setting
- * DWT->CTRL with CYCCNTENA also skips the one-time init branch.            */
-
-#define DWT_CTRL_CYCCNTENA_Msk     (1UL << 0)
-#define CoreDebug_DEMCR_TRCENA_Msk (1UL << 24)
-
-struct _DWT_Mock_Type       { uint32_t CTRL; uint32_t CYCCNT; };
-struct _CoreDebug_Mock_Type { uint32_t DEMCR; };
-
-extern struct _DWT_Mock_Type       _dwt_mock;
-extern struct _CoreDebug_Mock_Type _coredebug_mock;
-extern uint32_t                    SystemCoreClock;
-
-#define DWT       (&_dwt_mock)
-#define CoreDebug (&_coredebug_mock)
-
 #ifdef __cplusplus
 }
 #endif
@@ -4,11 +4,6 @@ module ad9484_interface_400m (
    input wire [7:0] adc_d_n,        // ADC Data N
    input wire adc_dco_p,            // Data Clock Output P (400MHz)
    input wire adc_dco_n,            // Data Clock Output N (400MHz)
-    // Audit F-0.1: AD9484 OR (overrange) LVDS pair, DDR like data.
-    // Routed on the 50T main board to bank 14 pins M6/N6. Asserts for any
-    // sample whose absolute value exceeds full-scale.
-    input wire adc_or_p,
-    input wire adc_or_n,
    
    // System Interface
    input wire sys_clk,              // 100MHz system clock (for control only)
@@ -17,10 +12,7 @@ module ad9484_interface_400m (
    // Output at 400MHz domain
    output wire [7:0] adc_data_400m, // ADC data at 400MHz
    output wire adc_data_valid_400m, // Valid at 400MHz
-    output wire adc_dco_bufg,        // Buffered 400MHz DCO clock for downstream use
-    // Audit F-0.1: OR flag, clk_400m domain. High on any sample in the
-    // current 400 MHz cycle where the ADC reports overrange.
-    output wire adc_overrange_400m
+    output wire adc_dco_bufg         // Buffered 400MHz DCO clock for downstream use
 );

 // LVDS to single-ended conversion
@@ -174,54 +166,4 @@ end
 assign adc_data_400m = adc_data_400m_reg;
 assign adc_data_valid_400m = adc_data_valid_400m_reg;

-// ============================================================================
-// Audit F-0.1: AD9484 OR (overrange) capture
-// OR is a DDR LVDS pair (same as data). Buffer it, capture both edges with an
-// IDDR in the BUFIO domain, then OR the two phases into a single clk_400m
-// flag. Register once for stability. No latching — downstream is expected to
-// stickify in its own domain.
-// ============================================================================
-wire adc_or_raw;
-IBUFDS #(
-    .DIFF_TERM("FALSE"),
-    .IOSTANDARD("DEFAULT")
-) ibufds_or (
-    .O(adc_or_raw),
-    .I(adc_or_p),
-    .IB(adc_or_n)
-);
-
-wire adc_or_rise;
-wire adc_or_fall;
-IDDR #(
-    .DDR_CLK_EDGE("SAME_EDGE_PIPELINED"),
-    .INIT_Q1(1'b0),
-    .INIT_Q2(1'b0),
-    .SRTYPE("SYNC")
-) iddr_or (
-    .Q1(adc_or_rise),
-    .Q2(adc_or_fall),
-    .C(adc_dco_bufio),
-    .CE(1'b1),
-    .D(adc_or_raw),
-    .R(1'b0),
-    .S(1'b0)
-);
-
-reg adc_or_rise_bufg;
-reg adc_or_fall_bufg;
-always @(posedge adc_dco_buffered) begin
-    adc_or_rise_bufg <= adc_or_rise;
-    adc_or_fall_bufg <= adc_or_fall;
-end
-
-reg adc_overrange_r;
-always @(posedge adc_dco_buffered or negedge reset_n_400m) begin
-    if (!reset_n_400m)
-        adc_overrange_r <= 1'b0;
-    else
-        adc_overrange_r <= adc_or_rise_bufg | adc_or_fall_bufg;
-end
-assign adc_overrange_400m = adc_overrange_r;
-
 endmodule
@@ -17,12 +17,7 @@ module cdc_adc_to_processing #(
    input wire [WIDTH-1:0] src_data,
    input wire src_valid,
    output wire [WIDTH-1:0] dst_data,
-    output wire dst_valid,
-    // Audit F-1.2: overrun pulse in src_clk domain. Asserts for 1 src cycle
-    // whenever src_valid fires while the previous sample has not yet been
-    // acknowledged by the destination edge-detector (i.e., the transaction
-    // the CDC is silently dropping). Hold/count externally.
-    output wire overrun
+    output wire dst_valid
 `ifdef FORMAL
    ,output wire [WIDTH-1:0] fv_src_data_reg,
    output wire [1:0]       fv_src_toggle
@@ -135,36 +130,6 @@ module cdc_adc_to_processing #(
    assign dst_data = dst_data_reg;
    assign dst_valid = dst_valid_reg;

-    // ------------------------------------------------------------------
-    // Audit F-1.2: overrun detection
-    //
-    // The src-side `src_toggle` counter flips on each latched src_valid.
-    // We feed back a 1-bit "ack" toggle from the dst domain (flipped each
-    // time dst_valid fires) through a STAGES-deep synchronizer into the
-    // src domain. If a new src_valid arrives while src_toggle[0] already
-    // differs from the acked value, the previous sample is still in flight
-    // and this new latch drops it. Emit a 1-cycle overrun pulse.
-    // ------------------------------------------------------------------
-    reg dst_ack_toggle;
-    always @(posedge dst_clk) begin
-        if (!dst_reset_n)      dst_ack_toggle <= 1'b0;
-        else if (dst_valid_reg) dst_ack_toggle <= ~dst_ack_toggle;
-    end
-
-    (* ASYNC_REG = "TRUE" *) reg [STAGES-1:0] ack_sync_chain;
-    always @(posedge src_clk) begin
-        if (!src_reset_n) ack_sync_chain <= {STAGES{1'b0}};
-        else              ack_sync_chain <= {ack_sync_chain[STAGES-2:0], dst_ack_toggle};
-    end
-    wire ack_in_src = ack_sync_chain[STAGES-1];
-
-    reg overrun_r;
-    always @(posedge src_clk) begin
-        if (!src_reset_n) overrun_r <= 1'b0;
-        else              overrun_r <= src_valid && (src_toggle[0] != ack_in_src);
-    end
-    assign overrun = overrun_r;
-
 `ifdef FORMAL
    assign fv_src_data_reg = src_data_reg;
    assign fv_src_toggle   = src_toggle;
@@ -32,50 +32,11 @@ localparam COMB_WIDTH = 28;
 // adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
 // on 7-series regardless of speed grade.
 //
-// Active-high reset derived from reset_n (inverted and REGISTERED).
+// Active-high reset derived from reset_n (inverted).
 // CEP (clock enable for P register) gated by data_valid.
-//
-// ----------------------------------------------------------------------------
-// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
-// ----------------------------------------------------------------------------
-// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
-// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
-// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
-// plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
-// Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
-// period. Timing failed by 626 ps on the 400 MHz domain.
-//
-// Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
-// Vivado treats max_fanout on a REG (not a wire) as authoritative and
-// replicates the register into N copies, each placed near its ≈50 loads.
-// Invariants preserved:
-//   I1 (correctness):       reset_h is still active-high, equals ~reset_n
-//                           after one clk edge; CIC reset is a RECEIVER-side
-//                           synchronizer anyway (driven by reset_n_400m which
-//                           is already sync'd in the parent DDC), so adding
-//                           one more clk cycle of latency is safe.
-//   I2 (glitch-free):       Registered output => inherently glitch-free,
-//                           feeding DSP48E1 RST pins (which are synchronous
-//                           to CLK, so they capture on the same edge anyway).
-//   I3 (power-up safety):   reset_h is NOT async-reset itself. On power-up,
-//                           FDRE INIT=0 starts reset_h LOW. First clk edge
-//                           samples ~reset_n which is LOW on power-up (the
-//                           parent DDC holds reset_n_400m low until the 2-
-//                           stage synchronizer releases), so reset_h goes
-//                           HIGH on cycle 1 and all DSPs see reset during
-//                           the following cycles. System is held in reset
-//                           for enough cycles that any initial register
-//                           state garbage is overwritten. ✅
-//   I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
-//                           goes HIGH. Downstream DSPs come out of reset on
-//                           the next clk edge after that. Total latency
-//                           from system reset release to first valid sample:
-//                           2 (sync chain) + 1 (reset_h reg) + 1 (first
-//                           DSP output) = 4 cycles at 400 MHz = 10 ns.
-//                           Negligible vs system reset assertion duration.
-// ----------------------------------------------------------------------------
-(* max_fanout = 25 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
-always @(posedge clk) reset_h <= ~reset_n;
+// ============================================================================
+
+wire reset_h = ~reset_n;  // active-high reset for DSP48E1 RSTP

 // Sign-extended input for integrator_0 C port (48-bit)
 wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -738,11 +699,10 @@ initial begin
 end

 // Decimation control + monitoring (integrators are now DSP48E1 instances)
-// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
-// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
-// DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
+// Sync reset: enables FDRE inference for better timing at 400 MHz.
+// Reset is already synchronous to clk via reset synchronizer in parent module.
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
        integrator_sampled <= 0;
        decimation_counter <= 0;
        data_valid_delayed <= 0;
@@ -795,9 +755,9 @@ always @(posedge clk) begin
 end

 // Pipeline the valid signal for comb section
-// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
+// Sync reset: matches decimation control block reset style.
 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
        data_valid_comb <= 0;
        data_valid_comb_pipe <= 0;
        data_valid_comb_0_out <= 0;
@@ -832,7 +792,7 @@ end
 //   - Each stage: comb[i] = comb[i-1] - comb_delay[i][last]

 always @(posedge clk) begin
-    if (reset_h) begin
+    if (!reset_n) begin
        for (i = 0; i < STAGES; i = i + 1) begin
            comb[i] <= 0;
            for (j = 0; j < COMB_DELAY; j = j + 1) begin
@@ -33,10 +33,10 @@
 # (one period) to ensure the tools verify the transfer fits within one cycle
 # without over-constraining with full inter-clock setup/hold analysis.
 set_max_delay -datapath_only -from [get_clocks adc_dco_p] \
-    -to [get_clocks clk_mmcm_out0] 2.700
+    -to [get_clocks clk_mmcm_out0] 2.500

 set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
-    -to [get_clocks adc_dco_p] 2.700
+    -to [get_clocks adc_dco_p] 2.500

 # --------------------------------------------------------------------------
 # CDC: MMCM output domain ↔ other clock domains
@@ -47,12 +47,8 @@ set_max_delay -datapath_only -from [get_clocks clk_mmcm_out0] \
 set_false_path -from [get_clocks clk_100m] -to [get_clocks clk_mmcm_out0]
 set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_100m]

-# Audit F-0.6: the USB-domain clock name differs per board
-# (50T: ft_clkout, 200T: ft601_clk_in). XDC files only support a
-# restricted Tcl subset — `foreach`/`unset` trigger CRITICAL WARNING
-# [Designutils 20-1307]. The clk_mmcm_out0 ↔ USB-clock false paths
-# are declared in the per-board XDC (xc7a50t_ftg256.xdc and
-# xc7a200t_fbg484.xdc) where the USB clock name is already known.
+set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
+set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]

 set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks clk_120m_dac]
 set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
@@ -63,10 +59,7 @@ set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks clk_mmcm_out0]
 # LOCKED is not a valid timing startpoint (it's a combinational output of the
 # MMCM primitive). Use -through instead of -from to waive all paths that pass
 # through the LOCKED net. This avoids the CRITICAL WARNING from Build 19/20.
-# Audit F-0.7: the literal hierarchical path was missing the `u_core/`
-# prefix and silently matched no pins. Use a hierarchical wildcard to
-# catch the MMCM LOCKED pin regardless of wrapper hierarchy.
-set_false_path -through [get_pins -hierarchical -filter {REF_PIN_NAME == LOCKED}]
+set_false_path -through [get_pins rx_inst/adc/mmcm_inst/mmcm_adc_400m/LOCKED]

 # --------------------------------------------------------------------------
 # Hold waiver for source-synchronous ADC capture (BUFIO-clocked IDDR)
@@ -89,19 +82,14 @@ set_false_path -through [get_pins -hierarchical -filter {REF_PIN_NAME == LOCKED}
 #
 # Waiving hold on these 8 paths (adc_d_p[0..7] → IDDR) is standard practice
 # for source-synchronous LVDS ADC interfaces using BUFIO capture.
-# adc_or_p (AD9484 overrange, audit F-0.1) shares the same IBUFDS→BUFIO
-# source-synchronous capture topology as adc_d_p[*] — same ~1.9 ns STA hold
-# violation for the same reason (BUFIO clock insertion ~4 ns vs data IBUFDS
-# ~0.9 ns), resolved by the same external-timing argument.
-set_false_path -hold -from [get_ports {adc_d_p[*] adc_or_p}] -to [get_clocks adc_dco_p]
+set_false_path -hold -from [get_ports {adc_d_p[*]}] -to [get_clocks adc_dco_p]

 # --------------------------------------------------------------------------
 # Timing margin for 400 MHz critical paths
 # --------------------------------------------------------------------------
 # Extra setup uncertainty forces Vivado to leave margin for temperature/voltage/
-# aging variation. 150 ps absolute covers the built-in jitter-based value
-# (~53 ps) plus ~100 ps temperature/voltage/aging guardband.
-# NOTE: Vivado's set_clock_uncertainty does NOT accept -add; prior use of
-# -add 0.100 was silently rejected as a CRITICAL WARNING, so no guardband
-# was applied. Use an absolute value. (audit finding F-0.8)
-set_clock_uncertainty -setup 0.150 [get_clocks clk_mmcm_out0]
+# aging variation. Reduced from 200 ps to 100 ps after NCO→mixer pipeline
+# register fix eliminated the dominant timing bottleneck (WNS went from +0.002ns
+# to comfortable margin). 100 ps still provides ~4% guardband on the 2.5ns period.
+# This is additive to the existing jitter-based uncertainty (~53 ps).
+set_clock_uncertainty -setup -add 0.100 [get_clocks clk_mmcm_out0]
@@ -134,22 +134,6 @@ set_property IOSTANDARD LVDS_25 [get_ports {adc_d_p[*]}]
 set_property IOSTANDARD LVDS_25 [get_ports {adc_d_n[*]}]
 set_property DIFF_TERM TRUE [get_ports {adc_d_p[*]}]

-# --------------------------------------------------------------------------
-# Audit F-0.1: AD9484 OR (overrange) LVDS pair
-# The 50T main board schematic routes ADC_OR_P/N to bank-14 pins M6/N6 on
-# xc7a50t-ftg256. The 200T dev-board schematic has NOT been checked yet;
-# adc_or_p/n are declared as top-level ports so the 50T build anchors them
-# cleanly, but the 200T anchor below is a TODO placeholder — synth/impl will
-# error on unplaced IO until the 200T schematic is verified and the PACKAGE_PIN
-# values are set. IOSTANDARD/DIFF_TERM properties stay as-is (same class as
-# adc_d_p).
-# --------------------------------------------------------------------------
-set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
-set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
-# TODO(F-0.1): set_property PACKAGE_PIN <?> [get_ports {adc_or_p}] after 200T schematic audit
-# TODO(F-0.1): set_property PACKAGE_PIN <?> [get_ports {adc_or_n}] after 200T schematic audit
-
 # ADC Power Down — single-ended, Bank 14 (LVCMOS25 matches bank VCCO)
 # Pin: P20 = IO_0_14
 set_property PACKAGE_PIN P20 [get_ports {adc_pwdn}]
@@ -637,10 +621,6 @@ set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_120m_dac]
 set_false_path -from [get_clocks adc_dco_p] -to [get_clocks ft601_clk_in]
 set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks adc_dco_p]

-# MMCM 400 MHz domain ↔ FT601 USB clock (see adc_clk_mmcm.xdc for rationale)
-set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft601_clk_in]
-set_false_path -from [get_clocks ft601_clk_in] -to [get_clocks clk_mmcm_out0]
-
 # Generated clock cross-domain paths:
 # dac_clk_fwd and ft601_clk_fwd are generated from their respective source
 # clocks. Vivado automatically inherits the source clock false paths for
@@ -107,15 +107,8 @@ set_property PACKAGE_PIN C4 [get_ports {ft_clkout}]
 set_property IOSTANDARD LVCMOS33 [get_ports {ft_clkout}]
 create_clock -name ft_clkout -period 16.667 [get_ports {ft_clkout}]
 set_input_jitter [get_clocks ft_clkout] 0.2
-# N-type MRCC pin requires dedicated route override (Place 30-876).
-# Audit F-0.4: the literal net name `ft_clkout_IBUF` exists post-synth but
-# the XDC scan happens before synthesis, when the IBUF net does not yet
-# exist — Vivado reported `No nets matched 'ft_clkout_IBUF'` + CRITICAL
-# WARNING. Use -hierarchical -filter + -quiet so the constraint matches
-# post-synth without warning during pre-synth XDC scan. The TCL duplicate
-# at scripts/50t/build_50t.tcl:119 remains as belt-and-suspenders.
-set_property -quiet CLOCK_DEDICATED_ROUTE FALSE \
-    [get_nets -quiet -hierarchical -filter {NAME =~ *ft_clkout_IBUF}]
+# N-type MRCC pin requires dedicated route override (Place 30-876)
+set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {ft_clkout_IBUF}]

 # ============================================================================
 # RESET (Active-Low)
@@ -290,22 +283,6 @@ set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_d_p[*]}]
 set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_d_p[*]}] -add_delay
 set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_d_p[*]}] -add_delay

-# --------------------------------------------------------------------------
-# Audit F-0.1: AD9484 OR (overrange) LVDS pair (Bank 14)
-# Schematic RADAR_Main_Board.sch: ADC_OR_P → U42 IO_L19P_T3_A10_D26_14 (M6)
-#                                  ADC_OR_N → U42 IO_L19N_T3_A09_D25_VREF_14 (N6)
-# DDR-sourced by adc_dco_p, same timing class as adc_d_p[*].
-# --------------------------------------------------------------------------
-set_property PACKAGE_PIN M6 [get_ports {adc_or_p}]
-set_property PACKAGE_PIN N6 [get_ports {adc_or_n}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_or_p}]
-set_property IOSTANDARD LVDS_25 [get_ports {adc_or_n}]
-set_property DIFF_TERM TRUE [get_ports {adc_or_p}]
-set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 [get_ports {adc_or_p}]
-set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 [get_ports {adc_or_p}]
-set_input_delay -clock [get_clocks adc_dco_p] -max 1.0 -clock_fall [get_ports {adc_or_p}] -add_delay
-set_input_delay -clock [get_clocks adc_dco_p] -min 0.2 -clock_fall [get_ports {adc_or_p}] -add_delay
-
 # ============================================================================
 # FT2232H USB 2.0 INTERFACE (Bank 35, VCCO=3.3V)
 # ============================================================================
@@ -359,46 +336,40 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
 # --------------------------------------------------------------------------
 # FT2232H Source-Synchronous Timing Constraints
 # --------------------------------------------------------------------------
-# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns).
-# Values per FTDI TN_167 "FT2232H Synchronous FIFO Bus Bridge" — verify
-# against the exact app-note revision before shipping.
+# FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns):
 #
-# FPGA Read Path (FT2232H drives data/RXF#/TXE#, FPGA samples on CLKOUT↑):
-#   - t_co  (CLKOUT↑ → data valid)   max = 10.0 ns
-#   - t_coh (CLKOUT↑ → data hold)    min = 0.5 ns
-#   - set_input_delay -max = t_co,  -min = t_coh
+# FPGA Read Path (FT2232H drives data, FPGA samples):
+#   - Data valid before CLKOUT rising edge: t_vr(max) = 7.0 ns
+#   - Data hold after CLKOUT rising edge:   t_hr(min) = 0.0 ns
+#   - Input delay max = period - t_vr = 16.667 - 7.0 = 9.667 ns
+#   - Input delay min = t_hr = 0.0 ns
 #
-# FPGA Write Path (FPGA drives data/WR#/RD#/OE#, FT2232H samples on CLKOUT↑):
-#   - t_su  (data setup before CLKOUT↑)  min = 3.5 ns  (NOT 5 ns — prior
-#           constraint used a synthetic period-based back-calculation)
-#   - t_h   (data hold after CLKOUT↑)    min = 1.0 ns  (NOT 0 — a 0 ns hold
-#           constraint produced no hold check at all)
-#   - set_output_delay -max = t_su, -min = -t_h (Vivado convention)
-#
-# Audit F-2026-04-20 Option B: the previous output_delay = 11.667 ns
-# (= period − 5) over-constrained launch by ~8 ns vs the actual datasheet
-# figure. Relaxing to 3.5 ns matches the chip's real setup requirement.
+# FPGA Write Path (FPGA drives data, FT2232H samples):
+#   - Data setup before next CLKOUT rising: t_su = 5.0 ns
+#   - Data hold after CLKOUT rising:        t_hd = 0.0 ns
+#   - Output delay max = period - t_su = 16.667 - 5.0 = 11.667 ns
+#   - Output delay min = t_hd = 0.0 ns
 # --------------------------------------------------------------------------

 # Input delays: FT2232H → FPGA (data bus and status signals)
-set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_data[*]}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_data[*]}]
-set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_rxf_n}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_rxf_n}]
-set_input_delay -clock [get_clocks ft_clkout] -max 10.0 [get_ports {ft_txe_n}]
-set_input_delay -clock [get_clocks ft_clkout] -min 0.5  [get_ports {ft_txe_n}]
+set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_data[*]}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_data[*]}]
+set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_rxf_n}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_rxf_n}]
+set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_txe_n}]
+set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_txe_n}]

 # Output delays: FPGA → FT2232H (control strobes and data bus when writing)
-set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_data[*]}]
-set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_data[*]}]
-set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_rd_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_rd_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_wr_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_wr_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_oe_n}]
-set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_oe_n}]
-set_output_delay -clock [get_clocks ft_clkout] -max 3.5  [get_ports {ft_siwu}]
-set_output_delay -clock [get_clocks ft_clkout] -min -1.0 [get_ports {ft_siwu}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_data[*]}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_data[*]}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_rd_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_rd_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_wr_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_wr_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_oe_n}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_oe_n}]
+set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_siwu}]
+set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_siwu}]

 # ============================================================================
 # STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
@@ -437,17 +408,7 @@ set_false_path -from [get_ports {stm32_mixers_enable}]
 #   - Reset deassertion order is not functionally critical — all registers
 #     come out of reset within a few cycles of each other
 # --------------------------------------------------------------------------
-# Audit F-0.5: the literal cell name `reset_sync_reg[*]` does not match any
-# cell in the post-synth netlist. The actual sync regs are
-# `u_core/reset_sync_reg[0..1]`, `u_core/rx_inst/ddc/reset_sync_400m_reg[*]`,
-# `u_core/gen_ft2232h.usb_inst/ft_reset_sync_reg[*]`, and peers under
-# `u_core/reset_sync_120m_reg[*]`, `u_core/reset_sync_ft601_reg[*]`,
-# `u_core/rx_inst/adc/reset_sync_400m_reg[*]`. The waiver below covers all
-# of them by matching any register whose name contains `reset_sync`.
-# Without this, STA runs recovery/removal on the fanout of each sync-chain
-# output register (up to ~1000 loads pre-PR#113 replication).
-set_false_path -from [get_cells -hierarchical -filter {NAME =~ *reset_sync*_reg*}] \
-               -to   [get_pins  -hierarchical -filter {REF_PIN_NAME == CLR || REF_PIN_NAME == PRE}]
+set_false_path -from [get_cells reset_sync_reg[*]] -to [get_pins -filter {REF_PIN_NAME == CLR} -of_objects [get_cells -hierarchical -filter {PRIMITIVE_TYPE =~ REGISTER.*.*}]]

 # --------------------------------------------------------------------------
 # Clock Domain Crossing false paths
@@ -469,10 +430,6 @@ set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_100m]
 set_false_path -from [get_clocks clk_120m_dac] -to [get_clocks ft_clkout]
 set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_120m_dac]

-# MMCM 400 MHz domain ↔ FT2232H USB clock (see adc_clk_mmcm.xdc for rationale)
-set_false_path -from [get_clocks clk_mmcm_out0] -to [get_clocks ft_clkout]
-set_false_path -from [get_clocks ft_clkout] -to [get_clocks clk_mmcm_out0]
-
 # ============================================================================
 # PHYSICAL CONSTRAINTS
 # ============================================================================
@@ -25,10 +25,7 @@ module ddc_400m_enhanced (
    input wire reset_monitors,
    output wire [31:0] debug_sample_count,
    output wire [17:0] debug_internal_i,
-    output wire [17:0] debug_internal_q,
-    // Audit F-1.2: sticky CIC→FIR CDC overrun flag (clk_400m domain). Goes
-    // high on the first dropped sample and stays high until reset_monitors.
-    output wire cdc_cic_fir_overrun
+    output wire [17:0] debug_internal_q
 );

 // Parameters for numerical precision
@@ -56,6 +53,46 @@ reg [2:0] saturation_count;
 reg overflow_detected;
 reg [7:0] error_counter;

+// ============================================================================
+// 400 MHz Reset Synchronizer
+//
+// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
+// Using it directly as an async reset in the 400 MHz domain causes the reset
+// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
+// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
+// domain, requiring 18.243ns of routing (WNS = -18.081ns).
+//
+// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
+// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
+// path from reset_n to all 400 MHz registers). Reset deassertion is
+// synchronized to clk_400m rising edge, preventing metastability.
+//
+// All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
+// All 100 MHz submodules (FIR, output stage) continue using reset_n directly
+// (already synchronized to 100 MHz at radar_system_top level).
+// ============================================================================
+(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
+(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
+
+// Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
+(* max_fanout = 50 *) reg reset_400m;
+
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
+        reset_sync_400m <= 2'b00;
+        reset_400m      <= 1'b1;
+    end else begin
+        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
+        reset_400m      <= ~reset_sync_400m[1];
+    end
+end
+
+// CDC synchronization for control signals (2-stage synchronizers)
+(* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
+(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
+wire mixers_enable_sync;
+wire force_saturation_sync;
+
 // Debug monitoring signals
 reg [31:0] sample_counter;
 wire signed [17:0] debug_mixed_i_trunc;
@@ -93,6 +130,8 @@ reg baseband_valid_reg;
 wire [7:0] phase_dither_bits;
 reg [31:0] phase_inc_dithered;

+
+
 // ============================================================================
 // Debug Signal Assignments
 // ============================================================================
@@ -103,68 +142,17 @@ assign debug_mixed_i_trunc = mixed_i[25:8];
 assign debug_mixed_q_trunc = mixed_q[25:8];

 // ============================================================================
-// 400 MHz Reset Synchronizer
-//
-// reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
-// Using it directly as an async reset in the 400 MHz domain causes the reset
-// deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
-// has its output fanning out to 1156 registers across the FPGA in the 400 MHz
-// domain, requiring 18.243ns of routing (WNS = -18.081ns).
-//
-// Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
-// 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
-// path from reset_n to all 400 MHz registers). Reset deassertion is
-//
-// reset_400m   : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
-//                This is THE signal fed to every synchronous 400 MHz FDRE
-//                and every DSP48E1 RST pin in this module and its children
-//                (NCO, CIC, LFSR). Vivado replicates the register (~14
-//                copies) so each replica drives ≈50 loads regionally,
-//                eliminating the single-LUT1 / 702-load net that caused
-//                WNS=-0.626 ns in Build N.
-//
-// System-level invariants preserved:
-//   I1  Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
-//       (2 sync + 1 replicated-reg fanout).  At 400 MHz = 7.5 ns << any
-//       system-level reset assertion duration.
-//   I2  Reset de-assertion is always synchronous to clk_400m (via
-//       reset_sync_400m), never glitches.
-//   I3  DSP48E1 RST pins are all fed from Q of a register — glitch-free.
-//   I4  No new CDC introduced: reset_400m is entirely in clk_400m domain.
-//   I5  Power-up: reset_n is asserted externally and mmcm_locked is low;
-//       reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
-//       FDREs stay cleared. Safe.
+// Clock Domain Crossing for Control Signals (2-stage synchronizers)
 // ============================================================================
-(* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
-(* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
-
-// Active-high replicated reset for all synchronous 400 MHz consumers
-(* max_fanout = 50 *) reg reset_400m = 1'b1;
-
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n) begin
-        reset_sync_400m <= 2'b00;
-        reset_400m      <= 1'b1;
-    end else begin
-        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
-        reset_400m      <= ~reset_sync_400m[1];
-    end
-end
-
-// CDC synchronization for control signals (2-stage synchronizers).
-// Audit F-1.3: the mixers_enable synchronizer was dead — its _sync output
-// was never consumed (the NCO phase_valid uses the raw port), and the only
-// caller (radar_receiver_final.v) ties the port to 1'b1. Removed.
-(* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
-wire force_saturation_sync;
+assign mixers_enable_sync = mixers_enable_sync_chain[1];
 assign force_saturation_sync = force_saturation_sync_chain[1];

-// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
-// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
+        mixers_enable_sync_chain <= 2'b00;
        force_saturation_sync_chain <= 2'b00;
    end else begin
+        mixers_enable_sync_chain <= {mixers_enable_sync_chain[0], mixers_enable};
        force_saturation_sync_chain <= {force_saturation_sync_chain[0], force_saturation};
    end
 end
@@ -172,8 +160,8 @@ end
 // ============================================================================
 // Sample Counter and Debug Monitoring
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_400m || reset_monitors) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m || reset_monitors) begin
        sample_counter <= 0;
        error_counter <= 0;
    end else if (adc_data_valid_i && adc_data_valid_q ) begin
@@ -201,8 +189,8 @@ lfsr_dither_enhanced #(
 localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;

 // Apply dithering to reduce spurious tones (registered for 400 MHz timing)
-always @(posedge clk_400m) begin
-    if (reset_400m)
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m)
        phase_inc_dithered <= PHASE_INC_120MHZ;
    else
        phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
@@ -241,8 +229,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
                      {1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;

 // Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        dsp_valid_pipe <= 5'b00000;
    end else begin
        dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -258,8 +246,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal;  // Mod
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg;            // Models PREG

 // Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        cos_nco_pipe <= 0;
        sin_nco_pipe <= 0;
    end else begin
@@ -269,8 +257,8 @@ always @(posedge clk_400m) begin
 end

 // Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        adc_signed_reg <= 0;
        cos_pipe_reg <= 0;
        sin_pipe_reg <= 0;
@@ -282,8 +270,8 @@ always @(posedge clk_400m) begin
 end

 // Stage 2: MREG equivalent
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mult_i_internal <= 0;
        mult_q_internal <= 0;
    end else begin
@@ -293,8 +281,8 @@ always @(posedge clk_400m) begin
 end

 // Stage 3: PREG equivalent
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mult_i_reg <= 0;
        mult_q_reg <= 0;
    end else begin
@@ -304,8 +292,8 @@ always @(posedge clk_400m) begin
 end

 // Stage 4: Post-DSP retiming register (matches synthesis path)
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mult_i_retimed <= 0;
        mult_q_retimed <= 0;
    end else begin
@@ -323,8 +311,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
 // (1.505ns routing observed in Build 26). These fabric registers are placed
 // near the DSP by the placer, splitting the route into two shorter segments.
 // DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        cos_nco_pipe <= 0;
        sin_nco_pipe <= 0;
    end else begin
@@ -341,10 +329,11 @@ DSP48E1 #(
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_SIMD("ONE48"),
+    // Pipeline register attributes — all enabled for max timing
    .AREG(1),
    .BREG(1),
    .MREG(1),
-    .PREG(1),
+    .PREG(1),           // P register enabled — absorbs CLK→P delay for timing closure
    .ADREG(0),
    .ACASCREG(1),
    .BCASCREG(1),
@@ -355,6 +344,7 @@ DSP48E1 #(
    .DREG(0),
    .INMODEREG(0),
    .OPMODEREG(0),
+    // Pattern detector (unused)
    .AUTORESET_PATDET("NO_RESET"),
    .MASK(48'h3fffffffffff),
    .PATTERN(48'h000000000000),
@@ -506,8 +496,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
 // Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
 // Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
 // the 2.500ns clock period at slow process corner
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mult_i_retimed <= 0;
        mult_q_retimed <= 0;
    end else begin
@@ -523,8 +513,8 @@ end
 // force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
 // polluting the critical input path with extra logic
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_400m) begin
+always @(posedge clk_400m or negedge reset_n_400m) begin
+    if (!reset_n_400m) begin
        mixed_i <= 0;
        mixed_q <= 0;
        mixed_valid <= 0;
@@ -602,9 +592,6 @@ wire fir_in_valid_i, fir_in_valid_q;
 wire fir_valid_i, fir_valid_q;
 wire fir_i_ready, fir_q_ready;
 wire [17:0] fir_d_in_i, fir_d_in_q; 
-// Audit F-1.2: per-lane CIC→FIR CDC overrun pulses (clk_400m domain)
-wire cdc_fir_i_overrun;
-wire cdc_fir_q_overrun;

 cdc_adc_to_processing #(
    .WIDTH(18),
@@ -617,8 +604,7 @@ cdc_adc_to_processing #(
    .src_data(cic_i_out),
    .src_valid(cic_valid_i),
    .dst_data(fir_d_in_i),
-    .dst_valid(fir_in_valid_i),
-    .overrun(cdc_fir_i_overrun)
+    .dst_valid(fir_in_valid_i)
 );

 cdc_adc_to_processing #(
@@ -632,30 +618,13 @@ cdc_adc_to_processing #(
    .src_data(cic_q_out),
    .src_valid(cic_valid_q),
    .dst_data(fir_d_in_q),
-    .dst_valid(fir_in_valid_q),
-    .overrun(cdc_fir_q_overrun)
+    .dst_valid(fir_in_valid_q)
 );

-// Audit F-1.2: sticky-latch the two per-lane overrun pulses in the 400 MHz
-// domain and expose a single module-level flag. Cleared only by
-// reset_monitors (or reset_n via reset_400m), matching the other DDC
-// diagnostic latches (overflow/saturation).
-reg  cdc_cic_fir_overrun_sticky;
-always @(posedge clk_400m) begin
-    if (reset_400m || reset_monitors)                         cdc_cic_fir_overrun_sticky <= 1'b0;
-    else if (cdc_fir_i_overrun || cdc_fir_q_overrun)          cdc_cic_fir_overrun_sticky <= 1'b1;
-end
-assign cdc_cic_fir_overrun = cdc_cic_fir_overrun_sticky;
-
 // ============================================================================
 // FIR Filter Instances
 // ============================================================================

-// FIR overflow flags (audit F-6.2 — previously dangling, now OR'd into
-// module-level filter_overflow so the receiver can see FIR arithmetic overflow)
-wire fir_i_overflow;
-wire fir_q_overflow;
-
 // FIR I channel
 fir_lowpass_parallel_enhanced fir_i_inst (
    .clk(clk_100m),
@@ -665,7 +634,7 @@ fir_lowpass_parallel_enhanced fir_i_inst (
    .data_out(fir_i_out),
    .data_out_valid(fir_valid_i),
    .fir_ready(fir_i_ready),
-    .filter_overflow(fir_i_overflow)
+    .filter_overflow()
 );

 // FIR Q channel  
@@ -677,11 +646,10 @@ fir_lowpass_parallel_enhanced fir_q_inst (
    .data_out(fir_q_out),
    .data_out_valid(fir_valid_q),
    .fir_ready(fir_q_ready),
-    .filter_overflow(fir_q_overflow)
+    .filter_overflow()
 );

 assign fir_valid = fir_valid_i & fir_valid_q;
-assign filter_overflow = fir_i_overflow | fir_q_overflow;

 // ============================================================================
 // Enhanced Output Stage
@@ -791,17 +759,8 @@ generate
    end
 endgenerate

-// ============================================================================
-// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
-// See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
-// by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
-// sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
-// ============================================================================
-(* max_fanout = 50 *) reg reset_h = 1'b1;
-always @(posedge clk) reset_h <= ~reset_n;
-
-always @(posedge clk) begin
-    if (reset_h) begin
+always @(posedge clk or negedge reset_n) begin
+    if (!reset_n) begin
        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
        cycle_counter <= 0;
        lock_detected <= 0;
@@ -58,12 +58,7 @@ module mti_canceller #(
    input wire mti_enable,   // 1=MTI active, 0=pass-through

    // ========== STATUS ==========
-    output reg mti_first_chirp, // 1 during first chirp (output muted)
-
-    // Audit F-6.3: count of saturated samples since last reset. Saturation
-    // here produces spurious Doppler harmonics (phantom targets at ±fs/2)
-    // and was previously invisible to the MCU. Saturates at 0xFF.
-    output reg [7:0] mti_saturation_count
+    output reg mti_first_chirp  // 1 during first chirp (output muted)
 );

 // ============================================================================
@@ -109,11 +104,6 @@ assign diff_q_sat = (diff_q_full > $signed({{2{1'b0}}, {(DATA_WIDTH-1){1'b1}}}))
                  ? $signed({1'b1, {(DATA_WIDTH-1){1'b0}}})
                  : diff_q_full[DATA_WIDTH-1:0];

-// Saturation detection (F-6.3): the top two bits of the DATA_WIDTH+1 signed
-// difference disagree iff the value exceeds the DATA_WIDTH signed range.
-wire diff_i_overflow = (diff_i_full[DATA_WIDTH] != diff_i_full[DATA_WIDTH-1]);
-wire diff_q_overflow = (diff_q_full[DATA_WIDTH] != diff_q_full[DATA_WIDTH-1]);
-
 // ============================================================================
 // MAIN LOGIC
 // ============================================================================
@@ -125,14 +115,7 @@ always @(posedge clk or negedge reset_n) begin
        range_bin_out   <= 6'd0;
        has_previous    <= 1'b0;
        mti_first_chirp <= 1'b1;
-        mti_saturation_count <= 8'd0;
    end else begin
-        // Count saturated MTI-active samples (F-6.3). Clamp at 0xFF.
-        if (range_valid_in && mti_enable && has_previous
-            && (diff_i_overflow || diff_q_overflow)
-            && (mti_saturation_count != 8'hFF)) begin
-            mti_saturation_count <= mti_saturation_count + 8'd1;
-        end
        // Default: no valid output
        range_valid_out <= 1'b0;

@@ -59,25 +59,6 @@ reg [1:0] quadrant_reg2;                 // Pass-through for Stage 5 MUX
 // Valid pipeline: tracks 6-stage latency
 reg [5:0] valid_pipe;

-// ============================================================================
-// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
-// ============================================================================
-// reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
-// Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
-// regionally, avoiding the single-LUT1 / 702-load net that caused timing
-// failure in Build N. It feeds:
-//   - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
-//   - All pipeline-stage fabric FDREs (synchronous reset)
-// Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
-//   I1 correctness:      reset_h == ~reset_n one cycle later
-//   I2 glitch-free:      registered output
-//   I3 power-up safe:    INIT=1'b1 holds all downstream in reset until first
-//                        valid clock edge; reset_n is low on power-up anyway
-//   I4 de-assert lat.:   +1 cycle vs. direct async; negligible at 400 MHz
-// ============================================================================
-(* max_fanout = 50 *) reg reset_h = 1'b1;
-always @(posedge clk_400m) reset_h <= ~reset_n;
-
 // Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
 wire [7:0] lut_address = phase_with_offset[31:24];

@@ -154,8 +135,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
 // Stage 2: phase_with_offset adds phase offset
 reg [31:0] phase_accumulator;

-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        phase_accumulator <= 32'h00000000;
        phase_accum_reg   <= 32'h00000000;
        phase_with_offset <= 32'h00000000;
@@ -209,8 +190,8 @@ DSP48E1 #(
    .RSTA(1'b0),
    .RSTB(1'b0),
    .RSTM(1'b0),
-    .RSTP(reset_h),              // Reset P register (phase accumulator) — registered, max_fanout=50
-    .RSTC(reset_h),              // Reset C register (tuning word)       — registered, max_fanout=50
+    .RSTP(!reset_n),             // Reset P register (phase accumulator) on !reset_n
+    .RSTC(!reset_n),             // Reset C register (tuning word) on !reset_n
    .RSTALLCARRYIN(1'b0),
    .RSTALUMODE(1'b0),
    .RSTCTRL(1'b0),
@@ -264,8 +245,8 @@ DSP48E1 #(
 // Stage 1: Capture DSP48E1 P output into fabric register
 // Stage 2: Add phase offset to captured value
 // Split into two registered stages to break DSP48E1.P→CARRY4 critical path
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        phase_accum_reg   <= 32'h00000000;
        phase_with_offset <= 32'h00000000;
    end else if (phase_valid) begin
@@ -283,8 +264,8 @@ end
 //           Only 2 registers driven (lut_index_pipe + quadrant_pipe)
 //           Minimal fanout → short routes → easy timing
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        lut_index_pipe_sin <= 6'b000000;
        lut_index_pipe_cos <= 6'b000000;
        quadrant_pipe      <= 2'b00;
@@ -300,8 +281,8 @@ end
 //           Registered address → combinational LUT6 read → register
 //           Only 1 logic level (LUT6), trivial timing
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        sin_abs_reg <= 16'h0000;
        cos_abs_reg <= 16'h7FFF;
        quadrant_reg <= 2'b00;
@@ -317,8 +298,8 @@ end
 //          CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
 //          Also pass through abs values and quadrant for Stage 5
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        sin_neg_reg <= 16'h0000;
        cos_neg_reg <= -16'h7FFF;
        sin_abs_reg2 <= 16'h0000;
@@ -337,8 +318,8 @@ end
 // Stage 5: Quadrant sign application → final sin/cos output
 //          Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        sin_out <= 16'h0000;
        cos_out <= 16'h7FFF;
    end else if (valid_pipe[4]) begin
@@ -366,8 +347,8 @@ end
 // ============================================================================
 // Valid pipeline and dds_ready (6-stage latency)
 // ============================================================================
-always @(posedge clk_400m) begin
-    if (reset_h) begin
+always @(posedge clk_400m or negedge reset_n) begin
+    if (!reset_n) begin
        valid_pipe <= 6'b000000;
        dds_ready <= 1'b0;
    end else begin
@@ -9,9 +9,6 @@ module radar_receiver_final (
    input wire [7:0] adc_d_n,        // ADC Data N (LVDS)
    input wire adc_dco_p,            // Data Clock Output P (400MHz LVDS)
    input wire adc_dco_n,            // Data Clock Output N (400MHz LVDS)
-    // Audit F-0.1: AD9484 OR (overrange) LVDS pair
-    input wire adc_or_p,
-    input wire adc_or_n,
 	 output wire adc_pwdn,
    
    // Chirp counter from transmitter (for matched filter indexing)
@@ -77,28 +74,7 @@ module radar_receiver_final (
    // AGC status outputs (for status readback / STM32 outer loop)
    output wire [7:0]  agc_saturation_count, // Per-frame clipped sample count
    output wire [7:0]  agc_peak_magnitude,   // Per-frame peak (upper 8 bits)
-    output wire [3:0]  agc_current_gain,     // Effective gain_shift encoding
-
-    // DDC overflow diagnostics (audit F-6.1 — previously deleted at boundary).
-    // Not yet plumbed into the USB status packet (protocol contract is frozen);
-    // exposed here for gpio aggregation and ILA mark_debug visibility.
-    output wire        ddc_overflow_any,
-    output wire [2:0]  ddc_saturation_count,
-
-    // MTI 2-pulse canceller saturation count (audit F-6.3).
-    output wire [7:0]  mti_saturation_count_out,
-
-    // Range-bin decimator watchdog (audit F-6.4 — previously tied off
-    // with an ILA-only note). A high pulse here means the decimator
-    // FSM has not seen the expected number of input samples within
-    // its timeout window, i.e. the upstream FIR/CDC has stalled.
-    output wire        range_decim_watchdog,
-
-    // Audit F-1.2: sticky CIC→FIR CDC overrun flag. Asserts on the first
-    // silent sample drop between the 400 MHz CIC output and the 100 MHz
-    // FIR input; stays high until the next reset. OR'd into the GPIO
-    // diagnostic bit at the top level.
-    output wire        ddc_cic_fir_overrun
+    output wire [3:0]  agc_current_gain      // Effective gain_shift encoding
 );

 // ========== INTERNAL SIGNALS ==========
@@ -209,43 +185,18 @@ wire adc_valid;            // Data valid signal
 // ADC power-down control (directly tie low = ADC always on)
 assign adc_pwdn = 1'b0;

-wire adc_overrange_400m;
 ad9484_interface_400m adc (
 	.adc_d_p(adc_d_p),
 	.adc_d_n(adc_d_n),
 	.adc_dco_p(adc_dco_p),
 	.adc_dco_n(adc_dco_n),
-	.adc_or_p(adc_or_p),
-	.adc_or_n(adc_or_n),
 	.sys_clk(clk),
 	.reset_n(reset_n),
 	.adc_data_400m(adc_data_cmos),
 	.adc_data_valid_400m(adc_valid),
-	.adc_dco_bufg(clk_400m),
-	.adc_overrange_400m(adc_overrange_400m)
+	.adc_dco_bufg(clk_400m)
 );

-// Audit F-0.1: stickify the 400 MHz OR pulse, then CDC to clk_100m via 2FF.
-// Same reasoning as ddc_cic_fir_overrun: single-bit, low→high-only once
-// latched, so a 2FF sync is sufficient for a GPIO-class diagnostic. Cleared
-// only by global reset_n.
-reg adc_overrange_sticky_400m;
-always @(posedge clk_400m or negedge reset_n) begin
-    if (!reset_n)
-        adc_overrange_sticky_400m <= 1'b0;
-    else if (adc_overrange_400m)
-        adc_overrange_sticky_400m <= 1'b1;
-end
-
-(* ASYNC_REG = "TRUE" *) reg [1:0] adc_overrange_sync_100m;
-always @(posedge clk or negedge reset_n) begin
-    if (!reset_n)
-        adc_overrange_sync_100m <= 2'b00;
-    else
-        adc_overrange_sync_100m <= {adc_overrange_sync_100m[0], adc_overrange_sticky_400m};
-end
-wire adc_overrange_100m = adc_overrange_sync_100m[1];
-
 // NOTE: The cdc_adc_to_processing instance that was here used src_clk=dst_clk=clk_400m
 // (same clock domain — no crossing). Gray-code CDC on same-clock with fast-changing
 // ADC data corrupts samples because Gray coding only guarantees safe transfer of
@@ -260,16 +211,6 @@ wire signed [17:0] ddc_out_q;
 wire ddc_valid_i;
 wire ddc_valid_q;

-// DDC diagnostic signals (audit F-6.1 — all outputs previously unconnected)
-wire [1:0] ddc_status_w;
-wire [7:0] ddc_diagnostics_w;
-wire       ddc_mixer_saturation;
-wire       ddc_filter_overflow;
-
-(* mark_debug = "true" *) wire ddc_mixer_saturation_dbg = ddc_mixer_saturation;
-(* mark_debug = "true" *) wire ddc_filter_overflow_dbg  = ddc_filter_overflow;
-(* mark_debug = "true" *) wire [7:0] ddc_diagnostics_dbg = ddc_diagnostics_w;
-
 ddc_400m_enhanced ddc(
    .clk_400m(clk_400m),           // 400MHz clock from ADC DCO
    .clk_100m(clk),           // 100MHz system clock //used by the 2 FIR
@@ -281,28 +222,9 @@ ddc_400m_enhanced ddc(
    .baseband_q(ddc_out_q), // Q output at 100MHz  
    .baseband_valid_i(ddc_valid_i),     // Valid at 100MHz
 	 .baseband_valid_q(ddc_valid_q),
-    .mixers_enable(1'b1),
-    // Diagnostics (audit F-6.1) — previously all unconnected
-    .ddc_status(ddc_status_w),
-    .ddc_diagnostics(ddc_diagnostics_w),
-    .mixer_saturation(ddc_mixer_saturation),
-    .filter_overflow(ddc_filter_overflow),
-    // Test/debug inputs — explicit tie-low (were floating)
-    .test_mode(2'b00),
-    .test_phase_inc(16'h0000),
-    .force_saturation(1'b0),
-    .reset_monitors(1'b0),
-    .debug_sample_count(),
-    .debug_internal_i(),
-    .debug_internal_q(),
-    .cdc_cic_fir_overrun(ddc_cic_fir_overrun)
+ 	 .mixers_enable(1'b1)
 );

-// Audit F-0.1: AD9484 overrange aggregated here so a single gpio_dig bit
-// covers DDC-internal saturation, FIR overflow, AND raw ADC clipping.
-assign ddc_overflow_any     = ddc_mixer_saturation | ddc_filter_overflow | adc_overrange_100m;
-assign ddc_saturation_count = ddc_diagnostics_w[7:5];
-
 ddc_input_interface ddc_if (
    .clk(clk),
    .reset_n(reset_n),
@@ -447,7 +369,7 @@ range_bin_decimator #(
    .range_bin_index(decimated_range_bin),
    .decimation_mode(2'b01),           // Peak detection mode
    .start_bin(10'd0),
-    .watchdog_timeout(range_decim_watchdog)  // Audit F-6.4 — plumbed out
+    .watchdog_timeout()                // Diagnostic — unconnected (monitored via ILA if needed)
 );

 // ========== MTI CANCELLER (Ground Clutter Removal) ==========
@@ -469,8 +391,7 @@ mti_canceller #(
    .range_valid_out(mti_range_valid),
    .range_bin_out(mti_range_bin),
    .mti_enable(host_mti_enable),
-    .mti_first_chirp(mti_first_chirp),
-    .mti_saturation_count(mti_saturation_count_out)
+    .mti_first_chirp(mti_first_chirp)
 );

 // ========== FRAME SYNC FROM TRANSMITTER ==========
@@ -67,9 +67,6 @@ module radar_system_top (
    input wire [7:0] adc_d_n,            // ADC Data N (LVDS)
    input wire adc_dco_p,                 // Data Clock Output P (400MHz LVDS)
    input wire adc_dco_n,                 // Data Clock Output N (400MHz LVDS)
-    // Audit F-0.1: AD9484 OR (overrange) LVDS pair
-    input wire adc_or_p,
-    input wire adc_or_n,
    output wire adc_pwdn,                  // ADC Power Down
    
    // ========== STM32 CONTROL INTERFACES ==========
@@ -201,19 +198,6 @@ wire [7:0]  rx_agc_saturation_count;
 wire [7:0]  rx_agc_peak_magnitude;
 wire [3:0]  rx_agc_current_gain;

-// DDC overflow diagnostics (audit F-6.1) — plumbed out of receiver so the
-// DDC mixer_saturation / filter_overflow ports are no longer deleted at
-// the boundary. Aggregated into gpio_dig5 alongside AGC saturation.
-wire        rx_ddc_overflow_any;
-wire [2:0]  rx_ddc_saturation_count;
-// MTI saturation count (audit F-6.3). OR'd into gpio_dig5 for MCU visibility.
-wire [7:0]  rx_mti_saturation_count;
-// Range-bin decimator watchdog (audit F-6.4). High = decimator stalled.
-wire        rx_range_decim_watchdog;
-// CIC→FIR CDC overrun sticky (audit F-1.2). High = at least one baseband
-// sample has been silently dropped between the 400 MHz CIC and 100 MHz FIR.
-wire        rx_ddc_cic_fir_overrun;
-
 // Data packing for USB
 wire [31:0] usb_range_profile;
 wire usb_range_valid;
@@ -529,8 +513,6 @@ radar_receiver_final rx_inst (
    .adc_d_n(adc_d_n),
    .adc_dco_p(adc_dco_p),
    .adc_dco_n(adc_dco_n),
-    .adc_or_p(adc_or_p),
-    .adc_or_n(adc_or_n),
    .adc_pwdn(adc_pwdn),
    
    // Doppler Outputs
@@ -580,15 +562,7 @@ radar_receiver_final rx_inst (
    // AGC status outputs
    .agc_saturation_count(rx_agc_saturation_count),
    .agc_peak_magnitude(rx_agc_peak_magnitude),
-    .agc_current_gain(rx_agc_current_gain),
-    // DDC overflow diagnostics (audit F-6.1)
-    .ddc_overflow_any(rx_ddc_overflow_any),
-    .ddc_saturation_count(rx_ddc_saturation_count),
-    // MTI saturation count (audit F-6.3)
-    .mti_saturation_count_out(rx_mti_saturation_count),
-    // Range-bin decimator watchdog (audit F-6.4)
-    .range_decim_watchdog(rx_range_decim_watchdog),
-    .ddc_cic_fir_overrun(rx_ddc_cic_fir_overrun)
+    .agc_current_gain(rx_agc_current_gain)
 );

 // ============================================================================
@@ -897,19 +871,6 @@ endgenerate
 // we simply sample them in clk_100m when the CDC'd pulse arrives.

 // Step 1: Toggle on cmd_valid pulse (ft601_clk domain)
-//
-// CDC INVARIANT (audit F-1.1): usb_cmd_opcode / usb_cmd_addr / usb_cmd_value
-// / usb_cmd_data MUST be driven to their final values BEFORE usb_cmd_valid
-// asserts, and held stable for at least (STAGES + 1) clk_100m cycles after
-// (i.e., until cmd_valid_100m has pulsed in the destination domain). These
-// buses cross from ft601_clk to clk_100m as quasi-static data, NOT through
-// a synchronizer — only the toggle bit above is CDC'd. If a future edit
-// moves the cmd_* register write to the SAME cycle as the toggle flip, or
-// drops the stability hold, the clk_100m sampler at the command decoder
-// will latch metastable bits and dispatch on a garbage opcode.
-// The source-side FSM in usb_data_interface_ft2232h.v / usb_data_interface.v
-// currently satisfies this by assigning the cmd_* buses several cycles
-// before pulsing cmd_valid and leaving them stable until the next command.
 reg cmd_valid_toggle_ft601;
 always @(posedge ft601_clk_buf or negedge sys_reset_ft601_n) begin
    if (!sys_reset_ft601_n)
@@ -1079,15 +1040,7 @@ assign system_status = status_reg;
 // DIG_6: AGC enable flag — mirrors host_agc_enable so STM32 outer-loop AGC
 //        tracks the FPGA register as single source of truth.
 // DIG_7: Reserved (tied low for future use).
-// gpio_dig5: "signal-chain clipped" — asserts on AGC saturation, DDC mixer/FIR
-// overflow, or MTI 2-pulse saturation. Audit F-6.1/F-6.3: these were all
-// previously invisible to the MCU.
-assign gpio_dig5 = (rx_agc_saturation_count != 8'd0)
-                 | rx_ddc_overflow_any
-                 | (rx_ddc_saturation_count != 3'd0)
-                 | (rx_mti_saturation_count != 8'd0)
-                 | rx_range_decim_watchdog    // audit F-6.4
-                 | rx_ddc_cic_fir_overrun;    // audit F-1.2
+assign gpio_dig5 = (rx_agc_saturation_count != 8'd0);
 assign gpio_dig6 = host_agc_enable;
 assign gpio_dig7 = 1'b0;

@@ -60,8 +60,6 @@ module radar_system_top_50t (
    input wire [7:0] adc_d_n,
    input wire adc_dco_p,
    input wire adc_dco_n,
-    input wire adc_or_p,
-    input wire adc_or_n,
    output wire adc_pwdn,

    // ===== STM32 Control (Bank 15: 3.3V) =====
@@ -173,8 +171,6 @@ module radar_system_top_50t (
        .adc_d_n                (adc_d_n),
        .adc_dco_p              (adc_dco_p),
        .adc_dco_n              (adc_dco_n),
-        .adc_or_p               (adc_or_p),
-        .adc_or_n               (adc_or_n),
        .adc_pwdn               (adc_pwdn),

        // ----- STM32 Control -----
@@ -19,10 +19,6 @@ module ad9484_interface_400m (
    input wire [7:0] adc_d_n,
    input wire adc_dco_p,
    input wire adc_dco_n,
-    // Audit F-0.1: AD9484 OR (overrange) LVDS pair — stub treats adc_or_p as
-    // the single-ended overrange flag, adc_or_n is ignored.
-    input wire adc_or_p,
-    input wire adc_or_n,

    // System Interface
    input wire sys_clk,
@@ -31,8 +27,7 @@ module ad9484_interface_400m (
    // Output at 400MHz domain
    output wire [7:0] adc_data_400m,
    output wire adc_data_valid_400m,
-    output wire adc_dco_bufg,
-    output wire adc_overrange_400m
+    output wire adc_dco_bufg
 );

 // Pass-through clock (no BUFG needed in simulation)
@@ -55,15 +50,4 @@ end
 assign adc_data_400m = adc_data_400m_reg;
 assign adc_data_valid_400m = adc_data_valid_400m_reg;

-// Audit F-0.1: 1-cycle pipeline of adc_or_p to match the real IDDR+register
-// capture path. TB drives adc_or_p directly with the overrange flag.
-reg adc_overrange_400m_reg;
-always @(posedge adc_dco_p or negedge reset_n) begin
-    if (!reset_n)
-        adc_overrange_400m_reg <= 1'b0;
-    else
-        adc_overrange_400m_reg <= adc_or_p;
-end
-assign adc_overrange_400m = adc_overrange_400m_reg;
-
 endmodule
@@ -487,8 +487,6 @@ radar_system_top #(
    .adc_d_n(adc_d_n),
    .adc_dco_p(adc_dco_p),
    .adc_dco_n(adc_dco_n),
-    .adc_or_p(1'b0),
-    .adc_or_n(1'b1),
    .adc_pwdn(adc_pwdn),
    
    // STM32 Control
@@ -64,11 +64,9 @@ module tb_ddc_cosim;

    // Scenario selector (set via +define)
    reg [255:0] scenario_name;
-    // Widened to 4 kbits (512 bytes) so fuzz-runner temp paths
-    // (e.g. /private/var/folders/.../pytest-of-...) fit without MSB truncation.
-    reg [4095:0] hex_file_path;
-    reg [4095:0] csv_out_path;
-    reg [4095:0] csv_cic_path;
+    reg [1023:0] hex_file_path;
+    reg [1023:0] csv_out_path;
+    reg [1023:0] csv_cic_path;

    // ── Clock generation ──────────────────────────────────────
    // 400 MHz clock
@@ -154,16 +152,7 @@ module tb_ddc_cosim;
        // ── Select scenario ───────────────────────────────────
        // Default to DC scenario for fastest validation
        // Override with: +define+SCENARIO_SINGLE, +define+SCENARIO_MULTI, etc.
-        `ifdef SCENARIO_FUZZ
-            // Audit F-3.2: fuzz runner provides +hex and +csv paths plus a
-            // scenario tag. Any missing plusarg falls back to the DC vector.
-            if (!$value$plusargs("hex=%s", hex_file_path))
-                hex_file_path = "tb/cosim/adc_dc.hex";
-            if (!$value$plusargs("csv=%s", csv_out_path))
-                csv_out_path  = "tb/cosim/rtl_bb_fuzz.csv";
-            if (!$value$plusargs("tag=%s", scenario_name))
-                scenario_name = "fuzz";
-        `elsif SCENARIO_SINGLE
+        `ifdef SCENARIO_SINGLE
            hex_file_path = "tb/cosim/adc_single_target.hex";
            csv_out_path  = "tb/cosim/rtl_bb_single_target.csv";
            scenario_name = "single_target";
@@ -139,8 +139,6 @@ radar_receiver_final dut (
    // ADC "LVDS" -- stub treats adc_d_p as single-ended data
    .adc_d_p(adc_data),
    .adc_d_n(~adc_data),       // Complement (ignored by stub)
-    .adc_or_p(1'b0),           // F-0.1: no overrange stimulus in this TB
-    .adc_or_n(1'b1),
    .adc_dco_p(clk_400m),      // 400 MHz clock
    .adc_dco_n(~clk_400m),     // Complement (ignored by stub)
    .adc_pwdn(),
@@ -427,8 +427,6 @@ radar_system_top #(
    .adc_d_n(adc_d_n),
    .adc_dco_p(adc_dco_p),
    .adc_dco_n(adc_dco_n),
-    .adc_or_p(1'b0),
-    .adc_or_n(1'b1),
    .adc_pwdn(adc_pwdn),

    .stm32_new_chirp(stm32_new_chirp),
@@ -940,106 +938,6 @@ initial begin

    $display("");

-    // ================================================================
-    // GROUP 9B: Adversarial reset sweep (audit F-2.2)
-    // ================================================================
-    // Drive the same auto-scan pipeline, then inject reset at four distinct
-    // offsets relative to a known-good start of operation. For each offset
-    // the system must:
-    //   (a) present system_status == 0 while held in reset
-    //   (b) produce at least one additional new_chirp_frame within the
-    //       observation window after reset release
-    //   (c) advance obs_range_valid_count (confirms full DDC+MF chain resumes)
-    // The four offsets are chosen to hit mid-chirp, mid-listen, and around
-    // the short/long chirp boundary, which covers the interesting FSM and
-    // CDC transitions in the pipeline.
-    $display("--- Group 9B: Adversarial reset sweep (F-2.2) ---");
-    begin : reset_sweep
-        integer sweep_i;
-        integer sweep_baseline_range;
-        integer sweep_baseline_chirp;
-        integer sweep_offsets [0:3];
-        integer sweep_holds   [0:3];
-        reg     sweep_ok;
-
-        // Reset injection offsets (ns) after the last auto-scan reconfigure.
-        // 3 us / 7 us / 12 us / 18 us — sprayed across a short-chirp burst.
-        sweep_offsets[0] = 3000;
-        sweep_offsets[1] = 7000;
-        sweep_offsets[2] = 12000;
-        sweep_offsets[3] = 18000;
-        // Reset-assert durations mix short (~20 clk_100m) and long (~120)
-        sweep_holds[0] = 200;
-        sweep_holds[1] = 1200;
-        sweep_holds[2] = 400;
-        sweep_holds[3] = 800;
-
-        for (sweep_i = 0; sweep_i < 4; sweep_i = sweep_i + 1) begin
-            // Re-seed auto-scan from a clean base each iteration
-            reset_n = 0;
-            bfm_rx_wr_ptr = 0;
-            bfm_rx_rd_ptr = 0;
-            #200;
-            reset_n = 1;
-            #500;
-            stm32_mixers_enable = 1;
-            ft601_txe = 0;
-            bfm_send_cmd(8'h04, 8'h00, 16'h0001);
-            #500;
-            bfm_send_cmd(8'h01, 8'h00, 16'h0001);
-            bfm_send_cmd(8'h10, 8'h00, 16'd100);
-            bfm_send_cmd(8'h11, 8'h00, 16'd200);
-            bfm_send_cmd(8'h12, 8'h00, 16'd100);
-            bfm_send_cmd(8'h13, 8'h00, 16'd20);
-            bfm_send_cmd(8'h14, 8'h00, 16'd100);
-            bfm_send_cmd(8'h15, 8'h00, 16'd4);
-
-            // Let the pipeline reach steady-state and capture a baseline
-            #30000;
-            sweep_baseline_range = obs_range_valid_count;
-            sweep_baseline_chirp = obs_chirp_frame_count;
-
-            // Wait out the configured offset, then assert reset asynchronously
-            #(sweep_offsets[sweep_i]);
-            reset_n = 0;
-            #(sweep_holds[sweep_i]);
-            sweep_ok = (system_status == 4'b0000);
-            check(sweep_ok,
-                  "G9B.a: system_status drops to 0 during injected reset");
-
-            // Release reset, re-configure (regs are cleared), allow recovery
-            reset_n = 1;
-            #500;
-            stm32_mixers_enable = 1;
-            ft601_txe = 0;
-            bfm_send_cmd(8'h04, 8'h00, 16'h0001);
-            #500;
-            bfm_send_cmd(8'h01, 8'h00, 16'h0001);
-            bfm_send_cmd(8'h10, 8'h00, 16'd100);
-            bfm_send_cmd(8'h11, 8'h00, 16'd200);
-            bfm_send_cmd(8'h12, 8'h00, 16'd100);
-            bfm_send_cmd(8'h13, 8'h00, 16'd20);
-            bfm_send_cmd(8'h14, 8'h00, 16'd100);
-            bfm_send_cmd(8'h15, 8'h00, 16'd4);
-
-            sweep_baseline_range = obs_range_valid_count;
-            sweep_baseline_chirp = obs_chirp_frame_count;
-            #60000;   // 60 us — two+ short-chirp frames
-
-            check(obs_chirp_frame_count > sweep_baseline_chirp,
-                  "G9B.b: new_chirp_frame resumes after injected reset");
-            check(obs_range_valid_count > sweep_baseline_range,
-                  "G9B.c: range pipeline resumes after injected reset");
-
-            $display("  [F-2.2] iter=%0d offset=%0dns hold=%0dns chirps=+%0d ranges=+%0d",
-                     sweep_i, sweep_offsets[sweep_i], sweep_holds[sweep_i],
-                     obs_chirp_frame_count - sweep_baseline_chirp,
-                     obs_range_valid_count - sweep_baseline_range);
-        end
-    end
-
-    $display("");
-
    // ================================================================
    // GROUP 10: STREAM CONTROL (Gap 2)
    // ================================================================
@@ -26,14 +26,12 @@ layers agree (because both could be wrong).

 from __future__ import annotations

-import ast
 import os
 import re
 import struct
 import subprocess
 import tempfile
 from pathlib import Path
-from typing import ClassVar

 import pytest

@@ -627,420 +625,6 @@ class TestTier1AgcCrossLayerInvariant:
        )


-# ===================================================================
-# ADAR1000 channel→register round-trip invariant (issue #90)
-# ===================================================================
-#
-# Ground-truth invariant crossing three system layers:
-#   Chip (datasheet) -> Driver (MCU helpers) -> Application (callers).
-#
-# For every logical element ch in {0,1,2,3} (hardware channels CH1..CH4),
-# the round-trip
-#     caller_expr(ch) --> helper_offset(channel) * stride --> base + off
-# must land on the physical register REG_CH{ch+1}_* defined in the ADI
-# ADAR1000 register map parsed from ADAR1000_Manager.h.
-#
-# Catches:
-#   * #90 channel rotation regardless of which side is fixed (caller OR helper).
-#   * Wrong stride (e.g. phase written with stride 1 instead of 2).
-#   * Bad mask (e.g. `channel & 0x07`, `channel & 0x01`).
-#   * Wrong base register in a helper.
-#   * New setter added with mismatched convention.
-#   * Caller moved to a file the test no longer scans (fails loudly).
-#
-# Cannot be defeated by:
-#   * Renaming/refactoring helper layout: the setter coverage test
-#     (`test_helper_sites_exist_for_all_setters`) catches missing parse.
-#   * Changing 0x03 to 3 or adding a named constant: the offset is
-#     evaluated symbolically via AST, not matched by regex.
-
-
-def _parse_adar_register_map(header_text):
-    """Extract `#define REG_CHn_(RX|TX)_(GAIN|PHS_I|PHS_Q)` values."""
-    regs = {}
-    for m in re.finditer(
-        r"^#define\s+(REG_CH[1-4]_(?:RX|TX)_(?:GAIN|PHS_I|PHS_Q))\s+(0x[0-9A-Fa-f]+)",
-        header_text,
-        re.MULTILINE,
-    ):
-        regs[m.group(1)] = int(m.group(2), 16)
-    return regs
-
-
-def _safe_eval_int_expr(expr, **variables):
-    """
-    Evaluate a small integer expression with +, -, *, &, |, ^, ~, <<, >>.
-    Python's & / | / ^ / ~ / << / >> have the same semantics as C for the
-    operand widths we care about here (uint8_t after the mask makes the
-    result fit in 0..3). No floating point, no function calls, no names
-    outside ``variables``.
-
-    SECURITY: ``expr`` MUST come from a trusted source -- specifically,
-    C/C++ source text under version control in this repository (e.g.
-    arguments parsed out of ``main.cpp``/``ADAR1000_AGC.cpp``).  Although
-    the AST whitelist below rejects function calls, attribute access,
-    subscripts, and any name not in ``variables``, ``eval`` is still
-    invoked on the compiled tree.  Do NOT pass user-supplied / network /
-    GUI input here.
-    """
-    tree = ast.parse(expr, mode="eval")
-    allowed = (
-        ast.Expression, ast.BinOp, ast.UnaryOp, ast.Constant,
-        ast.Name, ast.Load,
-        ast.Add, ast.Sub, ast.Mult, ast.Mod, ast.FloorDiv,
-        ast.BitAnd, ast.BitOr, ast.BitXor,
-        ast.USub, ast.UAdd, ast.Invert,
-        ast.LShift, ast.RShift,
-    )
-    for node in ast.walk(tree):
-        if not isinstance(node, allowed):
-            raise ValueError(
-                f"disallowed AST node {type(node).__name__!s} in `{expr}`"
-            )
-    return eval(
-        compile(tree, "<expr>", "eval"),
-        {"__builtins__": {}},
-        variables,
-    )
-
-
-def _extract_adar_helper_sites(manager_cpp, setter_names):
-    """
-    For each setter, locate the body of ``void ADAR1000Manager::<setter>``
-    and return a list of (setter, base_register, offset_expr_c, stride)
-    for every ``REG_CHn_XXX + <expr>`` memory-address assignment.
-    """
-    sites = []
-    for setter in setter_names:
-        m = re.search(
-            rf"void\s+ADAR1000Manager::{setter}\s*\([^)]*\)\s*\{{(.+?)^\}}",
-            manager_cpp,
-            re.MULTILINE | re.DOTALL,
-        )
-        if not m:
-            continue
-        body = m.group(1)
-        for access in re.finditer(
-            r"=\s*(REG_CH[1-4]_(?:RX|TX)_(?:GAIN|PHS_I|PHS_Q))\s*\+\s*([^;]+);",
-            body,
-        ):
-            base = access.group(1)
-            rhs = access.group(2).strip()
-            # Trailing `* <integer>` = stride multiplier (2 for phase I/Q).
-            stride_match = re.match(r"(.+?)\s*\*\s*(\d+)\s*$", rhs)
-            if stride_match:
-                offset_expr = stride_match.group(1).strip()
-                stride = int(stride_match.group(2))
-            else:
-                offset_expr = rhs
-                stride = 1
-            sites.append((setter, base, offset_expr, stride))
-    return sites
-
-
-# Method-definition line pattern: `[qualifier...] <ret-type> <Class>::<setter>(`
-# Covers: plain `void X::f(`, `inline void X::f(`, `static bool X::f(`, etc.
-_DEFN_RE = re.compile(
-    r"^\s*(?:inline\s+|static\s+|virtual\s+|constexpr\s+|explicit\s+)*"
-    r"(?:void|bool|uint\w+|int\w*|auto)\s+\S+::\w+\s*\("
-)
-
-
-def _extract_adar_caller_sites(sources, setter):
-    """
-    Find every call ``<obj>.<setter>(dev, <channel_expr>, ...)`` across
-    ``sources = [(filename, text), ...]``. Returns (filename, line_no,
-    channel_expr) for each. Skips function declarations/definitions.
-
-    Arg list up to matching `)`: restricted to a single line. All existing
-    call sites fit on one line; a future multi-line refactor would drop
-    callers from the scan, which the round-trip test surfaces loudly via
-    `assert callers` (rather than silently missing a site).
-    """
-    out = []
-    call_re = re.compile(rf"\b{setter}\s*\(([^;]*?)\)\s*;")
-    for filename, text in sources:
-        for line_no, line in enumerate(text.splitlines(), start=1):
-            # Skip method definition / declaration lines.
-            if _DEFN_RE.match(line):
-                continue
-            cm = call_re.search(line)
-            if not cm:
-                continue
-            args = _split_top_level_commas(cm.group(1))
-            if len(args) < 2:
-                continue
-            channel_expr = args[1].strip()
-            out.append((filename, line_no, channel_expr))
-    return out
-
-
-def _split_top_level_commas(text):
-    """Split on commas that sit at paren-depth 0 (ignores nested calls)."""
-    parts, depth, cur = [], 0, []
-    for ch in text:
-        if ch == "(":
-            depth += 1
-            cur.append(ch)
-        elif ch == ")":
-            depth -= 1
-            cur.append(ch)
-        elif ch == "," and depth == 0:
-            parts.append("".join(cur))
-            cur = []
-        else:
-            cur.append(ch)
-    if cur:
-        parts.append("".join(cur))
-    return parts
-
-
-class TestTier1Adar1000ChannelRegisterRoundTrip:
-    """
-    Cross-layer round-trip: caller channel expr -> helper offset formula
-    -> physical register address must equal REG_CH{ch+1}_* for every
-    caller and every ch in {0,1,2,3}.
-
-    See module-level block comment above and upstream issue #90.
-    """
-
-    _SETTERS = (
-        "adarSetRxPhase",
-        "adarSetTxPhase",
-        "adarSetRxVgaGain",
-        "adarSetTxVgaGain",
-    )
-
-    # Register base -> stride override. Parsed values of stride are
-    # trusted; this table is the independent ground truth for cross-check.
-    _EXPECTED_STRIDE: ClassVar[dict[str, int]] = {
-        "REG_CH1_RX_GAIN": 1,
-        "REG_CH1_TX_GAIN": 1,
-        "REG_CH1_RX_PHS_I": 2,
-        "REG_CH1_RX_PHS_Q": 2,
-        "REG_CH1_TX_PHS_I": 2,
-        "REG_CH1_TX_PHS_Q": 2,
-    }
-
-    @classmethod
-    def setup_class(cls):
-        cls.header_txt = (cp.MCU_LIB_DIR / "ADAR1000_Manager.h").read_text()
-        cls.manager_txt = (cp.MCU_LIB_DIR / "ADAR1000_Manager.cpp").read_text()
-        cls.reg_map = _parse_adar_register_map(cls.header_txt)
-        cls.helper_sites = _extract_adar_helper_sites(
-            cls.manager_txt, cls._SETTERS,
-        )
-        # Auto-discover every C++ TU under the MCU tree so a new caller
-        # added to e.g. a future ``ADAR1000_Calibration.cpp`` cannot
-        # silently escape the round-trip check (issue #90 reviewer note).
-        # Exclude any path containing a ``tests`` segment so this test
-        # does not parse its own fixtures.  The resulting list is
-        # deterministic (sorted) for reproducible parametrization.
-        scanned = []
-        seen = set()
-        for root in (cp.MCU_LIB_DIR, cp.MCU_CODE_DIR):
-            for path in sorted(root.rglob("*.cpp")):
-                if "tests" in path.parts:
-                    continue
-                if path in seen:
-                    continue
-                seen.add(path)
-                scanned.append((path.name, path.read_text()))
-        cls.sources = scanned
-        # Sanity: the two TUs known to call ADAR1000 setters at the time
-        # of issue #90 must be in scope.  If a future refactor renames or
-        # moves them this assert fires loudly rather than silently
-        # passing an empty round-trip.
-        scanned_names = {n for (n, _) in scanned}
-        for required in ("ADAR1000_AGC.cpp", "main.cpp", "ADAR1000_Manager.cpp"):
-            assert required in scanned_names, (
-                f"Auto-discovery missed `{required}`; check MCU_LIB_DIR / "
-                f"MCU_CODE_DIR roots in contract_parser.py."
-            )
-
-    # ---------- Tier A: chip ground truth ----------------------------
-
-    def test_register_map_gain_stride_is_one_per_channel(self):
-        """Datasheet invariant: RX/TX VGA gain registers are 1 byte apart."""
-        for kind in ("RX_GAIN", "TX_GAIN"):
-            for n in range(1, 4):
-                delta = (
-                    self.reg_map[f"REG_CH{n+1}_{kind}"]
-                    - self.reg_map[f"REG_CH{n}_{kind}"]
-                )
-                assert delta == 1, (
-                    f"ADAR1000 register map invariant broken: "
-                    f"REG_CH{n+1}_{kind} - REG_CH{n}_{kind} = {delta}, "
-                    f"datasheet says 1. Either the header was mis-edited "
-                    f"or ADI released a part with a different map."
-                )
-
-    def test_register_map_phase_stride_is_two_per_channel(self):
-        """Datasheet invariant: phase I/Q pairs occupy 2 bytes per channel."""
-        for kind in ("RX_PHS_I", "RX_PHS_Q", "TX_PHS_I", "TX_PHS_Q"):
-            for n in range(1, 4):
-                delta = (
-                    self.reg_map[f"REG_CH{n+1}_{kind}"]
-                    - self.reg_map[f"REG_CH{n}_{kind}"]
-                )
-                assert delta == 2, (
-                    f"ADAR1000 register map invariant broken: "
-                    f"REG_CH{n+1}_{kind} - REG_CH{n}_{kind} = {delta}, "
-                    f"datasheet says 2."
-                )
-
-    # ---------- Tier B: driver parses cleanly -------------------------
-
-    def test_helper_sites_exist_for_all_setters(self):
-        """Every channel-indexed setter must parse at least one register access."""
-        found = {s for (s, _, _, _) in self.helper_sites}
-        missing = set(self._SETTERS) - found
-        assert not missing, (
-            f"Helper parse failed for: {sorted(missing)}. "
-            f"Either a setter was renamed (update _SETTERS), moved out of "
-            f"ADAR1000_Manager.cpp (extend scan scope), or the register-"
-            f"access form changed beyond `REG_CHn_XXX + <expr>`. "
-            f"DO NOT weaken this test without reviewing issue #90."
-        )
-
-    def test_helper_parsed_stride_matches_datasheet(self):
-        """Parsed helper strides must match the datasheet register spacing."""
-        for setter, base, offset_expr, stride in self.helper_sites:
-            expected = self._EXPECTED_STRIDE.get(base)
-            assert expected is not None, (
-                f"{setter} writes to unrecognised base `{base}`. "
-                f"If ADI added a new channel-indexed register block, "
-                f"extend _EXPECTED_STRIDE with its datasheet stride."
-            )
-            assert stride == expected, (
-                f"{setter} helper uses stride {stride} for `{base}` "
-                f"(`{offset_expr} * {stride}`), datasheet says {expected}. "
-                f"Writes will overlap or skip channels."
-            )
-
-    # ---------- Tier C: round-trip to physical register ---------------
-
-    def test_all_callers_pass_one_based_channel(self):
-        """
-        INVARIANT: every caller's channel argument must, for ch in
-        {0,1,2,3}, evaluate to a 1-based ADI channel index in {1,2,3,4}.
-
-        The bug fixed in #90 was that helpers used ``channel & 0x03``
-        directly, so a caller passing bare ``ch`` (0..3) appeared to
-        work for ch=0..2 and silently aliased ch=3 onto CH4-then-CH1.
-        After the fix, helpers do ``(channel - 1) & 0x03`` and reject
-        ``channel < 1 || channel > 4``.  A future caller written as
-        ``adarSetRxPhase(dev, ch, ...)`` (bare 0-based) or
-        ``adarSetRxPhase(dev, 0, ...)`` (literal 0) would silently be
-        dropped by the bounds-check at runtime; this test catches it at
-        CI time instead.
-
-        The check intentionally lives one tier above the round-trip test
-        so the failure message points the reader at the API contract
-        (1-based per ADI datasheet & ADAR1000_AGC.cpp:76) rather than at
-        a register-arithmetic mismatch.
-        """
-        offenders = []
-        for setter in self._SETTERS:
-            callers = _extract_adar_caller_sites(self.sources, setter)
-            for filename, line_no, ch_expr in callers:
-                for ch in range(4):
-                    try:
-                        channel_val = _safe_eval_int_expr(ch_expr, ch=ch)
-                    except (NameError, KeyError, ValueError) as e:
-                        offenders.append(
-                            f"  - {filename}:{line_no} {setter}("
-                            f"…, `{ch_expr}`, …) -- ch={ch}: "
-                            f"unparseable ({e})"
-                        )
-                        continue
-                    if channel_val not in (1, 2, 3, 4):
-                        offenders.append(
-                            f"  - {filename}:{line_no} {setter}("
-                            f"…, `{ch_expr}`, …) -- ch={ch}: "
-                            f"channel={channel_val}, expected 1..4"
-                        )
-        assert not offenders, (
-            "ADAR1000 1-based channel API contract violated. The fix "
-            "for issue #90 requires every caller to pass channel in "
-            "{1,2,3,4} (CH1..CH4 per ADI datasheet). Bare 0-based ch "
-            "or a literal 0 will be silently dropped by the helper's "
-            "bounds check.  Offenders:\n" + "\n".join(offenders)
-        )
-
-    @pytest.mark.parametrize(
-        "setter",
-        [
-            "adarSetRxPhase",
-            "adarSetTxPhase",
-            "adarSetRxVgaGain",
-            "adarSetTxVgaGain",
-        ],
-    )
-    def test_round_trip_lands_on_intended_physical_channel(self, setter):
-        """
-        INVARIANT: for every caller of ``<setter>`` and every logical ch
-        in {0,1,2,3}, the effective register address equals
-        REG_CH{ch+1}_*. Catches #90 regardless of fix direction.
-        """
-        callers = _extract_adar_caller_sites(self.sources, setter)
-        assert callers, (
-            f"No callers of `{setter}` found. Either the test scope is "
-            f"incomplete (extend `setup_class.sources`) or the symbol was "
-            f"inlined/removed. A blind test is a dangerous test — "
-            f"investigate before weakening."
-        )
-        helpers = [
-            (b, e, s) for (nm, b, e, s) in self.helper_sites if nm == setter
-        ]
-        assert helpers, f"helper body for `{setter}` not parseable"
-
-        errors = []
-        for filename, line_no, ch_expr in callers:
-            for ch in range(4):
-                try:
-                    channel_val = _safe_eval_int_expr(ch_expr, ch=ch)
-                except (NameError, KeyError, ValueError) as e:
-                    pytest.fail(
-                        f"{filename}:{line_no}: caller channel expression "
-                        f"`{ch_expr}` uses symbol outside {{ch}} or a "
-                        f"disallowed operator ({e}). Extend "
-                        f"_safe_eval_int_expr variables or rewrite the "
-                        f"call site with a supported expression."
-                    )
-                for base_sym, offset_expr, stride in helpers:
-                    try:
-                        offset = _safe_eval_int_expr(
-                            offset_expr, channel=channel_val,
-                        )
-                    except (NameError, KeyError, ValueError) as e:
-                        pytest.fail(
-                            f"helper `{setter}` offset expr "
-                            f"`{offset_expr}` uses symbol outside "
-                            f"{{channel}} or a disallowed operator ({e}). "
-                            f"Extend _safe_eval_int_expr variables if new "
-                            f"driver state is introduced."
-                        )
-                    final = self.reg_map[base_sym] + offset * stride
-                    expected_sym = base_sym.replace("CH1", f"CH{ch + 1}")
-                    expected = self.reg_map[expected_sym]
-                    if final != expected:
-                        errors.append(
-                            f"  - {filename}:{line_no} {setter} "
-                            f"caller `{ch_expr}` | ch={ch} -> "
-                            f"channel={channel_val} -> "
-                            f"`{base_sym} + ({offset_expr})"
-                            f"{' * ' + str(stride) if stride != 1 else ''}`"
-                            f" = 0x{final:03X} "
-                            f"(expected {expected_sym} = 0x{expected:03X})"
-                        )
-        assert not errors, (
-            f"ADAR1000 channel round-trip FAILED for {setter} "
-            f"({len(errors)} mismatches) — writes routed to wrong physical "
-            f"channel. This is issue #90.\n" + "\n".join(errors)
-        )
-
-
 class TestTier1DataPacketLayout:
    """Verify data packet byte layout matches between Python and Verilog."""

@@ -1,185 +0,0 @@
-"""
-DDC Cosim Fuzz Runner (audit F-3.2)
-===================================
-Parameterized seed sweep over the existing DDC cosim testbench.
-
-For each seed the runner:
-  1. Generates a random plausible radar scene (1-4 targets, random range /
-     velocity / RCS, random noise level) via tb/cosim/radar_scene.py, using
-     the seed for full determinism.
-  2. Writes a temporary ADC hex file.
-  3. Compiles tb_ddc_cosim.v with -DSCENARIO_FUZZ (once, cached across seeds)
-     and runs vvp with +hex, +csv, +tag plusargs.
-  4. Parses the RTL output CSV and checks:
-       - non-empty output (the pipeline produced baseband samples)
-       - all I/Q values are within signed-18-bit range
-       - no NaN / parse errors
-       - sample count is within the expected bound from CIC decimation ratio
-
-The intent is liveness / crash-fuzz, not bit-exact cross-check. Bit-exact
-validation is covered by the static scenarios (single_target, multi_target,
-etc) in the existing suite. Fuzz complements that by surfacing edge-case
-corruption, saturation, or overflow on random-but-valid inputs.
-
-Marks:
-  - The default fuzz sweep uses 8 seeds for fast CI.
-  - Use `-m slow` to unlock the full 100-seed sweep matched to the audit ask.
-
-Compile + run times per seed on a laptop with iverilog 13: ~6 s. The default
-8-seed sweep fits in a ~1 minute pytest run; the 100-seed sweep takes ~10-12
-minutes.
-"""
-from __future__ import annotations
-
-import os
-import random
-import subprocess
-import sys
-import tempfile
-from pathlib import Path
-
-import pytest
-
-THIS_DIR = Path(__file__).resolve().parent
-REPO_ROOT = THIS_DIR.parent.parent.parent
-FPGA_DIR = REPO_ROOT / "9_Firmware" / "9_2_FPGA"
-COSIM_DIR = FPGA_DIR / "tb" / "cosim"
-
-sys.path.insert(0, str(COSIM_DIR))
-import radar_scene  # noqa: E402
-
-FAST_SEEDS = list(range(8))
-SLOW_SEEDS = list(range(100))
-
-# Pipeline constants
-N_ADC_SAMPLES = 16384
-CIC_DECIMATION = 4
-FIR_DECIMATION = 1
-EXPECTED_BB_MIN = N_ADC_SAMPLES // (CIC_DECIMATION * 4)   # pessimistic lower bound
-EXPECTED_BB_MAX = N_ADC_SAMPLES // CIC_DECIMATION         # upper bound before FIR drain
-SIGNED_18_MIN = -(1 << 17)
-SIGNED_18_MAX = (1 << 17) - 1
-
-SOURCE_FILES = [
-    "tb/tb_ddc_cosim.v",
-    "ddc_400m.v",
-    "nco_400m_enhanced.v",
-    "cic_decimator_4x_enhanced.v",
-    "fir_lowpass.v",
-    "cdc_modules.v",
-]
-
-
-@pytest.fixture(scope="module")
-def compiled_fuzz_vvp(tmp_path_factory):
-    """Compile tb_ddc_cosim.v once per pytest session with SCENARIO_FUZZ."""
-    iverilog = _iverilog_bin()
-    if not iverilog:
-        pytest.skip("iverilog not available on PATH")
-
-    out_dir = tmp_path_factory.mktemp("ddc_fuzz_build")
-    vvp = out_dir / "tb_ddc_cosim_fuzz.vvp"
-    sources = [str(FPGA_DIR / p) for p in SOURCE_FILES]
-    cmd = [
-        iverilog, "-g2001", "-DSIMULATION", "-DSCENARIO_FUZZ",
-        "-o", str(vvp), *sources,
-    ]
-    res = subprocess.run(cmd, cwd=FPGA_DIR, capture_output=True, text=True, check=False)
-    if res.returncode != 0:
-        pytest.skip(f"iverilog compile failed:\n{res.stderr}")
-    return vvp
-
-
-def _iverilog_bin() -> str | None:
-    from shutil import which
-    return which("iverilog")
-
-
-def _random_scene(seed: int) -> list[radar_scene.Target]:
-    rng = random.Random(seed)
-    n = rng.randint(1, 4)
-    return [
-        radar_scene.Target(
-            range_m=rng.uniform(50, 1500),
-            velocity_mps=rng.uniform(-40, 40),
-            rcs_dbsm=rng.uniform(-10, 20),
-            phase_deg=rng.uniform(0, 360),
-        )
-        for _ in range(n)
-    ]
-
-
-def _run_seed(seed: int, vvp: Path, work: Path) -> tuple[int, list[tuple[int, int]]]:
-    """Generate stimulus, run the DUT, return (bb_sample_count, [(i,q)...])."""
-    targets = _random_scene(seed)
-    noise = random.Random(seed ^ 0xA5A5).uniform(0.5, 6.0)
-    adc = radar_scene.generate_adc_samples(
-        targets, N_ADC_SAMPLES, noise_stddev=noise, seed=seed
-    )
-
-    hex_path = work / f"adc_fuzz_{seed:04d}.hex"
-    csv_path = work / f"rtl_bb_fuzz_{seed:04d}.csv"
-    radar_scene.write_hex_file(str(hex_path), adc, bits=8)
-
-    vvp_bin = _vvp_bin()
-    if not vvp_bin:
-        pytest.skip("vvp not available")
-
-    cmd = [
-        vvp_bin, str(vvp),
-        f"+hex={hex_path}",
-        f"+csv={csv_path}",
-        f"+tag=seed{seed:04d}",
-    ]
-    res = subprocess.run(cmd, cwd=FPGA_DIR, capture_output=True, text=True, check=False, timeout=120)
-    assert res.returncode == 0, f"vvp exit={res.returncode}\nstdout:\n{res.stdout}\nstderr:\n{res.stderr}"
-    assert csv_path.exists(), (
-        f"vvp completed rc=0 but CSV was not produced at {csv_path}\n"
-        f"cmd: {cmd}\nstdout:\n{res.stdout[-2000:]}\nstderr:\n{res.stderr[-500:]}"
-    )
-
-    rows = []
-    with csv_path.open() as fh:
-        header = fh.readline()
-        assert "baseband_i" in header and "baseband_q" in header, f"unexpected CSV header: {header!r}"
-        for line in fh:
-            parts = line.strip().split(",")
-            if len(parts) != 3:
-                continue
-            _, i_str, q_str = parts
-            rows.append((int(i_str), int(q_str)))
-    return len(rows), rows
-
-
-def _vvp_bin() -> str | None:
-    from shutil import which
-    return which("vvp")
-
-
-def _fuzz_assertions(seed: int, rows: list[tuple[int, int]]) -> None:
-    n = len(rows)
-    assert EXPECTED_BB_MIN <= n <= EXPECTED_BB_MAX, (
-        f"seed {seed}: bb sample count {n} outside [{EXPECTED_BB_MIN},{EXPECTED_BB_MAX}]"
-    )
-    for idx, (i, q) in enumerate(rows):
-        assert SIGNED_18_MIN <= i <= SIGNED_18_MAX, (
-            f"seed {seed} row {idx}: baseband_i={i} out of signed-18 range"
-        )
-        assert SIGNED_18_MIN <= q <= SIGNED_18_MAX, (
-            f"seed {seed} row {idx}: baseband_q={q} out of signed-18 range"
-        )
-    all_zero = all(i == 0 and q == 0 for i, q in rows)
-    assert not all_zero, f"seed {seed}: all-zero baseband output — pipeline likely stalled"
-
-
-@pytest.mark.parametrize("seed", FAST_SEEDS)
-def test_ddc_fuzz_fast(seed: int, compiled_fuzz_vvp: Path, tmp_path: Path) -> None:
-    _, rows = _run_seed(seed, compiled_fuzz_vvp, tmp_path)
-    _fuzz_assertions(seed, rows)
-
-
-@pytest.mark.slow
-@pytest.mark.parametrize("seed", SLOW_SEEDS)
-def test_ddc_fuzz_full(seed: int, compiled_fuzz_vvp: Path, tmp_path: Path) -> None:
-    _, rows = _run_seed(seed, compiled_fuzz_vvp, tmp_path)
-    _fuzz_assertions(seed, rows)
@@ -19,11 +19,6 @@ dev = [
 # ---------------------------------------------------------------------------
 # Ruff configuration
 # ---------------------------------------------------------------------------
-[tool.pytest.ini_options]
-markers = [
-    "slow: full-sweep tests (opt-in via -m slow); audit F-3.2 100-seed fuzz",
-]
-
 [tool.ruff]
 target-version = "py312"
 line-length = 100
@@ -1,216 +0,0 @@
-version = 1
-revision = 1
-requires-python = ">=3.12"
-
-[[package]]
-name = "aeris-10-radar"
-version = "1.0.0"
-source = { virtual = "." }
-
-[package.dev-dependencies]
-dev = [
-    { name = "h5py" },
-    { name = "numpy" },
-    { name = "pytest" },
-    { name = "ruff" },
-]
-
-[package.metadata]
-
-[package.metadata.requires-dev]
-dev = [
-    { name = "h5py", specifier = ">=3.10" },
-    { name = "numpy", specifier = ">=1.26" },
-    { name = "pytest", specifier = ">=8" },
-    { name = "ruff", specifier = ">=0.5" },
-]
-
-[[package]]
-name = "colorama"
-version = "0.4.6"
-source = { registry = "https://pypi.org/simple" }
-sdist = { url = "https://files.pythonhosted.org/packages/d8/53/6f443c9a4a8358a93a6792e2acffb9d9d5cb0a5cfd8802644b7b1c9a02e4/colorama-0.4.6.tar.gz", hash = "sha256:08695f5cb7ed6e0531a20572697297273c47b8cae5a63ffc6d6ed5c201be6e44", size = 27697 }
-wheels = [
-    { url = "https://files.pythonhosted.org/packages/d1/d6/3965ed04c63042e047cb6a3e6ed1a63a35087b6a609aa3a15ed8ac56c221/colorama-0.4.6-py2.py3-none-any.whl", hash = "sha256:4f1d9991f5acc0ca119f9d443620b77f9d6b33703e51011c16baf57afb285fc6", size = 25335 },
-]
-
-[[package]]
-name = "h5py"
-version = "3.16.0"
-source = { registry = "https://pypi.org/simple" }
-dependencies = [
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