Merge pull request #119 from NawfalMotii79/fix/mcu-fault-ack-emergency-clear

fix(mcu): FAULT_ACK USB command clears system_emergency_state (closes #83)
fix(mcu): add FAULT_ACK command to clear system_emergency_state via USB (closes #83 )
2026-04-21 23:11:42 +01:00 · 2026-04-21 03:57:55 +05:45 · 2026-04-21 00:57:08 +03:00 · 2026-04-21 03:35:48 +05:45 · 2026-04-21 00:26:33 +03:00 · 2026-04-21 03:06:32 +05:45
240 changed files with 140359 additions and 688166 deletions
@@ -1,21 +0,0 @@
 # Enforce LF line endings for all text files going forward.
 # Existing CRLF files are left as-is to avoid polluting git blame.
 * text=auto eol=lf
 # Binary files — ensure git doesn't mangle these
 *.npy binary
 *.h5 binary
 *.hdf5 binary
 *.png binary
 *.jpg binary
 *.pdf binary
 *.zip binary
 *.bin binary
 *.mem binary
 *.hex binary
 *.vvp binary
 *.s2p binary
 *.s3p binary
 *.step binary
 *.FCStd binary
 *.FCBak binary
@@ -32,12 +32,6 @@
 9_Firmware/9_2_FPGA/tb/cosim/rtl_doppler_*.csv
 9_Firmware/9_2_FPGA/tb/cosim/compare_doppler_*.csv
 9_Firmware/9_2_FPGA/tb/cosim/rtl_multiseg_*.csv
 9_Firmware/9_2_FPGA/tb/cosim/rx_final_doppler_out.csv
 9_Firmware/9_2_FPGA/tb/cosim/rtl_mf_*.csv
 9_Firmware/9_2_FPGA/tb/cosim/compare_mf_*.csv
 # Golden reference outputs (regenerated by testbenches)
 9_Firmware/9_2_FPGA/tb/golden/
 # macOS
 .DS_Store
@@ -63,17 +57,3 @@ build*_reports/
 # UART capture logs (generated by tools/uart_capture.py)
 logs/
 # Local schematic files
 # Schematic and board files (untracked)
 4_Schematics and Boards Layout/4_6_Schematics/FMC_TestBoard/*
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.kicad_sch
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.kicad_pcb
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.bak
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.tmp
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.net
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.dcm
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.svg
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.pdf
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/*.sch-bak
 4_Schematics and Boards Layout/4_6_Schematics/Main_Board/backup/
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@@ -714,8 +714,8 @@
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 <libraries>
 <library name="eagle-ltspice">
@@ -24576,8 +24625,8 @@ Your PCBWay Team
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@@ -1,10 +1,7 @@
 import numpy as np
 # Define parameters
-# NOTE: This is a standalone LUT generation utility. The production chirp LUT
+fs = 120e6  # Sampling frequency
 # is generated by 9_Firmware/9_2_FPGA/tb/cosim/gen_chirp_mem.py with
 # CHIRP_BW=20e6 (target: 30e6 Phase 1) and DAC_CLK=120e6.
 fs = 120e6  # Sampling frequency (DAC clock from AD9523 OUT10)
 Ts = 1 / fs  # Sampling time
 Tb = 1e-6  # Burst time
 Tau = 30e-6  # Pulse repetition time
@@ -18,12 +18,13 @@ ADAR1000_AGC::ADAR1000_AGC()
    , min_gain(0)
    , max_gain(127)
    , holdoff_frames(4)
-    , enabled(true)
+    , enabled(false)
    , holdoff_counter(0)
    , last_saturated(false)
    , saturation_event_count(0)
 {
    memset(cal_offset, 0, sizeof(cal_offset));
    if (holdoff_frames == 0) holdoff_frames = 1;
 }
 // ---------------------------------------------------------------------------
@@ -20,18 +20,71 @@ static const struct {
    {ADAR_4_CS_3V3_GPIO_Port, ADAR_4_CS_3V3_Pin}  // ADAR1000 #4
 };
-// Vector Modulator lookup tables
+// ADAR1000 Vector Modulator lookup tables (128-state phase grid, 2.8125 deg step).
 //
 // Source: Analog Devices ADAR1000 datasheet Rev. B, Tables 13-16, page 34
 //   (7_Components Datasheets and Application notes/ADAR1000.pdf)
 // Cross-checked against the ADI Linux mainline driver (GPL-2.0, NOT vendored):
 //   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/
 //     drivers/iio/beamformer/adar1000.c  (adar1000_phase_values[])
 // The 128 byte values themselves are factual data from the datasheet and are
 // not subject to copyright; only the ADI driver code is GPL.
 //
 // Byte format (per datasheet):
 //   bit  [7:6] reserved (0)
 //   bit  [5]   polarity:  1 = positive lobe (sign(I) or sign(Q) >= 0)
 //                          0 = negative lobe
 //   bits [4:0] 5-bit unsigned magnitude (0..31)
 // At magnitude=0 the polarity bit is physically meaningless; the datasheet
 // uses POL=1 (e.g. VM_Q at 0 deg = 0x20, VM_I at 90 deg = 0x21).
 //
 // Index mapping is uniform: VM_I[k] / VM_Q[k] correspond to phase angle
 // k * 360/128 = k * 2.8125 degrees.  Callers index as VM_*[phase % 128].
 const uint8_t ADAR1000Manager::VM_I[128] = {
-    // ... (same as in your original file)
+    0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3E, 0x3E, 0x3D,  // [  0]   0.0000 deg
    0x3D, 0x3C, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37,  // [  8]  22.5000 deg
    0x36, 0x35, 0x34, 0x33, 0x32, 0x30, 0x2F, 0x2E,  // [ 16]  45.0000 deg
    0x2C, 0x2B, 0x2A, 0x28, 0x27, 0x25, 0x24, 0x22,  // [ 24]  67.5000 deg
    0x21, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A,  // [ 32]  90.0000 deg
    0x0B, 0x0D, 0x0E, 0x0F, 0x11, 0x12, 0x13, 0x14,  // [ 40] 112.5000 deg
    0x16, 0x17, 0x18, 0x19, 0x19, 0x1A, 0x1B, 0x1C,  // [ 48] 135.0000 deg
    0x1C, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F,  // [ 56] 157.5000 deg
    0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, 0x1D,  // [ 64] 180.0000 deg
    0x1D, 0x1C, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17,  // [ 72] 202.5000 deg
    0x16, 0x15, 0x14, 0x13, 0x12, 0x10, 0x0F, 0x0E,  // [ 80] 225.0000 deg
    0x0C, 0x0B, 0x0A, 0x08, 0x07, 0x05, 0x04, 0x02,  // [ 88] 247.5000 deg
    0x01, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A,  // [ 96] 270.0000 deg
    0x2B, 0x2D, 0x2E, 0x2F, 0x31, 0x32, 0x33, 0x34,  // [104] 292.5000 deg
    0x36, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3C,  // [112] 315.0000 deg
    0x3C, 0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F,  // [120] 337.5000 deg
 };
 const uint8_t ADAR1000Manager::VM_Q[128] = {
-    // ... (same as in your original file)
+    0x20, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A,  // [  0]   0.0000 deg
    0x2B, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x33, 0x34,  // [  8]  22.5000 deg
    0x35, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A,  // [ 16]  45.0000 deg
    0x3B, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, 0x3D,  // [ 24]  67.5000 deg
    0x3D, 0x3D, 0x3D, 0x3D, 0x3D, 0x3C, 0x3C, 0x3C,  // [ 32]  90.0000 deg
    0x3B, 0x3A, 0x3A, 0x39, 0x38, 0x38, 0x37, 0x36,  // [ 40] 112.5000 deg
    0x35, 0x34, 0x33, 0x31, 0x30, 0x2F, 0x2E, 0x2D,  // [ 48] 135.0000 deg
    0x2B, 0x2A, 0x28, 0x27, 0x26, 0x24, 0x23, 0x21,  // [ 56] 157.5000 deg
    0x20, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A,  // [ 64] 180.0000 deg
    0x0B, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x13, 0x14,  // [ 72] 202.5000 deg
    0x15, 0x16, 0x17, 0x18, 0x18, 0x19, 0x1A, 0x1A,  // [ 80] 225.0000 deg
    0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D,  // [ 88] 247.5000 deg
    0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1C, 0x1C, 0x1C,  // [ 96] 270.0000 deg
    0x1B, 0x1A, 0x1A, 0x19, 0x18, 0x18, 0x17, 0x16,  // [104] 292.5000 deg
    0x15, 0x14, 0x13, 0x11, 0x10, 0x0F, 0x0E, 0x0D,  // [112] 315.0000 deg
    0x0B, 0x0A, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01,  // [120] 337.5000 deg
 };
-const uint8_t ADAR1000Manager::VM_GAIN[128] = {
+// NOTE: a VM_GAIN[128] table previously existed here as a placeholder but was
-    // ... (same as in your original file)
+// never populated and never read.  The ADAR1000 vector modulator has no
-};
+// separate gain register: phase-state magnitude is encoded directly in
 // bits [4:0] of the VM_I/VM_Q bytes above.  Per-channel VGA gain is a
 // distinct register (CHx_RX_GAIN at 0x10-0x13, CHx_TX_GAIN at 0x1C-0x1F)
 // written with the user-supplied byte directly by adarSetRxVgaGain() /
 // adarSetTxVgaGain().  Do not reintroduce a VM_GAIN[] array.
 ADAR1000Manager::ADAR1000Manager() {
    for (int i = 0; i < 4; ++i) {
@@ -815,11 +868,22 @@ void ADAR1000Manager::adarSetRamBypass(uint8_t deviceIndex, uint8_t broadcast) {
 }
 void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
    // channel is 1-based (CH1..CH4) per API contract documented in
    // ADAR1000_AGC.cpp and matching ADI datasheet terminology.
    // Reject out-of-range early so a stale 0-based caller does not
    // silently wrap to ((0-1) & 0x03) == 3 and write to CH4.
    // See issue #90.
    if (channel < 1 || channel > 4) {
        DIAG("BF", "adarSetRxPhase: channel %u out of range [1..4], ignored", channel);
        return;
    }
    uint8_t i_val = VM_I[phase % 128];
    uint8_t q_val = VM_Q[phase % 128];
-    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
+    // Subtract 1 to convert 1-based channel to 0-based register offset
-    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;
+    // before masking. See issue #90.
    uint32_t mem_addr_i = REG_CH1_RX_PHS_I + ((channel - 1) & 0x03) * 2;
    uint32_t mem_addr_q = REG_CH1_RX_PHS_Q + ((channel - 1) & 0x03) * 2;
    adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
    adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -827,11 +891,16 @@ void ADAR1000Manager::adarSetRxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 }
 void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8_t phase, uint8_t broadcast) {
    // channel is 1-based (CH1..CH4). See issue #90.
    if (channel < 1 || channel > 4) {
        DIAG("BF", "adarSetTxPhase: channel %u out of range [1..4], ignored", channel);
        return;
    }
    uint8_t i_val = VM_I[phase % 128];
    uint8_t q_val = VM_Q[phase % 128];
-    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
+    uint32_t mem_addr_i = REG_CH1_TX_PHS_I + ((channel - 1) & 0x03) * 2;
-    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;
+    uint32_t mem_addr_q = REG_CH1_TX_PHS_Q + ((channel - 1) & 0x03) * 2;
    adarWrite(deviceIndex, mem_addr_i, i_val, broadcast);
    adarWrite(deviceIndex, mem_addr_q, q_val, broadcast);
@@ -839,13 +908,23 @@ void ADAR1000Manager::adarSetTxPhase(uint8_t deviceIndex, uint8_t channel, uint8
 }
 void ADAR1000Manager::adarSetRxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    uint32_t mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
+    // channel is 1-based (CH1..CH4). See issue #90.
    if (channel < 1 || channel > 4) {
        DIAG("BF", "adarSetRxVgaGain: channel %u out of range [1..4], ignored", channel);
        return;
    }
    uint32_t mem_addr = REG_CH1_RX_GAIN + ((channel - 1) & 0x03);
    adarWrite(deviceIndex, mem_addr, gain, broadcast);
    adarWrite(deviceIndex, REG_LOAD_WORKING, 0x1, broadcast);
 }
 void ADAR1000Manager::adarSetTxVgaGain(uint8_t deviceIndex, uint8_t channel, uint8_t gain, uint8_t broadcast) {
-    uint32_t mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
+    // channel is 1-based (CH1..CH4). See issue #90.
    if (channel < 1 || channel > 4) {
        DIAG("BF", "adarSetTxVgaGain: channel %u out of range [1..4], ignored", channel);
        return;
    }
    uint32_t mem_addr = REG_CH1_TX_GAIN + ((channel - 1) & 0x03);
    adarWrite(deviceIndex, mem_addr, gain, broadcast);
    adarWrite(deviceIndex, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 }
@@ -116,10 +116,12 @@ public:
    bool beam_sweeping_active_ = false;
    uint32_t last_beam_update_time_ = 0;
-    // Lookup tables
+    // Vector Modulator lookup tables (see ADAR1000_Manager.cpp for provenance).
    // Indexed as VM_*[phase % 128] on a uniform 2.8125 deg grid.
    // No VM_GAIN[] table exists: VM magnitude is bits [4:0] of the I/Q bytes
    // themselves; per-channel VGA gain uses a separate register.
    static const uint8_t VM_I[128];
    static const uint8_t VM_Q[128];
    static const uint8_t VM_GAIN[128];
    // Named defaults for the ADTR1107 and ADAR1000 power sequence.
    static constexpr uint8_t kDefaultTxVgaGain = 0x7F;
@@ -6,16 +6,16 @@ RadarSettings::RadarSettings() {
 }
 void RadarSettings::resetToDefaults() {
-    system_frequency = 10.5e9;    // 10.5 GHz (PLFM TX LO, ADF4382 config)
+    system_frequency = 10.0e9;    // 10 GHz
-    chirp_duration_1 = 30.0e-6;   // 30 µs
+    chirp_duration_1 = 30.0e-6;   // 30 �s
-    chirp_duration_2 = 0.5e-6;    // 0.5 µs
+    chirp_duration_2 = 0.5e-6;    // 0.5 �s
    chirps_per_position = 32;
    freq_min = 10.0e6;           // 10 MHz
    freq_max = 30.0e6;           // 30 MHz
    prf1 = 1000.0;               // 1 kHz
    prf2 = 2000.0;               // 2 kHz
-    max_distance = 3072.0;       // 3072 m (512 bins × 6 m, 3 km mode)
+    max_distance = 50000.0;      // 50 km
-    map_size = 3072.0;           // 3072 m
+    map_size = 50000.0;          // 50 km
    settings_valid = true;
 }
@@ -88,7 +88,7 @@ bool RadarSettings::validateSettings() {
    if (prf1 < 100 || prf1 > 10000) return false;
    if (prf2 < 100 || prf2 > 10000) return false;
    if (max_distance < 100 || max_distance > 100000) return false;
-    if (map_size < 100 || map_size > 200000) return false;
+    if (map_size < 1000 || map_size > 200000) return false;
    return true;
 }
@@ -13,6 +13,7 @@ void USBHandler::reset() {
    start_flag_received = false;
    buffer_index = 0;
    current_settings.resetToDefaults();
    fault_ack_received = false;
 }
 void USBHandler::processUSBData(const uint8_t* data, uint32_t length) {
@@ -23,6 +24,18 @@ void USBHandler::processUSBData(const uint8_t* data, uint32_t length) {
    DIAG("USB", "processUSBData: %lu bytes, state=%d", (unsigned long)length, (int)current_state);
    // FAULT_ACK: host sends exactly 4 bytes [0x40, 0x00, 0x00, 0x00].
    // Requires exact 4-byte packet length: settings packets are always
    // >= 82 bytes, so a lone 4-byte payload is unambiguous. Scanning
    // inside larger packets would false-trigger on the IEEE 754
    // encoding of 2.0 (0x4000000000000000) embedded in settings doubles.
    static const uint8_t FAULT_ACK_SEQ[4] = {0x40, 0x00, 0x00, 0x00};
    if (length == 4 && memcmp(data, FAULT_ACK_SEQ, 4) == 0) {
        fault_ack_received = true;
        DIAG("USB", "FAULT_ACK received");
        return;
    }
    switch (current_state) {
        case USBState::WAITING_FOR_START:
            processStartFlag(data, length);
@@ -29,6 +29,11 @@ public:
    // Reset USB handler
    void reset();
    // Fault-acknowledgement: host sends FAULT_ACK (0x40) to clear
    // system_emergency_state and exit the safe-mode blink loop.
    bool isFaultAckReceived() const { return fault_ack_received; }
    void clearFaultAck()            { fault_ack_received = false; }
 private:
    RadarSettings current_settings;
    USBState current_state;
@@ -38,6 +43,7 @@ private:
    static constexpr uint32_t MAX_BUFFER_SIZE = 256;
    uint8_t usb_buffer[MAX_BUFFER_SIZE];
    uint32_t buffer_index;
    bool fault_ack_received;
    void processStartFlag(const uint8_t* data, uint32_t length);
    void processSettingsData(const uint8_t* data, uint32_t length);
@@ -1,693 +0,0 @@
 /**
 * MIT License
 * 
 * Copyright (c) 2020 Jimmy Pentz
 *
 * Reach me at: github.com/jgpentz, jpentz1(at)gmail.com
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sells
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
 /* ADAR1000 4-Channel, X Band and Ku Band Beamformer */
 // ----------------------------------------------------------------------------
 // Includes
 // ----------------------------------------------------------------------------
 #include "main.h"
 #include "stm32f7xx_hal.h"
 #include "stm32f7xx_hal_spi.h"
 #include "stm32f7xx_hal_gpio.h"
 #include "adar1000.h"
 // ----------------------------------------------------------------------------
 // Preprocessor Definitions and Constants
 // ----------------------------------------------------------------------------
 // VM_GAIN is 15 dB of gain in 128 steps. ~0.12 dB per step.
 // A 15 dB attenuator can be applied on top of these values.
 const uint8_t VM_GAIN[128] = {
 	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
 	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
 	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
 	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
 	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
 	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
 	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
 	0x70, 0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7a, 0x7b, 0x7c, 0x7d, 0x7e, 0x7f,
 };
 // VM_I and VM_Q are the settings for the vector modulator. 128 steps in 360 degrees. ~2.813 degrees per step.
 const uint8_t VM_I[128] = {
 	0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3E, 0x3E, 0x3D, 0x3D, 0x3C, 0x3C, 0x3B, 0x3A, 0x39, 0x38, 0x37,
 	0x36, 0x35, 0x34, 0x33, 0x32, 0x30, 0x2F, 0x2E, 0x2C, 0x2B, 0x2A, 0x28, 0x27, 0x25, 0x24, 0x22,
 	0x21, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0D, 0x0E, 0x0F, 0x11, 0x12, 0x13, 0x14,
 	0x16, 0x17, 0x18, 0x19, 0x19, 0x1A, 0x1B, 0x1C, 0x1C, 0x1D, 0x1E, 0x1E, 0x1E, 0x1F, 0x1F, 0x1F,
 	0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1E, 0x1E, 0x1D, 0x1D, 0x1C, 0x1C, 0x1B, 0x1A, 0x19, 0x18, 0x17,
 	0x16, 0x15, 0x14, 0x13, 0x12, 0x10, 0x0F, 0x0E, 0x0C, 0x0B, 0x0A, 0x08, 0x07, 0x05, 0x04, 0x02,
 	0x01, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, 0x2B, 0x2D, 0x2E, 0x2F, 0x31, 0x32, 0x33, 0x34,
 	0x36, 0x37, 0x38, 0x39, 0x39, 0x3A, 0x3B, 0x3C, 0x3C, 0x3D, 0x3E, 0x3E, 0x3E, 0x3F, 0x3F, 0x3F,
 };
 const uint8_t VM_Q[128] = {
 	0x20, 0x21, 0x23, 0x24, 0x26, 0x27, 0x28, 0x2A, 0x2B, 0x2D, 0x2E, 0x2F, 0x30, 0x31, 0x33, 0x34,
 	0x35, 0x36, 0x37, 0x38, 0x38, 0x39, 0x3A, 0x3A, 0x3B, 0x3C, 0x3C, 0x3C, 0x3D, 0x3D, 0x3D, 0x3D,
 	0x3D, 0x3D, 0x3D, 0x3D, 0x3D, 0x3C, 0x3C, 0x3C, 0x3B, 0x3A, 0x3A, 0x39, 0x38, 0x38, 0x37, 0x36,
 	0x35, 0x34, 0x33, 0x31, 0x30, 0x2F, 0x2E, 0x2D, 0x2B, 0x2A, 0x28, 0x27, 0x26, 0x24, 0x23, 0x21,
 	0x20, 0x01, 0x03, 0x04, 0x06, 0x07, 0x08, 0x0A, 0x0B, 0x0D, 0x0E, 0x0F, 0x10, 0x11, 0x13, 0x14,
 	0x15, 0x16, 0x17, 0x18, 0x18, 0x19, 0x1A, 0x1A, 0x1B, 0x1C, 0x1C, 0x1C, 0x1D, 0x1D, 0x1D, 0x1D,
 	0x1D, 0x1D, 0x1D, 0x1D, 0x1D, 0x1C, 0x1C, 0x1C, 0x1B, 0x1A, 0x1A, 0x19, 0x18, 0x18, 0x17, 0x16,
 	0x15, 0x14, 0x13, 0x11, 0x10, 0x0F, 0x0E, 0x0D, 0x0B, 0x0A, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01,
 };
 // ----------------------------------------------------------------------------
 // Function Definitions
 // ----------------------------------------------------------------------------
 /**
 * @brief	Initialize the ADC on the ADAR by setting the ADC with a 2 MHz clk, 
 *			and then enable it.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @warning	This is setup to only read temperature sensor data, not the power detectors.
 */
 void Adar_AdcInit(const AdarDevice * p_adar, uint8_t broadcast)
 {
 	uint8_t data;
 	data = ADAR1000_ADC_2MHZ_CLK | ADAR1000_ADC_EN;
 	Adar_Write(p_adar, REG_ADC_CONTROL, data, broadcast);
 }
 /**
 * @brief	Read a byte of data from the ADAR.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @return	Returns a byte of data that has been converted from the temperature sensor.
 *
 * @warning	This is setup to only read temperature sensor data, not the power detectors.
 */
 uint8_t Adar_AdcRead(const AdarDevice * p_adar, uint8_t broadcast)
 {
 	uint8_t data;
    // Start the ADC conversion
 	Adar_Write(p_adar, REG_ADC_CONTROL, ADAR1000_ADC_ST_CONV, broadcast);
    // This is blocking for now... wait until data is converted, then read it
 	while (!(Adar_Read(p_adar, REG_ADC_CONTROL) & 0x01))
 	{
 	}
 	data = Adar_Read(p_adar, REG_ADC_OUT);
 	return(data);
 }
 /**
 * @brief	Requests the device info from a specific ADAR and stores it in the
 *			provided AdarDeviceInfo struct.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param   info[out]	Struct that contains the device info fields.
 *
 * @return	Returns ADAR_ERROR_NOERROR if information was successfully received and stored in the struct.
 */
 uint8_t Adar_GetDeviceInfo(const AdarDevice * p_adar, AdarDeviceInfo * info)
 {
 	*((uint8_t *)info) = Adar_Read(p_adar, 0x002);
 	info->chip_type = Adar_Read(p_adar, 0x003);
 	info->product_id = ((uint16_t)Adar_Read(p_adar, 0x004)) << 8;
 	info->product_id |= ((uint16_t)Adar_Read(p_adar, 0x005)) & 0x00ff;
 	info->scratchpad = Adar_Read(p_adar, 0x00A);
 	info->spi_rev = Adar_Read(p_adar, 0x00B);
 	info->vendor_id = ((uint16_t)Adar_Read(p_adar, 0x00C)) << 8;
 	info->vendor_id |= ((uint16_t)Adar_Read(p_adar, 0x00D)) & 0x00ff;
 	info->rev_id = Adar_Read(p_adar, 0x045);
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief	Read the data that is stored in a single ADAR register.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param	mem_addr	Memory address of the register you wish to read from.
 *
 * @return	Returns the byte of data that is stored in the desired register.
 *
 * @warning	This function will clear ADDR_ASCN bits.
 * @warning The ADAR does not allow for block reads.
 */
 uint8_t Adar_Read(const AdarDevice * p_adar, uint32_t mem_addr)
 {
 	uint8_t instruction[3];
    // Set SDO active
 	Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, INTERFACE_CONFIG_A_SDO_ACTIVE, 0);
 	instruction[0] = 0x80 | ((p_adar->dev_addr & 0x03) << 5);
 	instruction[0] |= ((0xff00 & mem_addr) >> 8);
 	instruction[1] = (0xff & mem_addr);
 	instruction[2] = 0x00;
 	p_adar->Transfer(instruction, p_adar->p_rx_buffer, ADAR1000_RD_SIZE);
    // Set SDO Inactive
 	Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, 0, 0);
 	return(p_adar->p_rx_buffer[2]);
 }
 /**
 * @brief	Block memory write to an ADAR device.
 *
 * @pre		ADDR_ASCN bits in register zero must be set!
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param	mem_addr  	Memory address of the register you wish to read from.
 * @param	p_data    	Pointer to block of data to transfer (must have two unused bytes preceding the data for instruction).
 * @param	size      	Size of data in bytes, including the two additional leading bytes.
 *
 * @warning First two bytes of data will be corrupted if you do not provide two unused leading bytes!
 */
 void Adar_ReadBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size)
 {
    // Set SDO active
 	Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, INTERFACE_CONFIG_A_SDO_ACTIVE | INTERFACE_CONFIG_A_ADDR_ASCN, 0);
    // Prepare command
 	p_data[0] = 0x80 | ((p_adar->dev_addr & 0x03) << 5);
 	p_data[0] |= ((mem_addr) >> 8) & 0x1F;
 	p_data[1] = (0xFF & mem_addr);
    // Start the transfer
 	p_adar->Transfer(p_data, p_data, size);
 	Adar_Write(p_adar, REG_INTERFACE_CONFIG_A, 0, 0);
    // Return nothing since we assume this is non-blocking and won't wait around
 }
 /**
 * @brief	Sets the Rx/Tx bias currents for the LNA, VM, and VGA to be in either
 *			low power setting or nominal setting.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param	p_bias[in]	An AdarBiasCurrents struct filled with bias settings
 *						as seen in the datasheet Table 6. SPI Settings for 
 *						Different Power	Modules
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @return	Returns ADAR_ERR_NOERROR if the bias currents were set 
 */
 uint8_t Adar_SetBiasCurrents(const AdarDevice * p_adar, AdarBiasCurrents * p_bias, uint8_t broadcast)
 {
 	uint8_t bias = 0;
    // RX LNA/VGA/VM bias
 	bias = (p_bias->rx_lna & 0x0f);
 	Adar_Write(p_adar, REG_BIAS_CURRENT_RX_LNA, bias, broadcast); // RX LNA bias
 	bias = (p_bias->rx_vga & 0x07 << 3) | (p_bias->rx_vm & 0x07);
 	Adar_Write(p_adar, REG_BIAS_CURRENT_RX, bias, broadcast);     // RX VM/VGA bias
    // TX VGA/VM/DRV bias
 	bias = (p_bias->tx_vga & 0x07 << 3) | (p_bias->tx_vm & 0x07);
 	Adar_Write(p_adar, REG_BIAS_CURRENT_TX, bias, broadcast);     // TX VM/VGA bias
 	bias = (p_bias->tx_drv & 0x07);
 	Adar_Write(p_adar, REG_BIAS_CURRENT_TX_DRV, bias, broadcast); // TX DRV bias
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief	Set the bias ON and bias OFF voltages for the four PA's and one LNA.
 *
 * @pre		This will set all 5 bias ON values and all 5 bias OFF values at once.
 * 			To enable these bias values, please see the data sheet and ensure that the BIAS_CTRL,
 * 			LNA_BIAS_OUT_EN, TR_SOURCE, TX_EN, RX_EN, TR (input to chip), and PA_ON (input to chip)
 * 			bits have all been properly set.
 *
 * @param	p_adar[in]		Adar pointer Which specifies the device and what function 
 *							to use for SPI transfer.
 * @param 	bias_on_voltage   Array that contains the bias ON voltages.
 * @param 	bias_off_voltage  Array that contains the bias OFF voltages.
 *
 * @return	Returns ADAR_ERR_NOERROR if the bias currents were set 
 */
 uint8_t Adar_SetBiasVoltages(const AdarDevice * p_adar, uint8_t bias_on_voltage[5], uint8_t bias_off_voltage[5])
 {
 	Adar_SetBit(p_adar, 0x30, 6, BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x38, 5, BROADCAST_OFF);
 	Adar_Write(p_adar, REG_PA_CH1_BIAS_ON,bias_on_voltage[0], BROADCAST_OFF);
 	Adar_Write(p_adar, REG_PA_CH2_BIAS_ON,bias_on_voltage[1], BROADCAST_OFF);
 	Adar_Write(p_adar, REG_PA_CH3_BIAS_ON,bias_on_voltage[2], BROADCAST_OFF);
 	Adar_Write(p_adar, REG_PA_CH4_BIAS_ON,bias_on_voltage[3], BROADCAST_OFF);
 	Adar_Write(p_adar, REG_PA_CH1_BIAS_OFF,bias_off_voltage[0], BROADCAST_OFF);
 	Adar_Write(p_adar, REG_PA_CH2_BIAS_OFF,bias_off_voltage[1], BROADCAST_OFF);
 	Adar_Write(p_adar, REG_PA_CH3_BIAS_OFF,bias_off_voltage[2], BROADCAST_OFF);
 	Adar_Write(p_adar, REG_PA_CH4_BIAS_OFF,bias_off_voltage[3], BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x30, 4, BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x30, 6, BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x38, 5, BROADCAST_OFF);
 	Adar_Write(p_adar, REG_LNA_BIAS_ON,bias_on_voltage[4], BROADCAST_OFF);
 	Adar_Write(p_adar, REG_LNA_BIAS_OFF,bias_off_voltage[4], BROADCAST_OFF);
 	Adar_ResetBit(p_adar, 0x30, 7, BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x31, 2, BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x31, 4, BROADCAST_OFF);
 	Adar_SetBit(p_adar, 0x31, 7, BROADCAST_OFF);
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief	Setup the ADAR to use settings that are transferred over SPI.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @return	Returns ADAR_ERR_NOERROR if the bias currents were set 
 */
 uint8_t Adar_SetRamBypass(const AdarDevice * p_adar, uint8_t broadcast)
 {
 	uint8_t data;
 	data = (MEM_CTRL_BIAS_RAM_BYPASS | MEM_CTRL_BEAM_RAM_BYPASS);
 	Adar_Write(p_adar, REG_MEM_CTL, data, broadcast);
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief	Set the VGA gain value of a Receive channel in dB.
 *
 * @param	p_adar[in]		Adar pointer Which specifies the device and what function 
 *							to use for SPI transfer.
 * @param 	channel			Channel in which to set the gain (1-4).
 * @param 	vga_gain_db		Gain to be applied to the channel, ranging from 0 - 30 dB. 
 *							(Intended operation >16 dB).
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @return 	Returns ADAR_ERROR_NOERROR if the gain was successfully set. 
 * 					ADAR_ERROR_FAILED if an invalid channel was selected.
 *
 * @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
 */
 uint8_t Adar_SetRxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast)
 {
 	uint8_t	 vga_gain_bits = (uint8_t)(255*vga_gain_db/16);
 	uint32_t mem_addr = 0;
 	if((channel == 0) || (channel > 4))
 	{
 		return(ADAR_ERROR_FAILED);
 	}
 	mem_addr = REG_CH1_RX_GAIN + (channel & 0x03);
    // Set gain
 	Adar_Write(p_adar, mem_addr, vga_gain_bits, broadcast);
    // Load the new setting
 	Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief	Set the phase of a given receive channel using the I/Q vector modulator.
 *
 * @pre		According to the given @param phase, this sets the polarity (bit 5) and gain (bits 4-0)
 * 			of the @param channel, and then loads them into the working register.
 * 			A vector modulator I/Q look-up table has been provided at the beginning of this library.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param	channel   	Channel in which to set the gain (1-4).
 * @param	phase     	Byte that is used to set the polarity (bit 5) and gain (bits 4-0).
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @return 	Returns ADAR_ERROR_NOERROR if the phase was successfully set. 
 * 					ADAR_ERROR_FAILED if an invalid channel was selected.
 *
 * @note    To obtain your phase:
 *          phase = degrees * 128;
 *          phase /= 360;
 */
 uint8_t Adar_SetRxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast)
 {
 	uint8_t	 i_val = 0;
 	uint8_t	 q_val = 0;
 	uint32_t mem_addr_i, mem_addr_q;
 	if((channel == 0) || (channel > 4))
 	{
 		return(ADAR_ERROR_FAILED);
 	}
 	//phase = phase % 128;
 	i_val = VM_I[phase];
 	q_val = VM_Q[phase];
 	mem_addr_i = REG_CH1_RX_PHS_I + (channel & 0x03) * 2;
 	mem_addr_q = REG_CH1_RX_PHS_Q + (channel & 0x03) * 2;
 	Adar_Write(p_adar, mem_addr_i, i_val, broadcast);
 	Adar_Write(p_adar, mem_addr_q, q_val, broadcast);
 	Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief	Set the VGA gain value of a Tx channel in dB.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @return 	Returns ADAR_ERROR_NOERROR if the bias was successfully set. 
 * 					ADAR_ERROR_FAILED if an invalid channel was selected.
 *
 * @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
 */
 uint8_t Adar_SetTxBias(const AdarDevice * p_adar, uint8_t broadcast)
 {
 	uint8_t	 vga_bias_bits;
 	uint8_t	 drv_bias_bits;
 	uint32_t mem_vga_bias;
 	uint32_t mem_drv_bias;
 	mem_vga_bias = REG_BIAS_CURRENT_TX;
 	mem_drv_bias = REG_BIAS_CURRENT_TX_DRV;
    // Set bias to nom
 	vga_bias_bits = 0x2D;
 	drv_bias_bits = 0x06;
    // Set bias
 	Adar_Write(p_adar, mem_vga_bias, vga_bias_bits, broadcast);
    // Set bias
 	Adar_Write(p_adar, mem_drv_bias, drv_bias_bits, broadcast);
    // Load the new setting
 	Adar_Write(p_adar, REG_LOAD_WORKING, 0x2, broadcast);
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief	Set the VGA gain value of a Tx channel.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	channel     Tx channel in which to set the gain, ranging from 1 - 4.
 * @param 	gain   		Gain to be applied to the channel, ranging from 0 - 127,
 *						plus the MSb 15dB attenuator (Intended operation >16 dB).
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @return 	Returns ADAR_ERROR_NOERROR if the gain was successfully set. 
 * 					ADAR_ERROR_FAILED if an invalid channel was selected.
 *
 * @warning 0 dB or 15 dB step attenuator may also be turned on, which is why intended operation is >16 dB.
 */
 uint8_t Adar_SetTxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t gain, uint8_t broadcast)
 {
 	uint32_t mem_addr;
 	if((channel == 0) || (channel > 4))
 	{
 		return(ADAR_ERROR_FAILED);
 	}
 	mem_addr = REG_CH1_TX_GAIN + (channel & 0x03);
    // Set gain
 	Adar_Write(p_adar, mem_addr, gain, broadcast);
    // Load the new setting
 	Adar_Write(p_adar, REG_LOAD_WORKING, LD_WRK_REGS_LDTX_OVERRIDE, broadcast);
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief 	Set the phase of a given transmit channel using the I/Q vector modulator.
 *
 * @pre		According to the given @param phase, this sets the polarity (bit 5) and gain (bits 4-0)
 * 			of the @param channel, and then loads them into the working register.
 * 			A vector modulator I/Q look-up table has been provided at the beginning of this library.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	channel   	Channel in which to set the gain (1-4).
 * @param 	phase     	Byte that is used to set the polarity (bit 5) and gain (bits 4-0).
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 *
 * @return 	Returns ADAR_ERROR_NOERROR if the phase was successfully set. 
 * 					ADAR_ERROR_FAILED if an invalid channel was selected.
 *
 * @note    To obtain your phase:
 *          phase = degrees * 128;
 *          phase /= 360;
 */
 uint8_t Adar_SetTxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast)
 {
 	uint8_t	 i_val = 0;
 	uint8_t	 q_val = 0;
 	uint32_t mem_addr_i, mem_addr_q;
 	if((channel == 0) || (channel > 4))
 	{
 		return(ADAR_ERROR_FAILED);
 	}
 	//phase = phase % 128;
 	i_val = VM_I[phase];
 	q_val = VM_Q[phase];
 	mem_addr_i = REG_CH1_TX_PHS_I + (channel & 0x03) * 2;
 	mem_addr_q = REG_CH1_TX_PHS_Q + (channel & 0x03) * 2;
 	Adar_Write(p_adar, mem_addr_i, i_val, broadcast);
 	Adar_Write(p_adar, mem_addr_q, q_val, broadcast);
 	Adar_Write(p_adar, REG_LOAD_WORKING, 0x1, broadcast);
 	return(ADAR_ERROR_NOERROR);
 }
 /**
 * @brief 	Reset the whole ADAR device.
 *
 * @param	p_adar[in]	ADAR pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 */
 void Adar_SoftReset(const AdarDevice * p_adar)
 {
 	uint8_t instruction[3];
 	instruction[0] = ((p_adar->dev_addr & 0x03) << 5);
 	instruction[1] = 0x00;
 	instruction[2] = 0x81;
 	p_adar->Transfer(instruction, NULL, sizeof(instruction));
 }
 /**
 * @brief 	Reset ALL ADAR devices in the SPI chain.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 */
 void Adar_SoftResetAll(const AdarDevice * p_adar)
 {
 	uint8_t instruction[3];
 	instruction[0] = 0x08;
 	instruction[1] = 0x00;
 	instruction[2] = 0x81;
 	p_adar->Transfer(instruction, NULL, sizeof(instruction));
 }
 /**
 * @brief 	Write a byte of @param data to the register located at @param mem_addr.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	mem_addr  	Memory address of the register you wish to read from.
 * @param 	data      	Byte of data to be stored in the register.
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 						if this set to BROADCAST_ON.
 *
 * @warning If writing the same data to multiple registers, use ADAR_WriteBlock.
 */
 void Adar_Write(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data, uint8_t broadcast)
 {
 	uint8_t instruction[3];
 	if (broadcast)
 	{
 		instruction[0] = 0x08;
 	}
 	else
 	{
 		instruction[0] = ((p_adar->dev_addr & 0x03) << 5);
 	}
 	instruction[0] |= (0x1F00 & mem_addr) >> 8;
 	instruction[1] = (0xFF & mem_addr);
 	instruction[2] = data;
 	p_adar->Transfer(instruction, NULL, sizeof(instruction));
 }
 /**
 * @brief 	Block memory write to an ADAR device.
 *
 * @pre 	ADDR_ASCN BITS IN REGISTER ZERO MUST BE SET!
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param	mem_addr 	Memory address of the register you wish to read from.
 * @param	p_data[in]  Pointer to block of data to transfer (must have two unused bytes 
 						preceding the data for instruction).
 * @param	size      	Size of data in bytes, including the two additional leading bytes.
 *
 * @warning First two bytes of data will be corrupted if you do not provide two unused leading bytes!
 */
 void Adar_WriteBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size)
 {
    // Prepare command
 	p_data[0] = ((p_adar->dev_addr & 0x03) << 5);
 	p_data[0] |= ((mem_addr) >> 8) & 0x1F;
 	p_data[1] = (0xFF & mem_addr);
    // Start the transfer
 	p_adar->Transfer(p_data, NULL, size);
    // Return nothing since we assume this is non-blocking and won't wait around
 }
 /**
 * @brief	Set contents of the INTERFACE_CONFIG_A register.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	flags     	#INTERFACE_CONFIG_A_SOFTRESET, #INTERFACE_CONFIG_A_LSB_FIRST,
 *                  	#INTERFACE_CONFIG_A_ADDR_ASCN, #INTERFACE_CONFIG_A_SDO_ACTIVE
 * @param 	broadcast	Send the message as a broadcast to all ADARs in the SPI chain
 *						if this set to BROADCAST_ON.
 */
 void Adar_WriteConfigA(const AdarDevice * p_adar, uint8_t flags, uint8_t broadcast)
 {
 	Adar_Write(p_adar, 0x00, flags, broadcast);
 }
 /**
 * @brief 	Write a byte of @param data to the register located at @param mem_addr and
 *			then read from the device and verify that the register was correctly set.
 *
 * @param	p_adar[in]	Adar pointer Which specifies the device and what function 
 *						to use for SPI transfer.
 * @param 	mem_addr  	Memory address of the register you wish to read from.
 * @param 	data      	Byte of data to be stored in the register.
 *
 * @return	Returns the number of attempts that it took to successfully write to a register,
 *			starting from zero.
 * @warning This function currently only supports writes to a single regiter in a single ADAR.
 */
 uint8_t Adar_WriteVerify(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data)
 {
 	uint8_t rx_data;
 	for (uint8_t ii = 0; ii < 3; ii++)
 	{
 		Adar_Write(p_adar, mem_addr, data, 0);
 		// Can't read back from an ADAR with HW address 0
 		if (!((p_adar->dev_addr) % 4))
 		{
 			return(ADAR_ERROR_INVALIDADDR);
 		}
 		rx_data = Adar_Read(p_adar, mem_addr);
 		if (rx_data == data)
 		{
 			return(ii);
 		}
 	}
 	return(ADAR_ERROR_FAILED);
 }
 void Adar_SetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast)
 	{
 		uint8_t temp = Adar_Read(p_adar, mem_addr);
 		uint8_t data = temp|(1<<bit);
 		Adar_Write(p_adar,mem_addr, data,broadcast);
 	}
 void Adar_ResetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast)
 	{
 		uint8_t temp = Adar_Read(p_adar, mem_addr);
 		uint8_t data = temp&~(1<<bit);
 		Adar_Write(p_adar,mem_addr, data,broadcast);
 	}
@@ -1,294 +0,0 @@
 /**
 * MIT License
 * 
 * Copyright (c) 2020 Jimmy Pentz
 *
 * Reach me at: github.com/jgpentz, jpentz1( at )gmail.com
 * 
 * Permission is hereby granted, free of charge, to any person obtaining a copy
 * of this software and associated documentation files (the "Software"), to deal
 * in the Software without restriction, including without limitation the rights
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sells
 * copies of the Software, and to permit persons to whom the Software is
 * furnished to do so, subject to the following conditions:
 * 
 * The above copyright notice and this permission notice shall be included in all
 * copies or substantial portions of the Software.
 * 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */
 /* ADAR1000 4-Channel, X Band and Ku Band Beamformer */
 #ifndef LIB_ADAR1000_H_
 #define LIB_ADAR1000_H_
 #ifndef NULL
 #define NULL    (0)
 #endif
 // ----------------------------------------------------------------------------
 // Includes
 // ----------------------------------------------------------------------------
 #include "main.h"
 #include "stm32f7xx_hal.h"
 #include "stm32f7xx_hal_spi.h"
 #include "stm32f7xx_hal_gpio.h"
 #include <stdbool.h>
 #include <stdint.h>
 #include <string.h>
 #ifdef __cplusplus
 extern "C" {  // Prevent C++ name mangling
 #endif
 // ----------------------------------------------------------------------------
 // Datatypes
 // ----------------------------------------------------------------------------
 extern SPI_HandleTypeDef hspi1;
 extern const uint8_t VM_GAIN[128];
 extern const uint8_t VM_I[128];
 extern const uint8_t VM_Q[128];
 /// A function pointer prototype for a SPI transfer, the 3 parameters would be
 /// p_txData, p_rxData, and size (number of bytes to transfer), respectively.
 typedef uint32_t (*Adar_SpiTransfer)( uint8_t *, uint8_t *, uint32_t);
 typedef struct
 {
 	uint8_t			 dev_addr; 		///< 2-bit device hardware address, 0x00, 0x01, 0x10, 0x11
 	Adar_SpiTransfer Transfer;		///< Function pointer to the function used for SPI transfers
 	uint8_t *		 p_rx_buffer;	///< Data buffer to store received bytes into
 }const AdarDevice;
 /// Use this to store bias current values into, as seen in the datasheet 
 /// Table 6. SPI Settings for Different Power Modules
 typedef struct
 {
 	uint8_t rx_lna;		///< nominal:  8, low power: 5
 	uint8_t rx_vm;		///< nominal:  5, low power: 2
 	uint8_t rx_vga;		///< nominal: 10, low power: 3
 	uint8_t tx_vm;		///< nominal:  5, low power: 2
 	uint8_t tx_vga;		///< nominal:  5, low power: 5
 	uint8_t tx_drv;		///< nominal:  6, low power: 3
 } AdarBiasCurrents;
 /// Useful for queries regarding the device info
 typedef struct
 {
 	uint8_t	 norm_operating_mode : 2;
 	uint8_t	 cust_operating_mode : 2;
 	uint8_t	 dev_status : 4;
 	uint8_t	 chip_type;
 	uint16_t product_id;
 	uint8_t	 scratchpad;
 	uint8_t	 spi_rev;
 	uint16_t vendor_id;
 	uint8_t	 rev_id;
 } AdarDeviceInfo;
 /// Return types for functions in this library
 typedef enum {
 	ADAR_ERROR_NOERROR		= 0,
 	ADAR_ERROR_FAILED		= 1,
 	ADAR_ERROR_INVALIDADDR	= 2,
 } AdarErrorCodes;
 // ----------------------------------------------------------------------------
 // Function Prototypes
 // ----------------------------------------------------------------------------
 void Adar_AdcInit(const AdarDevice * p_adar, uint8_t broadcast_bit);
 uint8_t Adar_AdcRead(const AdarDevice * p_adar, uint8_t broadcast_bit);
 uint8_t Adar_GetDeviceInfo(const AdarDevice * p_adar, AdarDeviceInfo * info);
 uint8_t Adar_Read(const AdarDevice * p_adar, uint32_t mem_addr);
 void Adar_ReadBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size);
 uint8_t Adar_SetBiasCurrents(const AdarDevice * p_adar, AdarBiasCurrents * p_bias, uint8_t broadcast_bit);
 uint8_t Adar_SetBiasVoltages(const AdarDevice * p_adar, uint8_t bias_on_voltage[5], uint8_t bias_off_voltage[5]);
 uint8_t Adar_SetRamBypass(const AdarDevice * p_adar, uint8_t broadcast_bit);
 uint8_t Adar_SetRxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast_bit);
 uint8_t Adar_SetRxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast_bit);
 uint8_t Adar_SetTxBias(const AdarDevice * p_adar, uint8_t broadcast_bit);
 uint8_t Adar_SetTxVgaGain(const AdarDevice * p_adar, uint8_t channel, uint8_t vga_gain_db, uint8_t broadcast_bit);
 uint8_t Adar_SetTxPhase(const AdarDevice * p_adar, uint8_t channel, uint8_t phase, uint8_t broadcast_bit);
 void Adar_SoftReset(const AdarDevice * p_adar);
 void Adar_SoftResetAll(const AdarDevice * p_adar);
 void Adar_Write(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data, uint8_t broadcast_bit);
 void Adar_WriteBlock(const AdarDevice * p_adar, uint16_t mem_addr, uint8_t * p_data, uint32_t size);
 void Adar_WriteConfigA(const AdarDevice * p_adar, uint8_t flags, uint8_t broadcast);
 uint8_t Adar_WriteVerify(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t data);
 void Adar_SetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast);
 void Adar_ResetBit(const AdarDevice * p_adar, uint32_t mem_addr, uint8_t bit, uint8_t broadcast);
 // ----------------------------------------------------------------------------
 // Preprocessor Definitions and Constants
 // ----------------------------------------------------------------------------
 // Using BROADCAST_ON will send a command to all ADARs that share a bus
 #define BROADCAST_OFF					 0
 #define BROADCAST_ON					 1
 // The minimum size of a read from the ADARs consists of 3 bytes
 #define ADAR1000_RD_SIZE				 3
 // Address at which the TX RAM starts
 #define ADAR_TX_RAM_START_ADDR			 0x1800
 // ADC Defines
 #define ADAR1000_ADC_2MHZ_CLK			 0x00
 #define ADAR1000_ADC_EN					 0x60
 #define ADAR1000_ADC_ST_CONV			 0x70
 /* REGISTER DEFINITIONS */
 #define REG_INTERFACE_CONFIG_A			 0x000
 #define REG_INTERFACE_CONFIG_B			 0x001
 #define REG_DEV_CONFIG					 0x002
 #define REG_SCRATCHPAD					 0x00A
 #define REG_TRANSFER					 0x00F
 #define REG_CH1_RX_GAIN					 0x010
 #define REG_CH2_RX_GAIN					 0x011
 #define REG_CH3_RX_GAIN					 0x012
 #define REG_CH4_RX_GAIN					 0x013
 #define REG_CH1_RX_PHS_I				 0x014
 #define REG_CH1_RX_PHS_Q				 0x015
 #define REG_CH2_RX_PHS_I				 0x016
 #define REG_CH2_RX_PHS_Q				 0x017
 #define REG_CH3_RX_PHS_I				 0x018
 #define REG_CH3_RX_PHS_Q				 0x019
 #define REG_CH4_RX_PHS_I				 0x01A
 #define REG_CH4_RX_PHS_Q				 0x01B
 #define REG_CH1_TX_GAIN					 0x01C
 #define REG_CH2_TX_GAIN					 0x01D
 #define REG_CH3_TX_GAIN					 0x01E
 #define REG_CH4_TX_GAIN					 0x01F
 #define REG_CH1_TX_PHS_I				 0x020
 #define REG_CH1_TX_PHS_Q				 0x021
 #define REG_CH2_TX_PHS_I				 0x022
 #define REG_CH2_TX_PHS_Q				 0x023
 #define REG_CH3_TX_PHS_I				 0x024
 #define REG_CH3_TX_PHS_Q				 0x025
 #define REG_CH4_TX_PHS_I				 0x026
 #define REG_CH4_TX_PHS_Q				 0x027
 #define REG_LOAD_WORKING				 0x028
 #define REG_PA_CH1_BIAS_ON				 0x029
 #define REG_PA_CH2_BIAS_ON				 0x02A
 #define REG_PA_CH3_BIAS_ON				 0x02B
 #define REG_PA_CH4_BIAS_ON				 0x02C
 #define REG_LNA_BIAS_ON					 0x02D
 #define REG_RX_ENABLES					 0x02E
 #define REG_TX_ENABLES					 0x02F
 #define REG_MISC_ENABLES				 0x030
 #define REG_SW_CONTROL					 0x031
 #define REG_ADC_CONTROL					 0x032
 #define REG_ADC_CONTROL_TEMP_EN			 0xf0
 #define REG_ADC_OUT						 0x033
 #define REG_BIAS_CURRENT_RX_LNA			 0x034
 #define REG_BIAS_CURRENT_RX				 0x035
 #define REG_BIAS_CURRENT_TX				 0x036
 #define REG_BIAS_CURRENT_TX_DRV			 0x037
 #define REG_MEM_CTL						 0x038
 #define REG_RX_CHX_MEM					 0x039
 #define REG_TX_CHX_MEM					 0x03A
 #define REG_RX_CH1_MEM					 0x03D
 #define REG_RX_CH2_MEM					 0x03E
 #define REG_RX_CH3_MEM					 0x03F
 #define REG_RX_CH4_MEM					 0x040
 #define REG_TX_CH1_MEM					 0x041
 #define REG_TX_CH2_MEM					 0x042
 #define REG_TX_CH3_MEM					 0x043
 #define REG_TX_CH4_MEM					 0x044
 #define REG_PA_CH1_BIAS_OFF				 0x046
 #define REG_PA_CH2_BIAS_OFF				 0x047
 #define REG_PA_CH3_BIAS_OFF				 0x048
 #define REG_PA_CH4_BIAS_OFF				 0x049
 #define REG_LNA_BIAS_OFF				 0x04A
 #define REG_TX_BEAM_STEP_START			 0x04D
 #define REG_TX_BEAM_STEP_STOP			 0x04E
 #define REG_RX_BEAM_STEP_START			 0x04F
 #define REG_RX_BEAM_STEP_STOP			 0x050
 // REGISTER CONSTANTS
 #define INTERFACE_CONFIG_A_SOFTRESET	 	((1 << 7) | (1 << 0))
 #define INTERFACE_CONFIG_A_LSB_FIRST	 	((1 << 6) | (1 << 1))
 #define INTERFACE_CONFIG_A_ADDR_ASCN	 	((1 << 5) | (1 << 2))
 #define INTERFACE_CONFIG_A_SDO_ACTIVE		((1 << 4) | (1 << 3))
 #define LD_WRK_REGS_LDRX_OVERRIDE		   	(1 << 0)
 #define LD_WRK_REGS_LDTX_OVERRIDE		   	(1 << 1)
 #define RX_ENABLES_TX_VGA_EN			   	(1 << 0)
 #define RX_ENABLES_TX_VM_EN				   	(1 << 1)
 #define RX_ENABLES_TX_DRV_EN			   	(1 << 2)
 #define RX_ENABLES_CH3_TX_EN			   	(1 << 3)
 #define RX_ENABLES_CH2_TX_EN			   	(1 << 4)
 #define RX_ENABLES_CH1_TX_EN			   	(1 << 5)
 #define RX_ENABLES_CH0_TX_EN			   	(1 << 6)
 #define TX_ENABLES_TX_VGA_EN			   	(1 << 0)
 #define TX_ENABLES_TX_VM_EN				   	(1 << 1)
 #define TX_ENABLES_TX_DRV_EN			   	(1 << 2)
 #define TX_ENABLES_CH3_TX_EN			   	(1 << 3)
 #define TX_ENABLES_CH2_TX_EN			   	(1 << 4)
 #define TX_ENABLES_CH1_TX_EN			   	(1 << 5)
 #define TX_ENABLES_CH0_TX_EN			   	(1 << 6)
 #define MISC_ENABLES_CH4_DET_EN			   	(1 << 0)
 #define MISC_ENABLES_CH3_DET_EN			   	(1 << 1)
 #define MISC_ENABLES_CH2_DET_EN			   	(1 << 2)
 #define MISC_ENABLES_CH1_DET_EN			   	(1 << 3)
 #define MISC_ENABLES_LNA_BIAS_OUT_EN	   	(1 << 4)
 #define MISC_ENABLES_BIAS_EN			   	(1 << 5)
 #define MISC_ENABLES_BIAS_CTRL			   	(1 << 6)
 #define MISC_ENABLES_SW_DRV_TR_MODE_SEL	   	(1 << 7)
 #define SW_CTRL_POL						   	(1 << 0)
 #define SW_CTRL_TR_SPI					   	(1 << 1)
 #define SW_CTRL_TR_SOURCE				   	(1 << 2)
 #define SW_CTRL_SW_DRV_EN_POL			   	(1 << 3)
 #define SW_CTRL_SW_DRV_EN_TR			   	(1 << 4)
 #define SW_CTRL_RX_EN					   	(1 << 5)
 #define SW_CTRL_TX_EN					   	(1 << 6)
 #define SW_CTRL_SW_DRV_TR_STATE			   	(1 << 7)
 #define MEM_CTRL_RX_CHX_RAM_BYPASS		   	(1 << 0)
 #define MEM_CTRL_TX_CHX_RAM_BYPASS		   	(1 << 1)
 #define MEM_CTRL_RX_BEAM_STEP_EN		   	(1 << 2)
 #define MEM_CTRL_TX_BEAM_STEP_EN		   	(1 << 3)
 #define MEM_CTRL_BIAS_RAM_BYPASS		   	(1 << 5)
 #define MEM_CTRL_BEAM_RAM_BYPASS		   	(1 << 6)
 #define MEM_CTRL_SCAN_MODE_EN			   	(1 << 7)
 #ifdef __cplusplus
 }  // End extern "C"
 #endif
 #endif /* LIB_ADAR1000_H_ */
@@ -112,7 +112,7 @@ extern "C" {
 *   "BF"    -- ADAR1000 beamformer
 *   "PA"    -- Power amplifier bias/monitoring
 *   "FPGA"  -- FPGA communication and handshake
- *   "USB"   -- FT601 USB data path
+ *   "USB"   -- USB data path (FT2232H production / FT601 premium)
 *   "PWR"   -- Power sequencing and rail monitoring
 *   "IMU"   -- IMU/GPS/barometer sensors
 *   "MOT"   -- Stepper motor/scan mechanics
@@ -21,7 +21,6 @@
 #include "usb_device.h"
 #include "USBHandler.h"
 #include "usbd_cdc_if.h"
 #include "adar1000.h"
 #include "ADAR1000_Manager.h"
 #include "ADAR1000_AGC.h"
 extern "C" {
@@ -46,7 +45,9 @@ extern "C" {
 #include <vector>
 #include "stm32_spi.h"
 #include "stm32_delay.h"
-#include "TinyGPSPlus.h"
+extern "C" {
 #include "um982_gps.h"
 }
 extern "C" {
 #include "GY_85_HAL.h"
 }
@@ -121,8 +122,8 @@ UART_HandleTypeDef huart5;
 UART_HandleTypeDef huart3;
 /* USER CODE BEGIN PV */
-// The TinyGPSPlus object
+// UM982 dual-antenna GPS receiver
-TinyGPSPlus gps;
+UM982_GPS_t um982;
 // Global data structures
 GPS_Data_t current_gps_data = {0};
@@ -173,7 +174,7 @@ float RADAR_Altitude;
 double RADAR_Longitude = 0;
 double RADAR_Latitude = 0;
-extern uint8_t GUI_start_flag_received;
+extern uint8_t GUI_start_flag_received;  // [STM32-006] Legacy, unused -- kept for linker compat
 //RADAR
@@ -620,17 +621,39 @@ typedef enum {
    ERROR_POWER_SUPPLY,
    ERROR_TEMPERATURE_HIGH,
    ERROR_MEMORY_ALLOC,
-    ERROR_WATCHDOG_TIMEOUT
+    ERROR_WATCHDOG_TIMEOUT,
    ERROR_COUNT  // must be last — used for bounds checking error_strings[]
 } SystemError_t;
 static SystemError_t last_error = ERROR_NONE;
 static uint32_t error_count = 0;
-static bool system_emergency_state = false;
+static volatile bool system_emergency_state = false;
 // Error handler function
 SystemError_t checkSystemHealth(void) {
    SystemError_t current_error = ERROR_NONE;
    // 0. Watchdog: detect main-loop stall (checkSystemHealth not called for >60 s).
    //    Timestamp is captured at function ENTRY and updated unconditionally, so
    //    any early return from a sub-check below cannot leave a stale value that
    //    would later trip a spurious ERROR_WATCHDOG_TIMEOUT. A dedicated cold-start
    //    branch ensures the first call after boot never trips (last_health_check==0
    //    would otherwise make `HAL_GetTick() - 0 > 60000` true forever after the
    //    60-s mark of the init sequence).
    static uint32_t last_health_check = 0;
    uint32_t now_tick = HAL_GetTick();
    if (last_health_check == 0) {
        last_health_check = now_tick;          // cold start: seed only
    } else {
        uint32_t elapsed = now_tick - last_health_check;
        last_health_check = now_tick;          // update BEFORE any early return
        if (elapsed > 60000) {
            current_error = ERROR_WATCHDOG_TIMEOUT;
            DIAG_ERR("SYS", "Health check: Watchdog timeout (>60s since last check)");
            return current_error;
        }
    }
    // 1. Check AD9523 Clock Generator
    static uint32_t last_clock_check = 0;
    if (HAL_GetTick() - last_clock_check > 5000) {
@@ -700,14 +723,11 @@ SystemError_t checkSystemHealth(void) {
        last_bmp_check = HAL_GetTick();
    }
-    // 6. Check GPS Communication
+    // 6. Check GPS Communication (30s grace period from boot / last valid fix)
-    static uint32_t last_gps_fix = 0;
+    uint32_t gps_fix_age = um982_position_age(&um982);
-    if (gps.location.isUpdated()) {
+    if (gps_fix_age > 30000) {
        last_gps_fix = HAL_GetTick();
    }
    if (HAL_GetTick() - last_gps_fix > 30000) {
        current_error = ERROR_GPS_COMM;
-        DIAG_WARN("SYS", "Health check: GPS no fix for >30s");
+        DIAG_WARN("SYS", "Health check: GPS no fix for >30s (age=%lu ms)", (unsigned long)gps_fix_age);
        return current_error;
    }
@@ -734,14 +754,7 @@ SystemError_t checkSystemHealth(void) {
        return current_error;
    }
-    // 9. Simple watchdog check
+    // 9. Watchdog check is performed at function entry (see step 0).
    static uint32_t last_health_check = 0;
    if (HAL_GetTick() - last_health_check > 60000) {
        current_error = ERROR_WATCHDOG_TIMEOUT;
        DIAG_ERR("SYS", "Health check: Watchdog timeout (>60s since last check)");
        return current_error;
    }
    last_health_check = HAL_GetTick();
    if (current_error != ERROR_NONE) {
        DIAG_ERR("SYS", "checkSystemHealth returning error code %d", current_error);
@@ -853,7 +866,7 @@ void handleSystemError(SystemError_t error) {
    DIAG_ERR("SYS", "handleSystemError: error=%d error_count=%lu", error, error_count);
    char error_msg[100];
-    const char* error_strings[] = {
+    static const char* const error_strings[] = {
        "No error",
        "AD9523 Clock failure",
        "ADF4382 TX LO unlocked",
@@ -873,9 +886,16 @@ void handleSystemError(SystemError_t error) {
        "Watchdog timeout"
    };
    static_assert(sizeof(error_strings) / sizeof(error_strings[0]) == ERROR_COUNT,
                  "error_strings[] and SystemError_t enum are out of sync");
    const char* err_name = (error >= 0 && error < (int)(sizeof(error_strings) / sizeof(error_strings[0])))
                           ? error_strings[error]
                           : "Unknown error";
    snprintf(error_msg, sizeof(error_msg),
             "ERROR #%d: %s (Count: %lu)\r\n",
-             error, error_strings[error], error_count);
+             error, err_name, error_count);
    HAL_UART_Transmit(&huart3, (uint8_t*)error_msg, strlen(error_msg), 1000);
    // Blink LED pattern based on error code
@@ -901,7 +921,7 @@ void handleSystemError(SystemError_t error) {
    if ((error >= ERROR_RF_PA_OVERCURRENT && error <= ERROR_POWER_SUPPLY) ||
        error == ERROR_TEMPERATURE_HIGH ||
        error == ERROR_WATCHDOG_TIMEOUT) {
-        DIAG_ERR("SYS", "CRITICAL ERROR (code %d: %s) -- initiating Emergency_Stop()", error, error_strings[error]);
+        DIAG_ERR("SYS", "CRITICAL ERROR (code %d: %s) -- initiating Emergency_Stop()", error, err_name);
        snprintf(error_msg, sizeof(error_msg),
                 "CRITICAL ERROR! Initiating emergency shutdown.\r\n");
        HAL_UART_Transmit(&huart3, (uint8_t*)error_msg, strlen(error_msg), 1000);
@@ -1034,20 +1054,7 @@ static inline void delay_ms(uint32_t ms) { HAL_Delay(ms); }
-// This custom version of delay() ensures that the gps object
+// smartDelay removed -- replaced by non-blocking um982_process() in main loop
 // is being "fed".
 static void smartDelay(unsigned long ms)
 {
    uint32_t start = HAL_GetTick();
    uint8_t ch;
    do {
        // While there is new data available in UART (non-blocking)
        if (HAL_UART_Receive(&huart5, &ch, 1, 0) == HAL_OK) {
            gps.encode(ch);   // Pass received byte to TinyGPS++ equivalent parser
        }
    } while (HAL_GetTick() - start < ms);
 }
 // Small helper to enable DWT cycle counter for microdelay
 static void DWT_Init(void)
@@ -1191,7 +1198,14 @@ static int configure_ad9523(void)
    // init ad9523 defaults (fills any missing pdata defaults)
    DIAG("CLK", "Calling ad9523_init() -- fills pdata defaults");
-    ad9523_init(&init_param);
+    {
        int32_t init_ret = ad9523_init(&init_param);
        DIAG("CLK", "ad9523_init() returned %ld", (long)init_ret);
        if (init_ret != 0) {
            DIAG_ERR("CLK", "ad9523_init() FAILED (ret=%ld)", (long)init_ret);
            return -1;
        }
    }
    /* [Bug #2 FIXED] Removed first ad9523_setup() call that was here.
     * It wrote to the chip while still in reset — writes were lost.
@@ -1580,6 +1594,12 @@ int main(void)
    Yaw_Sensor = (180*atan2(magRawY,magRawX)/PI) - Mag_Declination;
    if(Yaw_Sensor<0)Yaw_Sensor+=360;
    // Override magnetometer heading with UM982 dual-antenna heading when available
    if (um982_is_heading_valid(&um982)) {
        Yaw_Sensor = um982_get_heading(&um982);
    }
    RxEst_0 = RxEst_1;
    RyEst_0 = RyEst_1;
    RzEst_0 = RzEst_1;
@@ -1755,10 +1775,34 @@ int main(void)
  	//////////////////////////////////////////////////////////////////////////////////////
    //////////////////////////////////////////GPS/////////////////////////////////////////
    //////////////////////////////////////////////////////////////////////////////////////
-  for(int i=0; i<10;i++){
+  DIAG_SECTION("GPS INIT (UM982)");
-  smartDelay(1000);
+  DIAG("GPS", "Initializing UM982 on UART5 @ 115200 (baseline=50cm, tol=3cm)");
-  RADAR_Longitude = gps.location.lng();
+  if (!um982_init(&um982, &huart5, 50.0f, 3.0f)) {
-  RADAR_Latitude = gps.location.lat();
+      DIAG_WARN("GPS", "UM982 init: no VERSIONA response -- module may need more time");
      // Not fatal: module may still start sending NMEA data after boot
  } else {
      DIAG("GPS", "UM982 init OK -- VERSIONA received");
  }
  // Collect GPS data for a few seconds (non-blocking pump)
  DIAG("GPS", "Pumping GPS for 5 seconds to acquire initial fix...");
  {
      uint32_t gps_start = HAL_GetTick();
      while (HAL_GetTick() - gps_start < 5000) {
          um982_process(&um982);
          HAL_Delay(10);
      }
  }
  RADAR_Longitude = um982_get_longitude(&um982);
  RADAR_Latitude = um982_get_latitude(&um982);
  DIAG("GPS", "Initial position: lat=%.6f lon=%.6f fix=%d sats=%d",
       RADAR_Latitude, RADAR_Longitude,
       um982_get_fix_quality(&um982), um982_get_num_sats(&um982));
  // Re-apply heading after GPS init so the north-alignment stepper move uses
  // UM982 dual-antenna heading when available.
  if (um982_is_heading_valid(&um982)) {
      Yaw_Sensor = um982_get_heading(&um982);
  }
  //move Stepper to position 1 = 0°
@@ -1784,29 +1828,11 @@ int main(void)
      HAL_UART_Transmit(&huart3, (uint8_t*)gps_send_error, sizeof(gps_send_error) - 1, 1000);
  }
-  // Check if start flag was received and settings are ready
+  /* [STM32-006 FIXED] Removed blocking do-while loop that waited for
-  do{
+   * usbHandler.isStartFlagReceived().  The production V7 PyQt GUI does not
-	  if (usbHandler.isStartFlagReceived() &&
+   * send the legacy 4-byte start flag [23,46,158,237], so this loop hung
-		  usbHandler.getState() == USBHandler::USBState::READY_FOR_DATA) {
+   * the MCU at boot indefinitely.  The USB settings handshake (if ever
-
+   * re-enabled) should be handled non-blocking in the main loop. */
 		  const RadarSettings& settings = usbHandler.getSettings();
 		  // Use the settings to configure your radar system
 		  /*
 			  settings.getSystemFrequency();
 			  settings.getChirpDuration1();
 			  settings.getChirpDuration2();
 			  settings.getChirpsPerPosition();
 			  settings.getFreqMin();
 			  settings.getFreqMax();
 			  settings.getPRF1();
 			  settings.getPRF2();
 			  settings.getMaxDistance();
 			  */
              }
  }while(!usbHandler.isStartFlagReceived());
  /***************************************************************/
  /************RF Power Amplifier Powering up sequence************/
@@ -2028,9 +2054,25 @@ int main(void)
 	            HAL_GPIO_TogglePin(LED_3_GPIO_Port, LED_3_Pin);
 	            HAL_GPIO_TogglePin(LED_4_GPIO_Port, LED_4_Pin);
 	            HAL_Delay(250);
 	            if (usbHandler.isFaultAckReceived()) {
 	                system_emergency_state = false;
 	                usbHandler.clearFaultAck();
 	            }
 	        }
 	        DIAG("SYS", "Exited safe mode blink loop -- system_emergency_state cleared");
 	    }
 	  //////////////////////////////////////////////////////////////////////////////////////
 	  ////////////////////////// GPS: Non-blocking NMEA processing ////////////////////////
 	  //////////////////////////////////////////////////////////////////////////////////////
 	  um982_process(&um982);
 	  // Update position globals continuously
 	  if (um982_is_position_valid(&um982)) {
 	      RADAR_Latitude = um982_get_latitude(&um982);
 	      RADAR_Longitude = um982_get_longitude(&um982);
 	  }
 	  //////////////////////////////////////////////////////////////////////////////////////
 	  ////////////////////////// Monitor ADF4382A lock status periodically//////////////////
 	  //////////////////////////////////////////////////////////////////////////////////////
@@ -2141,9 +2183,24 @@ int main(void)
      runRadarPulseSequence();
-      /* [AGC] Outer-loop AGC: read FPGA saturation flag (DIG_5 / PD13),
+      /* [AGC] Outer-loop AGC: sync enable from FPGA via DIG_6 (PD14),
-       * adjust ADAR1000 VGA common gain once per radar frame (~258 ms).
+       * then read saturation flag (DIG_5 / PD13) and adjust ADAR1000 VGA
-       * Only run when AGC is enabled — otherwise leave VGA gains untouched. */
+       * common gain once per radar frame (~258 ms).
       * FPGA register host_agc_enable is the single source of truth —
       * DIG_6 propagates it to MCU every frame.
       * 2-frame confirmation debounce: only change outerAgc.enabled when
       * two consecutive frames read the same DIG_6 value. Prevents a
       * single-sample glitch from causing a spurious AGC state transition.
       * Added latency: 1 extra frame (~258 ms), acceptable for control plane. */
      {
          bool dig6_now = (HAL_GPIO_ReadPin(FPGA_DIG6_GPIO_Port,
                                            FPGA_DIG6_Pin) == GPIO_PIN_SET);
          static bool dig6_prev = false;  // matches boot default (AGC off)
          if (dig6_now == dig6_prev) {
              outerAgc.enabled = dig6_now;
          }
          dig6_prev = dig6_now;
      }
      if (outerAgc.enabled) {
          bool sat = HAL_GPIO_ReadPin(FPGA_DIG5_SAT_GPIO_Port,
                                      FPGA_DIG5_SAT_Pin) == GPIO_PIN_SET;
@@ -2581,7 +2638,7 @@ static void MX_UART5_Init(void)
  /* USER CODE END UART5_Init 1 */
  huart5.Instance = UART5;
-  huart5.Init.BaudRate = 9600;
+  huart5.Init.BaudRate = 115200;
  huart5.Init.WordLength = UART_WORDLENGTH_8B;
  huart5.Init.StopBits = UART_STOPBITS_1;
  huart5.Init.Parity = UART_PARITY_NONE;
@@ -0,0 +1,586 @@
 /*******************************************************************************
 * um982_gps.c -- UM982 dual-antenna GNSS receiver driver implementation
 *
 * See um982_gps.h for API documentation.
 * Command syntax per Unicore N4 Command Reference EN R1.14.
 ******************************************************************************/
 #include "um982_gps.h"
 #include <string.h>
 #include <stdlib.h>
 #include <stdio.h>
 /* ========================= Internal helpers ========================== */
 /**
 * Advance to the next comma-delimited field in an NMEA sentence.
 * Returns pointer to the start of the next field (after the comma),
 * or NULL if no more commas found before end-of-string or '*'.
 *
 * Handles empty fields (consecutive commas) correctly by returning
 * a pointer to the character after the comma (which may be another comma).
 */
 static const char *next_field(const char *p)
 {
    if (p == NULL) return NULL;
    while (*p != '\0' && *p != ',' && *p != '*') {
        p++;
    }
    if (*p == ',') return p + 1;
    return NULL;  /* End of sentence or checksum marker */
 }
 /**
 * Get the length of the current field (up to next comma, '*', or '\0').
 */
 static int field_len(const char *p)
 {
    int len = 0;
    if (p == NULL) return 0;
    while (p[len] != '\0' && p[len] != ',' && p[len] != '*') {
        len++;
    }
    return len;
 }
 /**
 * Check if a field is non-empty (has at least one character before delimiter).
 */
 static bool field_valid(const char *p)
 {
    return p != NULL && field_len(p) > 0;
 }
 /**
 * Parse a floating-point value from a field, returning 0.0 if empty.
 */
 static double field_to_double(const char *p)
 {
    if (!field_valid(p)) return 0.0;
    return strtod(p, NULL);
 }
 static float field_to_float(const char *p)
 {
    return (float)field_to_double(p);
 }
 static int field_to_int(const char *p)
 {
    if (!field_valid(p)) return 0;
    return (int)strtol(p, NULL, 10);
 }
 /* ========================= Checksum ================================== */
 bool um982_verify_checksum(const char *sentence)
 {
    if (sentence == NULL || sentence[0] != '$') return false;
    const char *p = sentence + 1;  /* Skip '$' */
    uint8_t computed = 0;
    while (*p != '\0' && *p != '*') {
        computed ^= (uint8_t)*p;
        p++;
    }
    if (*p != '*') return false;  /* No checksum marker found */
    p++;  /* Skip '*' */
    /* Parse 2-char hex checksum */
    if (p[0] == '\0' || p[1] == '\0') return false;
    char hex_str[3] = { p[0], p[1], '\0' };
    unsigned long expected = strtoul(hex_str, NULL, 16);
    return computed == (uint8_t)expected;
 }
 /* ========================= Coordinate parsing ======================== */
 double um982_parse_coord(const char *field, char hemisphere)
 {
    if (field == NULL || field[0] == '\0') return NAN;
    /* Find the decimal point to determine degree digit count.
     * Latitude:  ddmm.mmmm  (dot at index 4, degrees = 2)
     * Longitude: dddmm.mmmm (dot at index 5, degrees = 3)
     * General:   degree_digits = dot_position - 2
     */
    const char *dot = strchr(field, '.');
    if (dot == NULL) return NAN;
    int dot_pos = (int)(dot - field);
    int deg_digits = dot_pos - 2;
    if (deg_digits < 1 || deg_digits > 3) return NAN;
    /* Extract degree portion */
    double degrees = 0.0;
    for (int i = 0; i < deg_digits; i++) {
        if (field[i] < '0' || field[i] > '9') return NAN;
        degrees = degrees * 10.0 + (field[i] - '0');
    }
    /* Extract minutes portion (everything from deg_digits onward) */
    double minutes = strtod(field + deg_digits, NULL);
    if (minutes < 0.0 || minutes >= 60.0) return NAN;
    double result = degrees + minutes / 60.0;
    /* Apply hemisphere sign */
    if (hemisphere == 'S' || hemisphere == 'W') {
        result = -result;
    }
    return result;
 }
 /* ========================= Sentence parsers ========================== */
 /**
 * Identify the NMEA sentence type by skipping the 2-char talker ID
 * and comparing the 3-letter formatter.
 *
 * "$GNGGA,..." -> talker="GN", formatter="GGA"
 * "$GPTHS,..." -> talker="GP", formatter="THS"
 *
 * Returns pointer to the formatter (3 chars at sentence+3), or NULL
 * if sentence is too short.
 */
 static const char *get_formatter(const char *sentence)
 {
    /* sentence starts with '$', followed by 2-char talker + 3-char formatter */
    if (sentence == NULL || strlen(sentence) < 6) return NULL;
    return sentence + 3;  /* Skip "$XX" -> points to formatter */
 }
 /**
 * Parse GGA sentence — position and fix quality.
 *
 * Format: $--GGA,time,lat,N/S,lon,E/W,quality,numSat,hdop,alt,M,geoidSep,M,dgpsAge,refID*XX
 *         field:  1    2   3    4   5     6      7     8    9 10    11    12   13     14
 */
 static void parse_gga(UM982_GPS_t *gps, const char *sentence)
 {
    /* Skip to first field (after "$XXGGA,") */
    const char *f = strchr(sentence, ',');
    if (f == NULL) return;
    f++;  /* f -> field 1 (time) */
    /* Field 1: UTC time — skip for now */
    const char *f2 = next_field(f);   /* lat */
    const char *f3 = next_field(f2);  /* N/S */
    const char *f4 = next_field(f3);  /* lon */
    const char *f5 = next_field(f4);  /* E/W */
    const char *f6 = next_field(f5);  /* quality */
    const char *f7 = next_field(f6);  /* numSat */
    const char *f8 = next_field(f7);  /* hdop */
    const char *f9 = next_field(f8);  /* altitude */
    const char *f10 = next_field(f9); /* M */
    const char *f11 = next_field(f10); /* geoid sep */
    uint32_t now = HAL_GetTick();
    /* Parse fix quality first — if 0, position is meaningless */
    gps->fix_quality = (uint8_t)field_to_int(f6);
    /* Parse coordinates */
    if (field_valid(f2) && field_valid(f3)) {
        char hem = field_valid(f3) ? *f3 : 'N';
        double lat = um982_parse_coord(f2, hem);
        if (!isnan(lat)) gps->latitude = lat;
    }
    if (field_valid(f4) && field_valid(f5)) {
        char hem = field_valid(f5) ? *f5 : 'E';
        double lon = um982_parse_coord(f4, hem);
        if (!isnan(lon)) gps->longitude = lon;
    }
    /* Number of satellites */
    gps->num_satellites = (uint8_t)field_to_int(f7);
    /* HDOP */
    if (field_valid(f8)) {
        gps->hdop = field_to_float(f8);
    }
    /* Altitude */
    if (field_valid(f9)) {
        gps->altitude = field_to_float(f9);
    }
    /* Geoid separation */
    if (field_valid(f11)) {
        gps->geoid_sep = field_to_float(f11);
    }
    gps->last_gga_tick = now;
    if (gps->fix_quality != UM982_FIX_NONE) {
        gps->last_fix_tick = now;
    }
 }
 /**
 * Parse RMC sentence — recommended minimum (position, speed, date).
 *
 * Format: $--RMC,time,status,lat,N/S,lon,E/W,speed,course,date,magVar,E/W,mode*XX
 *         field:  1     2      3   4   5   6    7      8     9    10    11   12
 */
 static void parse_rmc(UM982_GPS_t *gps, const char *sentence)
 {
    const char *f = strchr(sentence, ',');
    if (f == NULL) return;
    f++;  /* f -> field 1 (time) */
    const char *f2 = next_field(f);   /* status */
    const char *f3 = next_field(f2);  /* lat */
    const char *f4 = next_field(f3);  /* N/S */
    const char *f5 = next_field(f4);  /* lon */
    const char *f6 = next_field(f5);  /* E/W */
    const char *f7 = next_field(f6);  /* speed knots */
    const char *f8 = next_field(f7);  /* course true */
    /* Status */
    if (field_valid(f2)) {
        gps->rmc_status = *f2;
    }
    /* Position (only if status = A for valid) */
    if (field_valid(f2) && *f2 == 'A') {
        if (field_valid(f3) && field_valid(f4)) {
            double lat = um982_parse_coord(f3, *f4);
            if (!isnan(lat)) gps->latitude = lat;
        }
        if (field_valid(f5) && field_valid(f6)) {
            double lon = um982_parse_coord(f5, *f6);
            if (!isnan(lon)) gps->longitude = lon;
        }
    }
    /* Speed (knots) */
    if (field_valid(f7)) {
        gps->speed_knots = field_to_float(f7);
    }
    /* Course */
    if (field_valid(f8)) {
        gps->course_true = field_to_float(f8);
    }
    gps->last_rmc_tick = HAL_GetTick();
 }
 /**
 * Parse THS sentence — true heading and status (UM982-specific).
 *
 * Format: $--THS,heading,mode*XX
 *         field:    1      2
 */
 static void parse_ths(UM982_GPS_t *gps, const char *sentence)
 {
    const char *f = strchr(sentence, ',');
    if (f == NULL) return;
    f++;  /* f -> field 1 (heading) */
    const char *f2 = next_field(f);  /* mode */
    /* Heading */
    if (field_valid(f)) {
        gps->heading = field_to_float(f);
    } else {
        gps->heading = NAN;
    }
    /* Mode */
    if (field_valid(f2)) {
        gps->heading_mode = *f2;
    } else {
        gps->heading_mode = 'V';  /* Not valid if missing */
    }
    gps->last_ths_tick = HAL_GetTick();
 }
 /**
 * Parse VTG sentence — course and speed over ground.
 *
 * Format: $--VTG,courseTrue,T,courseMag,M,speedKnots,N,speedKmh,K,mode*XX
 *         field:     1      2     3      4     5      6    7     8   9
 */
 static void parse_vtg(UM982_GPS_t *gps, const char *sentence)
 {
    const char *f = strchr(sentence, ',');
    if (f == NULL) return;
    f++;  /* f -> field 1 (course true) */
    const char *f2 = next_field(f);   /* T */
    const char *f3 = next_field(f2);  /* course mag */
    const char *f4 = next_field(f3);  /* M */
    const char *f5 = next_field(f4);  /* speed knots */
    const char *f6 = next_field(f5);  /* N */
    const char *f7 = next_field(f6);  /* speed km/h */
    /* Course true */
    if (field_valid(f)) {
        gps->course_true = field_to_float(f);
    }
    /* Speed knots */
    if (field_valid(f5)) {
        gps->speed_knots = field_to_float(f5);
    }
    /* Speed km/h */
    if (field_valid(f7)) {
        gps->speed_kmh = field_to_float(f7);
    }
    gps->last_vtg_tick = HAL_GetTick();
 }
 /* ========================= Sentence dispatch ========================= */
 void um982_parse_sentence(UM982_GPS_t *gps, const char *sentence)
 {
    if (sentence == NULL || sentence[0] != '$') return;
    /* Verify checksum before parsing */
    if (!um982_verify_checksum(sentence)) return;
    /* Check for VERSIONA response (starts with '#', not '$') -- handled separately */
    /* Actually VERSIONA starts with '#', so it won't enter here. We check in feed(). */
    /* Identify sentence type */
    const char *fmt = get_formatter(sentence);
    if (fmt == NULL) return;
    if (strncmp(fmt, "GGA", 3) == 0) {
        gps->initialized = true;
        parse_gga(gps, sentence);
    } else if (strncmp(fmt, "RMC", 3) == 0) {
        gps->initialized = true;
        parse_rmc(gps, sentence);
    } else if (strncmp(fmt, "THS", 3) == 0) {
        gps->initialized = true;
        parse_ths(gps, sentence);
    } else if (strncmp(fmt, "VTG", 3) == 0) {
        gps->initialized = true;
        parse_vtg(gps, sentence);
    }
    /* Other sentences silently ignored */
 }
 /* ========================= Command interface ========================= */
 bool um982_send_command(UM982_GPS_t *gps, const char *cmd)
 {
    if (gps == NULL || gps->huart == NULL || cmd == NULL) return false;
    /* Build command with \r\n termination */
    char buf[UM982_CMD_BUF_SIZE];
    int len = snprintf(buf, sizeof(buf), "%s\r\n", cmd);
    if (len <= 0 || (size_t)len >= sizeof(buf)) return false;
    HAL_StatusTypeDef status = HAL_UART_Transmit(
        gps->huart, (const uint8_t *)buf, (uint16_t)len, 100);
    return status == HAL_OK;
 }
 /* ========================= Line assembly + feed ====================== */
 /**
 * Process a completed line from the line buffer.
 */
 static void process_line(UM982_GPS_t *gps, const char *line)
 {
    if (line == NULL || line[0] == '\0') return;
    /* NMEA sentence starts with '$' */
    if (line[0] == '$') {
        um982_parse_sentence(gps, line);
        return;
    }
    /* Unicore proprietary response starts with '#' (e.g. #VERSIONA) */
    if (line[0] == '#') {
        if (strncmp(line + 1, "VERSIONA", 8) == 0) {
            gps->version_received = true;
            gps->initialized = true;
        }
        return;
    }
 }
 void um982_feed(UM982_GPS_t *gps, const uint8_t *data, uint16_t len)
 {
    if (gps == NULL || data == NULL || len == 0) return;
    for (uint16_t i = 0; i < len; i++) {
        uint8_t ch = data[i];
        /* End of line: process if we have content */
        if (ch == '\n' || ch == '\r') {
            if (gps->line_len > 0 && !gps->line_overflow) {
                gps->line_buf[gps->line_len] = '\0';
                process_line(gps, gps->line_buf);
            }
            gps->line_len = 0;
            gps->line_overflow = false;
            continue;
        }
        /* Accumulate into line buffer */
        if (gps->line_len < UM982_LINE_BUF_SIZE - 1) {
            gps->line_buf[gps->line_len++] = (char)ch;
        } else {
            gps->line_overflow = true;
        }
    }
 }
 /* ========================= UART process (production) ================= */
 void um982_process(UM982_GPS_t *gps)
 {
    if (gps == NULL || gps->huart == NULL) return;
    /* Read all available bytes from the UART one at a time.
     * At 115200 baud (~11.5 KB/s) and a typical main-loop period of ~10 ms,
     * we expect ~115 bytes per call — negligible overhead on a 168 MHz STM32.
     *
     * Note: batch reads (HAL_UART_Receive with Size > 1 and Timeout = 0) are
     * NOT safe here because the HAL consumes bytes from the data register as
     * it reads them.  If fewer than Size bytes are available, the consumed
     * bytes are lost (HAL_TIMEOUT is returned and the caller has no way to
     * know how many bytes were actually placed into the buffer). */
    uint8_t ch;
    while (HAL_UART_Receive(gps->huart, &ch, 1, 0) == HAL_OK) {
        um982_feed(gps, &ch, 1);
    }
 }
 /* ========================= Validity checks =========================== */
 bool um982_is_heading_valid(const UM982_GPS_t *gps)
 {
    if (gps == NULL) return false;
    if (isnan(gps->heading)) return false;
    /* Mode must be Autonomous or Differential */
    if (gps->heading_mode != 'A' && gps->heading_mode != 'D') return false;
    /* Check age */
    uint32_t age = HAL_GetTick() - gps->last_ths_tick;
    return age < UM982_HEADING_TIMEOUT_MS;
 }
 bool um982_is_position_valid(const UM982_GPS_t *gps)
 {
    if (gps == NULL) return false;
    if (gps->fix_quality == UM982_FIX_NONE) return false;
    /* Check age of the last valid fix */
    uint32_t age = HAL_GetTick() - gps->last_fix_tick;
    return age < UM982_POSITION_TIMEOUT_MS;
 }
 uint32_t um982_heading_age(const UM982_GPS_t *gps)
 {
    if (gps == NULL) return UINT32_MAX;
    return HAL_GetTick() - gps->last_ths_tick;
 }
 uint32_t um982_position_age(const UM982_GPS_t *gps)
 {
    if (gps == NULL) return UINT32_MAX;
    return HAL_GetTick() - gps->last_fix_tick;
 }
 /* ========================= Initialization ============================ */
 bool um982_init(UM982_GPS_t *gps, UART_HandleTypeDef *huart,
                float baseline_cm, float tolerance_cm)
 {
    if (gps == NULL || huart == NULL) return false;
    /* Zero-init entire structure */
    memset(gps, 0, sizeof(UM982_GPS_t));
    gps->huart = huart;
    gps->heading = NAN;
    gps->heading_mode = 'V';
    gps->rmc_status = 'V';
    gps->speed_knots = 0.0f;
    /* Seed fix timestamp so position_age() returns ~0 instead of uptime.
     * Gives the module a full 30s grace window from init to acquire a fix
     * before the health check fires ERROR_GPS_COMM. */
    gps->last_fix_tick = HAL_GetTick();
    gps->speed_kmh = 0.0f;
    gps->course_true = 0.0f;
    /* Step 1: Stop all current output to get a clean slate */
    um982_send_command(gps, "UNLOG");
    HAL_Delay(100);
    /* Step 2: Configure heading mode
     * Per N4 Reference 4.18: CONFIG HEADING FIXLENGTH (default mode)
     * "The distance between ANT1 and ANT2 is fixed. They move synchronously." */
    um982_send_command(gps, "CONFIG HEADING FIXLENGTH");
    HAL_Delay(50);
    /* Step 3: Set baseline length if specified
     * Per N4 Reference: CONFIG HEADING LENGTH <cm> <tolerance_cm>
     * "parameter1: Fixed baseline length (cm), valid range >= 0"
     * "parameter2: Tolerable error margin (cm), valid range > 0" */
    if (baseline_cm > 0.0f) {
        char cmd[64];
        if (tolerance_cm > 0.0f) {
            snprintf(cmd, sizeof(cmd), "CONFIG HEADING LENGTH %.0f %.0f",
                     baseline_cm, tolerance_cm);
        } else {
            snprintf(cmd, sizeof(cmd), "CONFIG HEADING LENGTH %.0f",
                     baseline_cm);
        }
        um982_send_command(gps, cmd);
        HAL_Delay(50);
    }
    /* Step 4: Enable NMEA output sentences on COM2.
     * Per N4 Reference: "When requesting NMEA messages, users should add GP
     * before each command name"
     *
     * We target COM2 because the ELT0213 board (GNSS.STORE) exposes COM2
     * (RXD2/TXD2) on its 12-pin JST connector (pins 5 & 6).  The STM32
     * UART5 (PC12-TX, PD2-RX) connects to these pins via JP8.
     * COM2 defaults to 115200 baud — matching our UART5 config. */
    um982_send_command(gps, "GPGGA COM2 1");     /* GGA at 1 Hz */
    HAL_Delay(50);
    um982_send_command(gps, "GPRMC COM2 1");     /* RMC at 1 Hz */
    HAL_Delay(50);
    um982_send_command(gps, "GPTHS COM2 0.2");   /* THS at 5 Hz (heading primary) */
    HAL_Delay(50);
    /* Step 5: Skip SAVECONFIG -- NMEA config is re-sent every boot anyway.
     * Saving to NVM on every power cycle would wear flash.  If persistent
     * config is needed, call um982_send_command(gps, "SAVECONFIG") once
     * during commissioning. */
    /* Step 6: Query version to verify communication */
    gps->version_received = false;
    um982_send_command(gps, "VERSIONA");
    /* Wait for VERSIONA response (non-blocking poll) */
    uint32_t start = HAL_GetTick();
    while (!gps->version_received &&
           (HAL_GetTick() - start) < UM982_INIT_TIMEOUT_MS) {
        um982_process(gps);
        HAL_Delay(10);
    }
    gps->initialized = gps->version_received;
    return gps->initialized;
 }
@@ -0,0 +1,213 @@
 /*******************************************************************************
 * um982_gps.h -- UM982 dual-antenna GNSS receiver driver
 *
 * Parses NMEA sentences (GGA, RMC, THS, VTG) from the Unicore UM982 module
 * and provides position, heading, and velocity data.
 *
 * Design principles:
 *   - Non-blocking: process() reads available UART bytes without waiting
 *   - Correct NMEA parsing: proper tokenizer handles empty fields
 *   - Longitude handles 3-digit degrees (dddmm.mmmm) via decimal-point detection
 *   - Checksum verified on every sentence
 *   - Command syntax verified against Unicore N4 Command Reference EN R1.14
 *
 * Hardware: UM982 on UART5 @ 115200 baud, dual-antenna heading mode
 ******************************************************************************/
 #ifndef UM982_GPS_H
 #define UM982_GPS_H
 #include <stdint.h>
 #include <stdbool.h>
 #include <math.h>
 #ifdef __cplusplus
 extern "C" {
 #endif
 /* Forward-declare the HAL UART handle type.  The real definition comes from
 * stm32f7xx_hal.h (production) or stm32_hal_mock.h (tests). */
 #ifndef STM32_HAL_MOCK_H
 #include "stm32f7xx_hal.h"
 #else
 /* Already included via mock -- nothing to do */
 #endif
 /* ========================= Constants ================================= */
 #define UM982_RX_BUF_SIZE    512   /* Ring buffer for incoming UART bytes */
 #define UM982_LINE_BUF_SIZE   96   /* Max NMEA sentence (82 chars + margin) */
 #define UM982_CMD_BUF_SIZE   128   /* Outgoing command buffer */
 #define UM982_INIT_TIMEOUT_MS 3000 /* Timeout waiting for VERSIONA response */
 /* Fix quality values (from GGA field 6) */
 #define UM982_FIX_NONE       0
 #define UM982_FIX_GPS        1
 #define UM982_FIX_DGPS       2
 #define UM982_FIX_RTK_FIXED  4
 #define UM982_FIX_RTK_FLOAT  5
 /* Validity timeout defaults (ms) */
 #define UM982_HEADING_TIMEOUT_MS 2000
 #define UM982_POSITION_TIMEOUT_MS 5000
 /* ========================= Data Types ================================ */
 typedef struct {
    /* Position */
    double   latitude;       /* Decimal degrees, positive = North */
    double   longitude;      /* Decimal degrees, positive = East */
    float    altitude;       /* Meters above MSL */
    float    geoid_sep;      /* Geoid separation (meters) */
    /* Heading (from dual-antenna THS) */
    float    heading;        /* True heading 0-360 degrees, NAN if invalid */
    char     heading_mode;   /* A=autonomous, D=diff, E=est, M=manual, S=sim, V=invalid */
    /* Velocity */
    float    speed_knots;    /* Speed over ground (knots) */
    float    speed_kmh;      /* Speed over ground (km/h) */
    float    course_true;    /* Course over ground (degrees true) */
    /* Quality */
    uint8_t  fix_quality;    /* 0=none, 1=GPS, 2=DGPS, 4=RTK fixed, 5=RTK float */
    uint8_t  num_satellites; /* Satellites used in fix */
    float    hdop;           /* Horizontal dilution of precision */
    /* RMC status */
    char     rmc_status;     /* A=valid, V=warning */
    /* Timestamps (HAL_GetTick() at last update) */
    uint32_t last_fix_tick;   /* Last valid GGA fix (fix_quality > 0) */
    uint32_t last_gga_tick;
    uint32_t last_rmc_tick;
    uint32_t last_ths_tick;
    uint32_t last_vtg_tick;
    /* Communication state */
    bool     initialized;      /* VERSIONA or supported NMEA traffic seen */
    bool     version_received; /* VERSIONA response seen */
    /* ---- Internal parser state (not for external use) ---- */
    /* Ring buffer */
    uint8_t  rx_buf[UM982_RX_BUF_SIZE];
    uint16_t rx_head;        /* Write index */
    uint16_t rx_tail;        /* Read index */
    /* Line assembler */
    char     line_buf[UM982_LINE_BUF_SIZE];
    uint8_t  line_len;
    bool     line_overflow;  /* Current line exceeded buffer */
    /* UART handle */
    UART_HandleTypeDef *huart;
 } UM982_GPS_t;
 /* ========================= Public API ================================ */
 /**
 * Initialize the UM982_GPS_t structure and configure the module.
 *
 * Sends: UNLOG, CONFIG HEADING, optional CONFIG HEADING LENGTH,
 *        GPGGA, GPRMC, GPTHS
 * Queries VERSIONA to verify communication.
 *
 * @param gps          Pointer to UM982_GPS_t instance
 * @param huart        UART handle (e.g. &huart5)
 * @param baseline_cm  Distance between antennas in cm (0 = use module default)
 * @param tolerance_cm Baseline tolerance in cm (0 = use module default)
 * @return true if VERSIONA response received within timeout
 */
 bool um982_init(UM982_GPS_t *gps, UART_HandleTypeDef *huart,
                float baseline_cm, float tolerance_cm);
 /**
 * Process available UART data. Call from main loop — non-blocking.
 *
 * Reads all available bytes from UART, assembles lines, and dispatches
 * complete NMEA sentences to the appropriate parser.
 *
 * @param gps  Pointer to UM982_GPS_t instance
 */
 void um982_process(UM982_GPS_t *gps);
 /**
 * Feed raw bytes directly into the parser (useful for testing).
 * In production, um982_process() calls this internally after UART read.
 *
 * @param gps   Pointer to UM982_GPS_t instance
 * @param data  Pointer to byte array
 * @param len   Number of bytes
 */
 void um982_feed(UM982_GPS_t *gps, const uint8_t *data, uint16_t len);
 /* ---- Getters ---- */
 static inline float    um982_get_heading(const UM982_GPS_t *gps)     { return gps->heading; }
 static inline double   um982_get_latitude(const UM982_GPS_t *gps)    { return gps->latitude; }
 static inline double   um982_get_longitude(const UM982_GPS_t *gps)   { return gps->longitude; }
 static inline float    um982_get_altitude(const UM982_GPS_t *gps)    { return gps->altitude; }
 static inline uint8_t  um982_get_fix_quality(const UM982_GPS_t *gps) { return gps->fix_quality; }
 static inline uint8_t  um982_get_num_sats(const UM982_GPS_t *gps)    { return gps->num_satellites; }
 static inline float    um982_get_hdop(const UM982_GPS_t *gps)        { return gps->hdop; }
 static inline float    um982_get_speed_knots(const UM982_GPS_t *gps) { return gps->speed_knots; }
 static inline float    um982_get_speed_kmh(const UM982_GPS_t *gps)   { return gps->speed_kmh; }
 static inline float    um982_get_course(const UM982_GPS_t *gps)      { return gps->course_true; }
 /**
 * Check if heading is valid (mode A or D, and within timeout).
 */
 bool um982_is_heading_valid(const UM982_GPS_t *gps);
 /**
 * Check if position is valid (fix_quality > 0, and within timeout).
 */
 bool um982_is_position_valid(const UM982_GPS_t *gps);
 /**
 * Get age of last heading update in milliseconds.
 */
 uint32_t um982_heading_age(const UM982_GPS_t *gps);
 /**
 * Get age of the last valid position fix in milliseconds.
 */
 uint32_t um982_position_age(const UM982_GPS_t *gps);
 /* ========================= Internal (exposed for testing) ============ */
 /**
 * Verify NMEA checksum. Returns true if valid.
 * Sentence must start with '$' and contain '*XX' before termination.
 */
 bool um982_verify_checksum(const char *sentence);
 /**
 * Parse a complete NMEA line (with $ prefix and *XX checksum).
 * Dispatches to GGA/RMC/THS/VTG parsers as appropriate.
 */
 void um982_parse_sentence(UM982_GPS_t *gps, const char *sentence);
 /**
 * Parse NMEA coordinate string to decimal degrees.
 * Works for both latitude (ddmm.mmmm) and longitude (dddmm.mmmm)
 * by detecting the decimal point position.
 *
 * @param field     NMEA coordinate field (e.g. "4404.14036" or "12118.85961")
 * @param hemisphere 'N', 'S', 'E', or 'W'
 * @return Decimal degrees (negative for S/W), or NAN on parse error
 */
 double um982_parse_coord(const char *field, char hemisphere);
 /**
 * Send a command to the UM982. Appends \r\n automatically.
 * @return true if UART transmit succeeded
 */
 bool um982_send_command(UM982_GPS_t *gps, const char *cmd);
 #ifdef __cplusplus
 }
 #endif
 #endif /* UM982_GPS_H */
@@ -3,25 +3,38 @@
 *.dSYM/
 # Test binaries (built by Makefile)
 # TESTS_WITH_REAL
 test_bug1_timed_sync_init_ordering
 test_bug2_ad9523_double_setup
 test_bug3_timed_sync_noop
 test_bug4_phase_shift_before_check
 test_bug5_fine_phase_gpio_only
 test_bug9_platform_ops_null
 test_bug10_spi_cs_not_toggled
 test_bug15_htim3_dangling_extern
 # TESTS_MOCK_ONLY
 test_bug2_ad9523_double_setup
 test_bug6_timer_variable_collision
 test_bug7_gpio_pin_conflict
 test_bug8_uart_commented_out
-test_bug9_platform_ops_null
+test_bug14_diag_section_args
-test_bug10_spi_cs_not_toggled
+test_gap3_emergency_stop_rails
-test_bug11_platform_spi_transmit_only
+
 # TESTS_STANDALONE
 test_bug12_pa_cal_loop_inverted
 test_bug13_dac2_adc_buffer_mismatch
 test_bug14_diag_section_args
 test_bug15_htim3_dangling_extern
 test_agc_outer_loop
 test_gap3_emergency_state_ordering
 test_gap3_emergency_stop_rails
 test_gap3_idq_periodic_reread
 test_gap3_iwdg_config
 test_gap3_temperature_max
 test_gap3_idq_periodic_reread
 test_gap3_emergency_state_ordering
 test_gap3_overtemp_emergency_stop
 test_gap3_health_watchdog_cold_start
 # TESTS_WITH_PLATFORM
 test_bug11_platform_spi_transmit_only
 # TESTS_WITH_CXX
 test_agc_outer_loop
 # Manual / one-off test builds
 test_um982_gps
@@ -27,6 +27,10 @@ CXX_LIB_DIR := ../9_1_1_C_Cpp_Libraries
 CXX_SRCS    := $(CXX_LIB_DIR)/ADAR1000_AGC.cpp $(CXX_LIB_DIR)/ADAR1000_Manager.cpp
 CXX_OBJS    := ADAR1000_AGC.o ADAR1000_Manager.o
 # GPS driver source
 GPS_SRC := ../9_1_3_C_Cpp_Code/um982_gps.c
 GPS_OBJ := um982_gps.o
 # Real source files compiled against mock headers
 REAL_SRC := ../9_1_1_C_Cpp_Libraries/adf4382a_manager.c
@@ -65,7 +69,9 @@ TESTS_STANDALONE := test_bug12_pa_cal_loop_inverted \
                    test_gap3_temperature_max \
                    test_gap3_idq_periodic_reread \
                    test_gap3_emergency_state_ordering \
-                    test_gap3_overtemp_emergency_stop
+                    test_gap3_overtemp_emergency_stop \
                    test_gap3_health_watchdog_cold_start \
                    test_gap3_fault_ack_clears_emergency
 # Tests that need platform_noos_stm32.o + mocks
 TESTS_WITH_PLATFORM := test_bug11_platform_spi_transmit_only
@@ -73,12 +79,15 @@ TESTS_WITH_PLATFORM := test_bug11_platform_spi_transmit_only
 # C++ tests (AGC outer loop)
 TESTS_WITH_CXX := test_agc_outer_loop
-ALL_TESTS := $(TESTS_WITH_REAL) $(TESTS_MOCK_ONLY) $(TESTS_STANDALONE) $(TESTS_WITH_PLATFORM) $(TESTS_WITH_CXX)
+# GPS driver tests (need mocks + GPS source + -lm)
 TESTS_GPS := test_um982_gps
 ALL_TESTS := $(TESTS_WITH_REAL) $(TESTS_MOCK_ONLY) $(TESTS_STANDALONE) $(TESTS_WITH_PLATFORM) $(TESTS_WITH_CXX) $(TESTS_GPS)
 .PHONY: all build test clean \
        $(addprefix test_,bug1 bug2 bug3 bug4 bug5 bug6 bug7 bug8 bug9 bug10 bug11 bug12 bug13 bug14 bug15) \
        test_gap3_estop test_gap3_iwdg test_gap3_temp test_gap3_idq test_gap3_order \
-        test_gap3_overtemp
+        test_gap3_overtemp test_gap3_wdog
 all: build test
@@ -167,6 +176,12 @@ test_gap3_emergency_state_ordering: test_gap3_emergency_state_ordering.c
 test_gap3_overtemp_emergency_stop: test_gap3_overtemp_emergency_stop.c
 	$(CC) $(CFLAGS) $< -o $@
 test_gap3_health_watchdog_cold_start: test_gap3_health_watchdog_cold_start.c
 	$(CC) $(CFLAGS) $< -o $@
 test_gap3_fault_ack_clears_emergency: test_gap3_fault_ack_clears_emergency.c
 	$(CC) $(CFLAGS) $< -o $@
 # Tests that need platform_noos_stm32.o + mocks
 $(TESTS_WITH_PLATFORM): %: %.c $(MOCK_OBJS) $(PLATFORM_OBJ)
 	$(CC) $(CFLAGS) $(INCLUDES) $< $(MOCK_OBJS) $(PLATFORM_OBJ) -o $@
@@ -189,6 +204,20 @@ test_agc_outer_loop: test_agc_outer_loop.cpp $(CXX_OBJS) $(MOCK_OBJS)
 test_agc: test_agc_outer_loop
 	./test_agc_outer_loop
 # --- GPS driver rules ---
 $(GPS_OBJ): $(GPS_SRC)
 	$(CC) $(CFLAGS) $(INCLUDES) -I../9_1_3_C_Cpp_Code -c $< -o $@
 # Note: test includes um982_gps.c directly for white-box testing (static fn access)
 test_um982_gps: test_um982_gps.c $(MOCK_OBJS)
 	$(CC) $(CFLAGS) $(INCLUDES) -I../9_1_3_C_Cpp_Code $< $(MOCK_OBJS) -lm -o $@
 # Convenience target
 .PHONY: test_gps
 test_gps: test_um982_gps
 	./test_um982_gps
 # --- Individual test targets ---
 test_bug1: test_bug1_timed_sync_init_ordering
@@ -254,6 +283,9 @@ test_gap3_order: test_gap3_emergency_state_ordering
 test_gap3_overtemp: test_gap3_overtemp_emergency_stop
 	./test_gap3_overtemp_emergency_stop
 test_gap3_wdog: test_gap3_health_watchdog_cold_start
 	./test_gap3_health_watchdog_cold_start
 # --- Clean ---
 clean:
@@ -21,6 +21,7 @@ SPI_HandleTypeDef  hspi4 = { .id = 4 };
 I2C_HandleTypeDef  hi2c1 = { .id = 1 };
 I2C_HandleTypeDef  hi2c2 = { .id = 2 };
 UART_HandleTypeDef huart3 = { .id = 3 };
 UART_HandleTypeDef huart5 = { .id = 5 };  /* GPS UART */
 ADC_HandleTypeDef  hadc3 = { .id = 3 };
 TIM_HandleTypeDef  htim3 = { .id = 3 };
@@ -34,6 +35,26 @@ uint32_t mock_tick = 0;
 /* ========================= Printf control ========================= */
 int mock_printf_enabled = 0;
 /* ========================= Mock UART TX capture =================== */
 uint8_t  mock_uart_tx_buf[MOCK_UART_TX_BUF_SIZE];
 uint16_t mock_uart_tx_len = 0;
 /* ========================= Mock UART RX buffer ==================== */
 #define MOCK_UART_RX_SLOTS 8
 static struct {
    uint32_t uart_id;
    uint8_t  buf[MOCK_UART_RX_BUF_SIZE];
    uint16_t head;
    uint16_t tail;
 } mock_uart_rx[MOCK_UART_RX_SLOTS];
 void mock_uart_tx_clear(void)
 {
    mock_uart_tx_len = 0;
    memset(mock_uart_tx_buf, 0, sizeof(mock_uart_tx_buf));
 }
 /* ========================= Mock GPIO read ========================= */
 #define GPIO_READ_TABLE_SIZE 32
 static struct {
@@ -49,6 +70,9 @@ void spy_reset(void)
    mock_tick = 0;
    mock_printf_enabled = 0;
    memset(gpio_read_table, 0, sizeof(gpio_read_table));
    memset(mock_uart_rx, 0, sizeof(mock_uart_rx));
    mock_uart_tx_len = 0;
    memset(mock_uart_tx_buf, 0, sizeof(mock_uart_tx_buf));
 }
 const SpyRecord *spy_get(int index)
@@ -185,6 +209,83 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD
        .value = Timeout,
        .extra = huart
    });
    /* Capture TX data for test inspection */
    for (uint16_t i = 0; i < Size && mock_uart_tx_len < MOCK_UART_TX_BUF_SIZE; i++) {
        mock_uart_tx_buf[mock_uart_tx_len++] = pData[i];
    }
    return HAL_OK;
 }
 /* ========================= Mock UART RX helpers ====================== */
 /* find_rx_slot, mock_uart_rx_load, etc. use the mock_uart_rx declared above */
 static int find_rx_slot(UART_HandleTypeDef *huart)
 {
    if (huart == NULL) return -1;
    /* Find existing slot */
    for (int i = 0; i < MOCK_UART_RX_SLOTS; i++) {
        if (mock_uart_rx[i].uart_id == huart->id && mock_uart_rx[i].head != mock_uart_rx[i].tail) {
            return i;
        }
        if (mock_uart_rx[i].uart_id == huart->id) {
            return i;
        }
    }
    /* Find empty slot */
    for (int i = 0; i < MOCK_UART_RX_SLOTS; i++) {
        if (mock_uart_rx[i].uart_id == 0) {
            mock_uart_rx[i].uart_id = huart->id;
            return i;
        }
    }
    return -1;
 }
 void mock_uart_rx_load(UART_HandleTypeDef *huart, const uint8_t *data, uint16_t len)
 {
    int slot = find_rx_slot(huart);
    if (slot < 0) return;
    mock_uart_rx[slot].uart_id = huart->id;
    for (uint16_t i = 0; i < len; i++) {
        uint16_t next = (mock_uart_rx[slot].head + 1) % MOCK_UART_RX_BUF_SIZE;
        if (next == mock_uart_rx[slot].tail) break;  /* Buffer full */
        mock_uart_rx[slot].buf[mock_uart_rx[slot].head] = data[i];
        mock_uart_rx[slot].head = next;
    }
 }
 void mock_uart_rx_clear(UART_HandleTypeDef *huart)
 {
    int slot = find_rx_slot(huart);
    if (slot < 0) return;
    mock_uart_rx[slot].head = 0;
    mock_uart_rx[slot].tail = 0;
 }
 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData,
                                    uint16_t Size, uint32_t Timeout)
 {
    (void)Timeout;
    int slot = find_rx_slot(huart);
    if (slot < 0) return HAL_TIMEOUT;
    for (uint16_t i = 0; i < Size; i++) {
        if (mock_uart_rx[slot].head == mock_uart_rx[slot].tail) {
            return HAL_TIMEOUT;  /* No more data */
        }
        pData[i] = mock_uart_rx[slot].buf[mock_uart_rx[slot].tail];
        mock_uart_rx[slot].tail = (mock_uart_rx[slot].tail + 1) % MOCK_UART_RX_BUF_SIZE;
    }
    spy_push((SpyRecord){
        .type  = SPY_UART_RX,
        .port  = NULL,
        .pin   = Size,
        .value = Timeout,
        .extra = huart
    });
    return HAL_OK;
 }
@@ -105,6 +105,7 @@ typedef struct {
 extern SPI_HandleTypeDef  hspi1, hspi4;
 extern I2C_HandleTypeDef  hi2c1, hi2c2;
 extern UART_HandleTypeDef huart3;
 extern UART_HandleTypeDef huart5;  /* GPS UART */
 extern ADC_HandleTypeDef  hadc3;
 extern TIM_HandleTypeDef  htim3;  /* Timer for DELADJ PWM */
@@ -139,6 +140,7 @@ typedef enum {
    SPY_TIM_SET_COMPARE,
    SPY_SPI_TRANSMIT_RECEIVE,
    SPY_SPI_TRANSMIT,
    SPY_UART_RX,
 } SpyCallType;
 typedef struct {
@@ -187,6 +189,23 @@ void          HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
 uint32_t      HAL_GetTick(void);
 void          HAL_Delay(uint32_t Delay);
 HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
 HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 /* ========================= Mock UART RX buffer ======================= */
 /* Inject bytes into the mock UART RX buffer for a specific UART handle.
 * HAL_UART_Receive will return these bytes one at a time. */
 #define MOCK_UART_RX_BUF_SIZE 2048
 void mock_uart_rx_load(UART_HandleTypeDef *huart, const uint8_t *data, uint16_t len);
 void mock_uart_rx_clear(UART_HandleTypeDef *huart);
 /* Capture buffer for UART TX data (to verify commands sent to GPS module) */
 #define MOCK_UART_TX_BUF_SIZE 2048
 extern uint8_t  mock_uart_tx_buf[MOCK_UART_TX_BUF_SIZE];
 extern uint16_t mock_uart_tx_len;
 void mock_uart_tx_clear(void);
 /* ========================= SPI stubs ============================== */
@@ -50,7 +50,7 @@ static void test_defaults()
    assert(agc.min_gain == 0);
    assert(agc.max_gain == 127);
    assert(agc.holdoff_frames == 4);
-    assert(agc.enabled == true);
+    assert(agc.enabled == false);  // disabled by default — FPGA DIG_6 is source of truth
    assert(agc.holdoff_counter == 0);
    assert(agc.last_saturated == false);
    assert(agc.saturation_event_count == 0);
@@ -67,6 +67,7 @@ static void test_defaults()
 static void test_saturation_reduces_gain()
 {
    ADAR1000_AGC agc;
    agc.enabled = true;  // default is OFF; enable for this test
    uint8_t initial = agc.agc_base_gain;  // 30
    agc.update(true);  // saturation
@@ -82,6 +83,7 @@ static void test_saturation_reduces_gain()
 static void test_holdoff_prevents_early_gain_up()
 {
    ADAR1000_AGC agc;
    agc.enabled = true;  // default is OFF; enable for this test
    agc.update(true);  // saturate once -> gain = 26
    uint8_t after_sat = agc.agc_base_gain;
@@ -101,6 +103,7 @@ static void test_holdoff_prevents_early_gain_up()
 static void test_recovery_after_holdoff()
 {
    ADAR1000_AGC agc;
    agc.enabled = true;  // default is OFF; enable for this test
    agc.update(true);  // saturate -> gain = 26
    uint8_t after_sat = agc.agc_base_gain;
@@ -119,6 +122,7 @@ static void test_recovery_after_holdoff()
 static void test_min_gain_clamp()
 {
    ADAR1000_AGC agc;
    agc.enabled = true;  // default is OFF; enable for this test
    agc.min_gain = 10;
    agc.agc_base_gain = 12;
    agc.gain_step_down = 4;
@@ -136,6 +140,7 @@ static void test_min_gain_clamp()
 static void test_max_gain_clamp()
 {
    ADAR1000_AGC agc;
    agc.enabled = true;  // default is OFF; enable for this test
    agc.max_gain = 32;
    agc.agc_base_gain = 31;
    agc.gain_step_up = 2;
@@ -226,6 +231,7 @@ static void test_apply_gain_spi()
 static void test_reset_preserves_config()
 {
    ADAR1000_AGC agc;
    agc.enabled = true;  // default is OFF; enable for this test
    agc.agc_base_gain = 42;
    agc.gain_step_down = 8;
    agc.cal_offset[3] = -5;
@@ -255,6 +261,7 @@ static void test_reset_preserves_config()
 static void test_saturation_counter()
 {
    ADAR1000_AGC agc;
    agc.enabled = true;  // default is OFF; enable for this test
    for (int i = 0; i < 10; ++i) {
        agc.update(true);
@@ -274,6 +281,7 @@ static void test_saturation_counter()
 static void test_mixed_sequence()
 {
    ADAR1000_AGC agc;
    agc.enabled = true;  // default is OFF; enable for this test
    agc.agc_base_gain = 30;
    agc.gain_step_down = 4;
    agc.gain_step_up = 1;
@@ -0,0 +1,121 @@
 /*******************************************************************************
 * test_gap3_fault_ack_clears_emergency.c
 *
 * Verifies the FAULT_ACK clear path for system_emergency_state:
 *   - USBHandler detects exactly [0x40, 0x00, 0x00, 0x00] in a 4-byte packet
 *   - Detection is false-positive-free: larger packets (settings data) carrying
 *     the same bytes as a subsequence must NOT trigger the ack
 *   - Main-loop blink logic clears system_emergency_state on receipt
 *
 * Logic extracted from USBHandler.cpp + main.cpp to mirror the actual code
 * paths without requiring HAL headers.
 ******************************************************************************/
 #include <assert.h>
 #include <stdio.h>
 #include <stdbool.h>
 #include <string.h>
 #include <stdint.h>
 /* ── Simulated USBHandler state ─────────────────────────────────────────── */
 static bool fault_ack_received = false;
 static volatile bool system_emergency_state = false;
 static const uint8_t FAULT_ACK_SEQ[4] = {0x40, 0x00, 0x00, 0x00};
 /* Mirrors USBHandler::processUSBData() detection logic */
 static void sim_processUSBData(const uint8_t *data, uint32_t length)
 {
    if (data == NULL || length == 0) return;
    if (length == 4 && memcmp(data, FAULT_ACK_SEQ, 4) == 0) {
        fault_ack_received = true;
        return;
    }
    /* (normal state machine omitted — not under test here) */
 }
 /* Mirrors one iteration of the blink loop in main.cpp */
 static void sim_blink_iteration(void)
 {
    /* HAL_GPIO_TogglePin + HAL_Delay omitted */
    if (fault_ack_received) {
        system_emergency_state = false;
        fault_ack_received = false;
    }
 }
 int main(void)
 {
    printf("=== Gap-3 FAULT_ACK clears system_emergency_state ===\n");
    /* Test 1: exact 4-byte FAULT_ACK packet sets the flag */
    printf("  Test 1: exact FAULT_ACK packet detected... ");
    fault_ack_received = false;
    const uint8_t ack_pkt[4] = {0x40, 0x00, 0x00, 0x00};
    sim_processUSBData(ack_pkt, 4);
    assert(fault_ack_received == true);
    printf("PASS\n");
    /* Test 2: flag cleared and system_emergency_state exits blink loop */
    printf("  Test 2: blink loop exits on FAULT_ACK... ");
    system_emergency_state = true;
    fault_ack_received = true;
    sim_blink_iteration();
    assert(system_emergency_state == false);
    assert(fault_ack_received == false);
    printf("PASS\n");
    /* Test 3: blink loop does NOT exit without ack */
    printf("  Test 3: blink loop holds without ack... ");
    system_emergency_state = true;
    fault_ack_received = false;
    sim_blink_iteration();
    assert(system_emergency_state == true);
    printf("PASS\n");
    /* Test 4: settings-sized packet carrying [0x40,0x00,0x00,0x00] as first
     * 4 bytes does NOT trigger ack (IEEE 754 double 2.0 = 0x4000000000000000) */
    printf("  Test 4: settings packet with 2.0 double does not false-trigger... ");
    fault_ack_received = false;
    uint8_t settings_pkt[82];
    memset(settings_pkt, 0, sizeof(settings_pkt));
    /* First 4 bytes look like FAULT_ACK but packet length is 82 */
    settings_pkt[0] = 0x40; settings_pkt[1] = 0x00;
    settings_pkt[2] = 0x00; settings_pkt[3] = 0x00;
    sim_processUSBData(settings_pkt, sizeof(settings_pkt));
    assert(fault_ack_received == false);
    printf("PASS\n");
    /* Test 5: 3-byte packet (truncated) does not trigger */
    printf("  Test 5: truncated 3-byte packet ignored... ");
    fault_ack_received = false;
    const uint8_t short_pkt[3] = {0x40, 0x00, 0x00};
    sim_processUSBData(short_pkt, 3);
    assert(fault_ack_received == false);
    printf("PASS\n");
    /* Test 6: wrong opcode byte in 4-byte packet does not trigger */
    printf("  Test 6: wrong opcode (0x28 AGC_ENABLE) not detected as FAULT_ACK... ");
    fault_ack_received = false;
    const uint8_t agc_pkt[4] = {0x28, 0x00, 0x00, 0x01};
    sim_processUSBData(agc_pkt, 4);
    assert(fault_ack_received == false);
    printf("PASS\n");
    /* Test 7: multiple blink iterations — loop stays active until ack */
    printf("  Test 7: loop stays active across multiple iterations until ack... ");
    system_emergency_state = true;
    fault_ack_received = false;
    sim_blink_iteration();
    assert(system_emergency_state == true);
    sim_blink_iteration();
    assert(system_emergency_state == true);
    /* Now ack arrives */
    sim_processUSBData(ack_pkt, 4);
    assert(fault_ack_received == true);
    sim_blink_iteration();
    assert(system_emergency_state == false);
    printf("PASS\n");
    printf("\n=== Gap-3 FAULT_ACK: ALL 7 TESTS PASSED ===\n\n");
    return 0;
 }
@@ -0,0 +1,132 @@
 /*******************************************************************************
 * test_gap3_health_watchdog_cold_start.c
 *
 * Safety bug: checkSystemHealth()'s internal watchdog (step 9, pre-fix) had two
 * linked defects that, once ERROR_WATCHDOG_TIMEOUT was escalated to
 * Emergency_Stop() by the overtemp/watchdog PR, would false-latch the radar:
 *
 *   (1) Cold-start false trip:
 *         static uint32_t last_health_check = 0;
 *         if (HAL_GetTick() - last_health_check > 60000) { ... }
 *       On the very first call, last_health_check == 0, so once the MCU has
 *       been up >60 s (which is typical after the ADAR1000 / AD9523 / ADF4382
 *       init sequence) the subtraction `now - 0` exceeds 60 000 ms and the
 *       watchdog trips spuriously.
 *
 *   (2) Stale-timestamp after early returns:
 *         last_health_check = HAL_GetTick();   // at END of function
 *       Every earlier sub-check (IMU, BMP180, GPS, PA Idq, temperature) has an
 *       `if (fault) return current_error;` path that skips the update. After a
 *       cumulative 60 s of transient faults, the next clean call compares
 *       `now` against the long-stale `last_health_check` and trips.
 *
 * After fix:  Watchdog logic moved to function ENTRY. A dedicated cold-start
 *             branch seeds the timestamp on the first call without checking.
 *             On every subsequent call, the elapsed delta is captured FIRST
 *             and last_health_check is updated BEFORE any sub-check runs, so
 *             early returns no longer leave a stale value.
 *
 * Test strategy:
 *   Extract the post-fix watchdog predicate into a standalone function that
 *   takes a simulated HAL_GetTick() value and returns whether the watchdog
 *   should trip. Walk through boot + fault sequences that would have tripped
 *   the pre-fix code and assert the post-fix code does NOT trip.
 ******************************************************************************/
 #include <assert.h>
 #include <stdint.h>
 #include <stdio.h>
 /* --- Post-fix watchdog state + predicate, extracted verbatim --- */
 static uint32_t last_health_check = 0;
 /* Returns 1 iff this call should raise ERROR_WATCHDOG_TIMEOUT.
   Updates last_health_check BEFORE returning (matches post-fix behaviour). */
 static int health_watchdog_step(uint32_t now_tick)
 {
    if (last_health_check == 0) {
        last_health_check = now_tick;   /* cold start: seed only, never trip */
        return 0;
    }
    uint32_t elapsed = now_tick - last_health_check;
    last_health_check = now_tick;       /* update BEFORE any early return */
    return (elapsed > 60000) ? 1 : 0;
 }
 /* Test helper: reset the static state between scenarios. */
 static void reset_state(void) { last_health_check = 0; }
 int main(void)
 {
    printf("=== Safety fix: checkSystemHealth() watchdog cold-start + stale-ts ===\n");
    /* ---------- Scenario 1: cold-start after 60 s of init must NOT trip ---- */
    printf("  Test 1: first call at t=75000 ms (post-init) does not trip... ");
    reset_state();
    assert(health_watchdog_step(75000) == 0);
    printf("PASS\n");
    /* ---------- Scenario 2: first call far beyond 60 s (PRE-FIX BUG) ------- */
    printf("  Test 2: first call at t=600000 ms still does not trip... ");
    reset_state();
    assert(health_watchdog_step(600000) == 0);
    printf("PASS\n");
    /* ---------- Scenario 3: healthy main-loop pacing (10 ms period) -------- */
    printf("  Test 3: 1000 calls at 10 ms intervals never trip... ");
    reset_state();
    (void)health_watchdog_step(1000);  /* seed */
    for (int i = 1; i <= 1000; i++) {
        assert(health_watchdog_step(1000 + i * 10) == 0);
    }
    printf("PASS\n");
    /* ---------- Scenario 4: stale-timestamp after a burst of early returns -
       Pre-fix bug: many early returns skipped the timestamp update, so a
       later clean call would compare `now` against a 60+ s old value. Post-fix,
       every call (including ones that would have early-returned in the real
       function) updates the timestamp at the top, so this scenario is modelled
       by calling health_watchdog_step() on every iteration of the main loop. */
    printf("  Test 4: 70 s of 100 ms-spaced calls after seed do not trip... ");
    reset_state();
    (void)health_watchdog_step(50000);   /* seed mid-run */
    for (int i = 1; i <= 700; i++) {     /* 70 s @ 100 ms */
        int tripped = health_watchdog_step(50000 + i * 100);
        assert(tripped == 0);
    }
    printf("PASS\n");
    /* ---------- Scenario 5: genuine stall MUST trip ------------------------ */
    printf("  Test 5: real 60+ s gap between calls does trip... ");
    reset_state();
    (void)health_watchdog_step(10000);              /* seed */
    assert(health_watchdog_step(10000 + 60001) == 1);
    printf("PASS\n");
    /* ---------- Scenario 6: exactly 60 s gap is the boundary -- do NOT trip
       Post-fix predicate uses strict >60000, matching the pre-fix comparator. */
    printf("  Test 6: exactly 60000 ms gap does not trip (boundary)... ");
    reset_state();
    (void)health_watchdog_step(10000);
    assert(health_watchdog_step(10000 + 60000) == 0);
    printf("PASS\n");
    /* ---------- Scenario 7: trip, then recover on next paced call ---------- */
    printf("  Test 7: after a genuine stall+trip, next paced call does not re-trip... ");
    reset_state();
    (void)health_watchdog_step(5000);                      /* seed */
    assert(health_watchdog_step(5000 + 70000) == 1);       /* stall -> trip */
    assert(health_watchdog_step(5000 + 70000 + 10) == 0);  /* resume paced */
    printf("PASS\n");
    /* ---------- Scenario 8: HAL_GetTick() 32-bit wrap (~49.7 days) ---------
       Because we subtract unsigned 32-bit values, wrap is handled correctly as
       long as the true elapsed time is < 2^32 ms. */
    printf("  Test 8: tick wrap from 0xFFFFFF00 -> 0x00000064 (200 ms span) does not trip... ");
    reset_state();
    (void)health_watchdog_step(0xFFFFFF00u);
    assert(health_watchdog_step(0x00000064u) == 0);  /* elapsed = 0x164 = 356 ms */
    printf("PASS\n");
    printf("\n=== Safety fix: ALL TESTS PASSED ===\n\n");
    return 0;
 }
@@ -0,0 +1,853 @@
 /*******************************************************************************
 * test_um982_gps.c -- Unit tests for UM982 GPS driver
 *
 * Tests NMEA parsing, checksum validation, coordinate parsing, init sequence,
 * and validity tracking. Uses the mock HAL infrastructure for UART.
 *
 * Build: see Makefile target test_um982_gps
 * Run:   ./test_um982_gps
 ******************************************************************************/
 #include "stm32_hal_mock.h"
 #include "../9_1_3_C_Cpp_Code/um982_gps.h"
 #include "../9_1_3_C_Cpp_Code/um982_gps.c"  /* Include .c directly for white-box testing */
 #include <stdio.h>
 #include <string.h>
 #include <assert.h>
 #include <math.h>
 /* ========================= Test helpers ============================== */
 static int tests_passed = 0;
 static int tests_failed = 0;
 #define TEST(name) \
    do { printf("  [TEST] %-55s ", name); } while(0)
 #define PASS() \
    do { printf("PASS\n"); tests_passed++; } while(0)
 #define FAIL(msg) \
    do { printf("FAIL: %s\n", msg); tests_failed++; } while(0)
 #define ASSERT_TRUE(expr, msg) \
    do { if (!(expr)) { FAIL(msg); return; } } while(0)
 #define ASSERT_FALSE(expr, msg) \
    do { if (expr) { FAIL(msg); return; } } while(0)
 #define ASSERT_EQ_INT(a, b, msg) \
    do { if ((a) != (b)) { \
        char _buf[256]; \
        snprintf(_buf, sizeof(_buf), "%s (got %d, expected %d)", msg, (int)(a), (int)(b)); \
        FAIL(_buf); return; \
    } } while(0)
 #define ASSERT_NEAR(a, b, tol, msg) \
    do { if (fabs((double)(a) - (double)(b)) > (tol)) { \
        char _buf[256]; \
        snprintf(_buf, sizeof(_buf), "%s (got %.8f, expected %.8f)", msg, (double)(a), (double)(b)); \
        FAIL(_buf); return; \
    } } while(0)
 #define ASSERT_NAN(val, msg) \
    do { if (!isnan(val)) { FAIL(msg); return; } } while(0)
 static UM982_GPS_t gps;
 static void reset_gps(void)
 {
    spy_reset();
    memset(&gps, 0, sizeof(gps));
    gps.huart = &huart5;
    gps.heading = NAN;
    gps.heading_mode = 'V';
    gps.rmc_status = 'V';
 }
 /* ========================= Checksum tests ============================ */
 static void test_checksum_valid(void)
 {
    TEST("checksum: valid GGA");
    ASSERT_TRUE(um982_verify_checksum(
        "$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47"),
        "should be valid");
    PASS();
 }
 static void test_checksum_valid_ths(void)
 {
    TEST("checksum: valid THS");
    ASSERT_TRUE(um982_verify_checksum("$GNTHS,341.3344,A*1F"),
        "should be valid");
    PASS();
 }
 static void test_checksum_invalid(void)
 {
    TEST("checksum: invalid (wrong value)");
    ASSERT_FALSE(um982_verify_checksum("$GNTHS,341.3344,A*FF"),
        "should be invalid");
    PASS();
 }
 static void test_checksum_missing_star(void)
 {
    TEST("checksum: missing * marker");
    ASSERT_FALSE(um982_verify_checksum("$GNTHS,341.3344,A"),
        "should be invalid");
    PASS();
 }
 static void test_checksum_null(void)
 {
    TEST("checksum: NULL input");
    ASSERT_FALSE(um982_verify_checksum(NULL), "should be false");
    PASS();
 }
 static void test_checksum_no_dollar(void)
 {
    TEST("checksum: missing $ prefix");
    ASSERT_FALSE(um982_verify_checksum("GNTHS,341.3344,A*1F"),
        "should be invalid without $");
    PASS();
 }
 /* ========================= Coordinate parsing tests ================== */
 static void test_coord_latitude_north(void)
 {
    TEST("coord: latitude 4404.14036 N");
    double lat = um982_parse_coord("4404.14036", 'N');
    /* 44 + 04.14036/60 = 44.069006 */
    ASSERT_NEAR(lat, 44.069006, 0.000001, "latitude");
    PASS();
 }
 static void test_coord_latitude_south(void)
 {
    TEST("coord: latitude 3358.92500 S (negative)");
    double lat = um982_parse_coord("3358.92500", 'S');
    ASSERT_TRUE(lat < 0.0, "should be negative for S");
    ASSERT_NEAR(lat, -(33.0 + 58.925/60.0), 0.000001, "latitude");
    PASS();
 }
 static void test_coord_longitude_3digit(void)
 {
    TEST("coord: longitude 12118.85961 W (3-digit degrees)");
    double lon = um982_parse_coord("12118.85961", 'W');
    /* 121 + 18.85961/60 = 121.314327 */
    ASSERT_TRUE(lon < 0.0, "should be negative for W");
    ASSERT_NEAR(lon, -(121.0 + 18.85961/60.0), 0.000001, "longitude");
    PASS();
 }
 static void test_coord_longitude_east(void)
 {
    TEST("coord: longitude 11614.19729 E");
    double lon = um982_parse_coord("11614.19729", 'E');
    ASSERT_TRUE(lon > 0.0, "should be positive for E");
    ASSERT_NEAR(lon, 116.0 + 14.19729/60.0, 0.000001, "longitude");
    PASS();
 }
 static void test_coord_empty(void)
 {
    TEST("coord: empty string returns NAN");
    ASSERT_NAN(um982_parse_coord("", 'N'), "should be NAN");
    PASS();
 }
 static void test_coord_null(void)
 {
    TEST("coord: NULL returns NAN");
    ASSERT_NAN(um982_parse_coord(NULL, 'N'), "should be NAN");
    PASS();
 }
 static void test_coord_no_dot(void)
 {
    TEST("coord: no decimal point returns NAN");
    ASSERT_NAN(um982_parse_coord("440414036", 'N'), "should be NAN");
    PASS();
 }
 /* ========================= GGA parsing tests ========================= */
 static void test_parse_gga_full(void)
 {
    TEST("GGA: full sentence with all fields");
    reset_gps();
    mock_set_tick(1000);
    um982_parse_sentence(&gps,
        "$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
    ASSERT_NEAR(gps.latitude, 44.069006, 0.0001, "latitude");
    ASSERT_NEAR(gps.longitude, -(121.0 + 18.85961/60.0), 0.0001, "longitude");
    ASSERT_EQ_INT(gps.fix_quality, 1, "fix quality");
    ASSERT_EQ_INT(gps.num_satellites, 12, "num sats");
    ASSERT_NEAR(gps.hdop, 0.98, 0.01, "hdop");
    ASSERT_NEAR(gps.altitude, 1113.0, 0.1, "altitude");
    ASSERT_NEAR(gps.geoid_sep, -21.3, 0.1, "geoid sep");
    PASS();
 }
 static void test_parse_gga_rtk_fixed(void)
 {
    TEST("GGA: RTK fixed (quality=4)");
    reset_gps();
    um982_parse_sentence(&gps,
        "$GNGGA,023634.00,4004.73871635,N,11614.19729418,E,4,28,0.7,61.0988,M,-8.4923,M,,*5D");
    ASSERT_EQ_INT(gps.fix_quality, 4, "RTK fixed");
    ASSERT_EQ_INT(gps.num_satellites, 28, "num sats");
    ASSERT_NEAR(gps.latitude, 40.0 + 4.73871635/60.0, 0.0000001, "latitude");
    ASSERT_NEAR(gps.longitude, 116.0 + 14.19729418/60.0, 0.0000001, "longitude");
    PASS();
 }
 static void test_parse_gga_no_fix(void)
 {
    TEST("GGA: no fix (quality=0)");
    reset_gps();
    /* Compute checksum for this sentence */
    um982_parse_sentence(&gps,
        "$GNGGA,235959.00,,,,,0,00,99.99,,,,,,*79");
    ASSERT_EQ_INT(gps.fix_quality, 0, "no fix");
    PASS();
 }
 /* ========================= RMC parsing tests ========================= */
 static void test_parse_rmc_valid(void)
 {
    TEST("RMC: valid position and speed");
    reset_gps();
    mock_set_tick(2000);
    um982_parse_sentence(&gps,
        "$GNRMC,001031.00,A,4404.13993,N,12118.86023,W,0.146,,100117,,,A*7B");
    ASSERT_EQ_INT(gps.rmc_status, 'A', "status");
    ASSERT_NEAR(gps.latitude, 44.0 + 4.13993/60.0, 0.0001, "latitude");
    ASSERT_NEAR(gps.longitude, -(121.0 + 18.86023/60.0), 0.0001, "longitude");
    ASSERT_NEAR(gps.speed_knots, 0.146, 0.001, "speed");
    PASS();
 }
 static void test_parse_rmc_void(void)
 {
    TEST("RMC: void status (no valid fix)");
    reset_gps();
    gps.latitude = 12.34;  /* Pre-set to check it doesn't get overwritten */
    um982_parse_sentence(&gps,
        "$GNRMC,235959.00,V,,,,,,,100117,,,N*64");
    ASSERT_EQ_INT(gps.rmc_status, 'V', "void status");
    ASSERT_NEAR(gps.latitude, 12.34, 0.001, "lat should not change on void");
    PASS();
 }
 /* ========================= THS parsing tests ========================= */
 static void test_parse_ths_autonomous(void)
 {
    TEST("THS: autonomous heading 341.3344");
    reset_gps();
    mock_set_tick(3000);
    um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
    ASSERT_NEAR(gps.heading, 341.3344, 0.001, "heading");
    ASSERT_EQ_INT(gps.heading_mode, 'A', "mode");
    PASS();
 }
 static void test_parse_ths_not_valid(void)
 {
    TEST("THS: not valid mode");
    reset_gps();
    um982_parse_sentence(&gps, "$GNTHS,,V*10");
    ASSERT_NAN(gps.heading, "heading should be NAN when empty");
    ASSERT_EQ_INT(gps.heading_mode, 'V', "mode V");
    PASS();
 }
 static void test_parse_ths_zero(void)
 {
    TEST("THS: heading exactly 0.0000");
    reset_gps();
    um982_parse_sentence(&gps, "$GNTHS,0.0000,A*19");
    ASSERT_NEAR(gps.heading, 0.0, 0.001, "heading zero");
    ASSERT_EQ_INT(gps.heading_mode, 'A', "mode A");
    PASS();
 }
 static void test_parse_ths_360_boundary(void)
 {
    TEST("THS: heading near 360");
    reset_gps();
    um982_parse_sentence(&gps, "$GNTHS,359.9999,D*13");
    ASSERT_NEAR(gps.heading, 359.9999, 0.001, "heading near 360");
    ASSERT_EQ_INT(gps.heading_mode, 'D', "mode D");
    PASS();
 }
 /* ========================= VTG parsing tests ========================= */
 static void test_parse_vtg(void)
 {
    TEST("VTG: course and speed");
    reset_gps();
    um982_parse_sentence(&gps,
        "$GPVTG,220.86,T,,M,2.550,N,4.724,K,A*34");
    ASSERT_NEAR(gps.course_true, 220.86, 0.01, "course");
    ASSERT_NEAR(gps.speed_knots, 2.550, 0.001, "speed knots");
    ASSERT_NEAR(gps.speed_kmh, 4.724, 0.001, "speed kmh");
    PASS();
 }
 /* ========================= Talker ID tests =========================== */
 static void test_talker_gp(void)
 {
    TEST("talker: GP prefix parses correctly");
    reset_gps();
    um982_parse_sentence(&gps, "$GPTHS,123.4567,A*07");
    ASSERT_NEAR(gps.heading, 123.4567, 0.001, "heading with GP");
    PASS();
 }
 static void test_talker_gl(void)
 {
    TEST("talker: GL prefix parses correctly");
    reset_gps();
    um982_parse_sentence(&gps, "$GLTHS,123.4567,A*1B");
    ASSERT_NEAR(gps.heading, 123.4567, 0.001, "heading with GL");
    PASS();
 }
 /* ========================= Feed / line assembly tests ================ */
 static void test_feed_single_sentence(void)
 {
    TEST("feed: single complete sentence with CRLF");
    reset_gps();
    mock_set_tick(5000);
    const char *data = "$GNTHS,341.3344,A*1F\r\n";
    um982_feed(&gps, (const uint8_t *)data, (uint16_t)strlen(data));
    ASSERT_NEAR(gps.heading, 341.3344, 0.001, "heading");
    PASS();
 }
 static void test_feed_multiple_sentences(void)
 {
    TEST("feed: multiple sentences in one chunk");
    reset_gps();
    mock_set_tick(5000);
    const char *data =
        "$GNTHS,100.0000,A*18\r\n"
        "$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47\r\n";
    um982_feed(&gps, (const uint8_t *)data, (uint16_t)strlen(data));
    ASSERT_NEAR(gps.heading, 100.0, 0.01, "heading from THS");
    ASSERT_EQ_INT(gps.fix_quality, 1, "fix from GGA");
    PASS();
 }
 static void test_feed_partial_then_complete(void)
 {
    TEST("feed: partial bytes then complete");
    reset_gps();
    mock_set_tick(5000);
    const char *part1 = "$GNTHS,200.";
    const char *part2 = "5000,A*1E\r\n";
    um982_feed(&gps, (const uint8_t *)part1, (uint16_t)strlen(part1));
    /* Heading should not be set yet */
    ASSERT_NAN(gps.heading, "should be NAN before complete");
    um982_feed(&gps, (const uint8_t *)part2, (uint16_t)strlen(part2));
    ASSERT_NEAR(gps.heading, 200.5, 0.01, "heading after complete");
    PASS();
 }
 static void test_feed_bad_checksum_rejected(void)
 {
    TEST("feed: bad checksum sentence is rejected");
    reset_gps();
    mock_set_tick(5000);
    const char *data = "$GNTHS,999.0000,A*FF\r\n";
    um982_feed(&gps, (const uint8_t *)data, (uint16_t)strlen(data));
    ASSERT_NAN(gps.heading, "heading should remain NAN");
    PASS();
 }
 static void test_feed_versiona_response(void)
 {
    TEST("feed: VERSIONA response sets flag");
    reset_gps();
    const char *data = "#VERSIONA,79,GPS,FINE,2326,378237000,15434,0,18,889;\"UM982\"\r\n";
    um982_feed(&gps, (const uint8_t *)data, (uint16_t)strlen(data));
    ASSERT_TRUE(gps.version_received, "version_received should be true");
    ASSERT_TRUE(gps.initialized, "VERSIONA should mark communication alive");
    PASS();
 }
 /* ========================= Validity / age tests ====================== */
 static void test_heading_valid_within_timeout(void)
 {
    TEST("validity: heading valid within timeout");
    reset_gps();
    mock_set_tick(10000);
    um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
    /* Still at tick 10000 */
    ASSERT_TRUE(um982_is_heading_valid(&gps), "should be valid");
    PASS();
 }
 static void test_heading_invalid_after_timeout(void)
 {
    TEST("validity: heading invalid after 2s timeout");
    reset_gps();
    mock_set_tick(10000);
    um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
    /* Advance past timeout */
    mock_set_tick(12500);
    ASSERT_FALSE(um982_is_heading_valid(&gps), "should be invalid after 2.5s");
    PASS();
 }
 static void test_heading_invalid_mode_v(void)
 {
    TEST("validity: heading invalid with mode V");
    reset_gps();
    mock_set_tick(10000);
    um982_parse_sentence(&gps, "$GNTHS,,V*10");
    ASSERT_FALSE(um982_is_heading_valid(&gps), "mode V is invalid");
    PASS();
 }
 static void test_position_valid(void)
 {
    TEST("validity: position valid with fix quality 1");
    reset_gps();
    mock_set_tick(10000);
    um982_parse_sentence(&gps,
        "$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
    ASSERT_TRUE(um982_is_position_valid(&gps), "should be valid");
    PASS();
 }
 static void test_position_invalid_no_fix(void)
 {
    TEST("validity: position invalid with no fix");
    reset_gps();
    mock_set_tick(10000);
    um982_parse_sentence(&gps,
        "$GNGGA,235959.00,,,,,0,00,99.99,,,,,,*79");
    ASSERT_FALSE(um982_is_position_valid(&gps), "no fix = invalid");
    PASS();
 }
 static void test_position_age_uses_last_valid_fix(void)
 {
    TEST("age: position age uses last valid fix, not no-fix GGA");
    reset_gps();
    mock_set_tick(10000);
    um982_parse_sentence(&gps,
        "$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
    mock_set_tick(12000);
    um982_parse_sentence(&gps,
        "$GNGGA,235959.00,,,,,0,00,99.99,,,,,,*79");
    mock_set_tick(12500);
    ASSERT_EQ_INT(um982_position_age(&gps), 2500, "age should still be from last valid fix");
    ASSERT_FALSE(um982_is_position_valid(&gps), "latest no-fix GGA should invalidate position");
    PASS();
 }
 static void test_heading_age(void)
 {
    TEST("age: heading age computed correctly");
    reset_gps();
    mock_set_tick(10000);
    um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
    mock_set_tick(10500);
    uint32_t age = um982_heading_age(&gps);
    ASSERT_EQ_INT(age, 500, "age should be 500ms");
    PASS();
 }
 /* ========================= Send command tests ======================== */
 static void test_send_command_appends_crlf(void)
 {
    TEST("send_command: appends \\r\\n");
    reset_gps();
    um982_send_command(&gps, "GPGGA COM2 1");
    /* Check that TX buffer contains "GPGGA COM2 1\r\n" */
    const char *expected = "GPGGA COM2 1\r\n";
    ASSERT_TRUE(mock_uart_tx_len == strlen(expected), "TX length");
    ASSERT_TRUE(memcmp(mock_uart_tx_buf, expected, strlen(expected)) == 0,
        "TX content should be 'GPGGA COM2 1\\r\\n'");
    PASS();
 }
 static void test_send_command_null_safety(void)
 {
    TEST("send_command: NULL gps returns false");
    ASSERT_FALSE(um982_send_command(NULL, "RESET"), "should return false");
    PASS();
 }
 /* ========================= Init sequence tests ======================= */
 static void test_init_sends_correct_commands(void)
 {
    TEST("init: sends correct command sequence");
    spy_reset();
    mock_uart_tx_clear();
    /* Pre-load VERSIONA response so init succeeds */
    const char *ver_resp = "#VERSIONA,79,GPS,FINE,2326,378237000,15434,0,18,889;\"UM982\"\r\n";
    mock_uart_rx_load(&huart5, (const uint8_t *)ver_resp, (uint16_t)strlen(ver_resp));
    UM982_GPS_t init_gps;
    bool ok = um982_init(&init_gps, &huart5, 50.0f, 3.0f);
    ASSERT_TRUE(ok, "init should succeed");
    ASSERT_TRUE(init_gps.initialized, "should be initialized");
    /* Verify TX buffer contains expected commands */
    const char *tx = (const char *)mock_uart_tx_buf;
    ASSERT_TRUE(strstr(tx, "UNLOG\r\n") != NULL, "should send UNLOG");
    ASSERT_TRUE(strstr(tx, "CONFIG HEADING FIXLENGTH\r\n") != NULL, "should send CONFIG HEADING");
    ASSERT_TRUE(strstr(tx, "CONFIG HEADING LENGTH 50 3\r\n") != NULL, "should send LENGTH");
    ASSERT_TRUE(strstr(tx, "GPGGA COM2 1\r\n") != NULL, "should enable GGA");
    ASSERT_TRUE(strstr(tx, "GPRMC COM2 1\r\n") != NULL, "should enable RMC");
    ASSERT_TRUE(strstr(tx, "GPTHS COM2 0.2\r\n") != NULL, "should enable THS at 5Hz");
    ASSERT_TRUE(strstr(tx, "SAVECONFIG\r\n") == NULL, "should NOT save config (NVM wear)");
    ASSERT_TRUE(strstr(tx, "VERSIONA\r\n") != NULL, "should query version");
    /* Verify command order: UNLOG should come before GPGGA */
    const char *unlog_pos = strstr(tx, "UNLOG\r\n");
    const char *gpgga_pos = strstr(tx, "GPGGA COM2 1\r\n");
    ASSERT_TRUE(unlog_pos < gpgga_pos, "UNLOG should precede GPGGA");
    PASS();
 }
 static void test_init_no_baseline(void)
 {
    TEST("init: baseline=0 skips LENGTH command");
    spy_reset();
    mock_uart_tx_clear();
    const char *ver_resp = "#VERSIONA,79,GPS,FINE,2326,378237000,15434,0,18,889;\"UM982\"\r\n";
    mock_uart_rx_load(&huart5, (const uint8_t *)ver_resp, (uint16_t)strlen(ver_resp));
    UM982_GPS_t init_gps;
    um982_init(&init_gps, &huart5, 0.0f, 0.0f);
    const char *tx = (const char *)mock_uart_tx_buf;
    ASSERT_TRUE(strstr(tx, "CONFIG HEADING LENGTH") == NULL, "should NOT send LENGTH");
    PASS();
 }
 static void test_init_fails_no_version(void)
 {
    TEST("init: fails if no VERSIONA response");
    spy_reset();
    mock_uart_tx_clear();
    /* Don't load any RX data — init should timeout */
    UM982_GPS_t init_gps;
    bool ok = um982_init(&init_gps, &huart5, 50.0f, 3.0f);
    ASSERT_FALSE(ok, "init should fail without version response");
    ASSERT_FALSE(init_gps.initialized, "should not be initialized");
    PASS();
 }
 static void test_nmea_traffic_sets_initialized_without_versiona(void)
 {
    TEST("init state: supported NMEA traffic sets initialized");
    reset_gps();
    ASSERT_FALSE(gps.initialized, "should start uninitialized");
    um982_parse_sentence(&gps, "$GNTHS,341.3344,A*1F");
    ASSERT_TRUE(gps.initialized, "supported NMEA should mark communication alive");
    PASS();
 }
 /* ========================= Edge case tests =========================== */
 static void test_empty_fields_handled(void)
 {
    TEST("edge: GGA with empty lat/lon fields");
    reset_gps();
    gps.latitude = 99.99;
    gps.longitude = 99.99;
    /* GGA with empty position fields (no fix) */
    um982_parse_sentence(&gps,
        "$GNGGA,235959.00,,,,,0,00,99.99,,,,,,*79");
    ASSERT_EQ_INT(gps.fix_quality, 0, "no fix");
    /* Latitude/longitude should not be updated (fields are empty) */
    ASSERT_NEAR(gps.latitude, 99.99, 0.01, "lat unchanged");
    ASSERT_NEAR(gps.longitude, 99.99, 0.01, "lon unchanged");
    PASS();
 }
 static void test_sentence_too_short(void)
 {
    TEST("edge: sentence too short to have formatter");
    reset_gps();
    /* Should not crash */
    um982_parse_sentence(&gps, "$GN");
    um982_parse_sentence(&gps, "$");
    um982_parse_sentence(&gps, "");
    um982_parse_sentence(&gps, NULL);
    PASS();
 }
 static void test_line_overflow(void)
 {
    TEST("edge: oversized line is dropped");
    reset_gps();
    /* Create a line longer than UM982_LINE_BUF_SIZE */
    char big[200];
    memset(big, 'X', sizeof(big));
    big[0] = '$';
    big[198] = '\n';
    big[199] = '\0';
    um982_feed(&gps, (const uint8_t *)big, 199);
    /* Should not crash, heading should still be NAN */
    ASSERT_NAN(gps.heading, "no valid data from overflow");
    PASS();
 }
 static void test_process_via_mock_uart(void)
 {
    TEST("process: reads from mock UART RX buffer");
    reset_gps();
    mock_set_tick(5000);
    /* Load data into mock UART RX */
    const char *data = "$GNTHS,275.1234,D*18\r\n";
    mock_uart_rx_load(&huart5, (const uint8_t *)data, (uint16_t)strlen(data));
    /* Call process() which reads from UART */
    um982_process(&gps);
    ASSERT_NEAR(gps.heading, 275.1234, 0.001, "heading via process()");
    ASSERT_EQ_INT(gps.heading_mode, 'D', "mode D");
    PASS();
 }
 /* ========================= PR #68 bug regression tests =============== */
 /* These tests specifically verify the bugs found in the reverted PR #68 */
 static void test_regression_sentence_id_with_gn_prefix(void)
 {
    TEST("regression: GN-prefixed GGA is correctly identified");
    reset_gps();
    /* PR #68 bug: strncmp(sentence, "GGA", 3) compared "GNG" vs "GGA" — never matched.
     * Our fix: skip 2-char talker ID, compare at sentence+3. */
    um982_parse_sentence(&gps,
        "$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
    ASSERT_EQ_INT(gps.fix_quality, 1, "GGA should parse with GN prefix");
    ASSERT_NEAR(gps.latitude, 44.069006, 0.001, "latitude should be parsed");
    PASS();
 }
 static void test_regression_longitude_3digit_degrees(void)
 {
    TEST("regression: 3-digit longitude degrees parsed correctly");
    reset_gps();
    /* PR #68 bug: hardcoded 2-digit degrees for longitude.
     * 12118.85961 should be 121° 18.85961' = 121.314327° */
    um982_parse_sentence(&gps,
        "$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
    ASSERT_NEAR(gps.longitude, -(121.0 + 18.85961/60.0), 0.0001,
        "longitude 121° should not be parsed as 12°");
    ASSERT_TRUE(gps.longitude < -100.0, "longitude should be > 100 degrees");
    PASS();
 }
 static void test_regression_hemisphere_no_ptr_corrupt(void)
 {
    TEST("regression: hemisphere parsing doesn't corrupt field pointer");
    reset_gps();
    /* PR #68 bug: GGA/RMC hemisphere cases manually advanced ptr,
     * desynchronizing from field counter. Our parser uses proper tokenizer. */
    um982_parse_sentence(&gps,
        "$GNGGA,001043.00,4404.14036,N,12118.85961,W,1,12,0.98,1113.0,M,-21.3,M*47");
    /* After lat/lon, remaining fields should be correct */
    ASSERT_EQ_INT(gps.num_satellites, 12, "sats after hemisphere");
    ASSERT_NEAR(gps.hdop, 0.98, 0.01, "hdop after hemisphere");
    ASSERT_NEAR(gps.altitude, 1113.0, 0.1, "altitude after hemisphere");
    PASS();
 }
 static void test_regression_rmc_also_parsed(void)
 {
    TEST("regression: RMC sentence is actually parsed (not dead code)");
    reset_gps();
    /* PR #68 bug: identifySentence never matched GGA/RMC, so position
     * parsing was dead code. */
    um982_parse_sentence(&gps,
        "$GNRMC,001031.00,A,4404.13993,N,12118.86023,W,0.146,,100117,,,A*7B");
    ASSERT_TRUE(gps.latitude > 44.0, "RMC lat should be parsed");
    ASSERT_TRUE(gps.longitude < -121.0, "RMC lon should be parsed");
    ASSERT_NEAR(gps.speed_knots, 0.146, 0.001, "RMC speed");
    PASS();
 }
 /* ========================= Main ====================================== */
 int main(void)
 {
    printf("=== UM982 GPS Driver Tests ===\n\n");
    printf("--- Checksum ---\n");
    test_checksum_valid();
    test_checksum_valid_ths();
    test_checksum_invalid();
    test_checksum_missing_star();
    test_checksum_null();
    test_checksum_no_dollar();
    printf("\n--- Coordinate Parsing ---\n");
    test_coord_latitude_north();
    test_coord_latitude_south();
    test_coord_longitude_3digit();
    test_coord_longitude_east();
    test_coord_empty();
    test_coord_null();
    test_coord_no_dot();
    printf("\n--- GGA Parsing ---\n");
    test_parse_gga_full();
    test_parse_gga_rtk_fixed();
    test_parse_gga_no_fix();
    printf("\n--- RMC Parsing ---\n");
    test_parse_rmc_valid();
    test_parse_rmc_void();
    printf("\n--- THS Parsing ---\n");
    test_parse_ths_autonomous();
    test_parse_ths_not_valid();
    test_parse_ths_zero();
    test_parse_ths_360_boundary();
    printf("\n--- VTG Parsing ---\n");
    test_parse_vtg();
    printf("\n--- Talker IDs ---\n");
    test_talker_gp();
    test_talker_gl();
    printf("\n--- Feed / Line Assembly ---\n");
    test_feed_single_sentence();
    test_feed_multiple_sentences();
    test_feed_partial_then_complete();
    test_feed_bad_checksum_rejected();
    test_feed_versiona_response();
    printf("\n--- Validity / Age ---\n");
    test_heading_valid_within_timeout();
    test_heading_invalid_after_timeout();
    test_heading_invalid_mode_v();
    test_position_valid();
    test_position_invalid_no_fix();
    test_position_age_uses_last_valid_fix();
    test_heading_age();
    printf("\n--- Send Command ---\n");
    test_send_command_appends_crlf();
    test_send_command_null_safety();
    printf("\n--- Init Sequence ---\n");
    test_init_sends_correct_commands();
    test_init_no_baseline();
    test_init_fails_no_version();
    test_nmea_traffic_sets_initialized_without_versiona();
    printf("\n--- Edge Cases ---\n");
    test_empty_fields_handled();
    test_sentence_too_short();
    test_line_overflow();
    test_process_via_mock_uart();
    printf("\n--- PR #68 Regression ---\n");
    test_regression_sentence_id_with_gn_prefix();
    test_regression_longitude_3digit_degrees();
    test_regression_hemisphere_no_ptr_corrupt();
    test_regression_rmc_also_parsed();
    printf("\n===============================================\n");
    printf("  Results: %d passed, %d failed (of %d total)\n",
           tests_passed, tests_failed, tests_passed + tests_failed);
    printf("===============================================\n");
    return tests_failed > 0 ? 1 : 0;
 }
@@ -16,9 +16,9 @@
 *
 *   Phase 2 (CFAR): After frame_complete pulse from Doppler processor,
 *     process each Doppler column independently:
- *     a) Read 512 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
+ *     a) Read 64 magnitudes from BRAM for one Doppler bin (ST_COL_LOAD)
 *     b) Compute initial sliding window sums (ST_CFAR_INIT)
- *     c) Slide CUT through all 512 range bins:
+ *     c) Slide CUT through all 64 range bins:
 *        - 3 sub-cycles per CUT:
 *          ST_CFAR_THR: register noise_sum (mode select + cross-multiply)
 *          ST_CFAR_MUL: compute alpha * noise_sum_reg in DSP
@@ -47,23 +47,21 @@
 *   typically clutter).
 *
 * Timing:
- *   Phase 2 takes ~(514 + T + 3*512) * 32 ≈ 55000 cycles per frame @ 100 MHz
+ *   Phase 2 takes ~(66 + T + 3*64) * 32 ≈ 8500 cycles per frame @ 100 MHz
- *   = 0.55 ms. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
+ *   = 85 µs. Frame period @ PRF=1932 Hz, 32 chirps = 16.6 ms. Fits easily.
 *   (3 cycles per CUT due to pipeline: THR → MUL → CMP)
 *
 * Resources:
- *   - 1 BRAM36K for magnitude buffer (16384 x 17 bits)
+ *   - 1 BRAM18K for magnitude buffer (2048 x 17 bits)
 *   - 1 DSP48 for alpha multiply
 *   - ~300 LUTs for FSM + sliding window + comparators
 *
 * Clock domain: clk (100 MHz, same as Doppler processor)
 */
 `include "radar_params.vh"
 module cfar_ca #(
-    parameter NUM_RANGE_BINS   = `RP_NUM_RANGE_BINS,    // 512
+    parameter NUM_RANGE_BINS   = 64,
-    parameter NUM_DOPPLER_BINS = `RP_NUM_DOPPLER_BINS,  // 32
+    parameter NUM_DOPPLER_BINS = 32,
    parameter MAG_WIDTH        = 17,
    parameter ALPHA_WIDTH      = 8,
    parameter MAX_GUARD        = 8,
@@ -76,7 +74,7 @@ module cfar_ca #(
    input wire [31:0] doppler_data,
    input wire        doppler_valid,
    input wire [4:0]  doppler_bin_in,
-    input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in,  // 9-bit
+    input wire [5:0]  range_bin_in,
    input wire        frame_complete,
    // ========== CONFIGURATION ==========
@@ -90,7 +88,7 @@ module cfar_ca #(
    // ========== DETECTION OUTPUTS ==========
    output reg        detect_flag,
    output reg        detect_valid,
-    output reg [`RP_RANGE_BIN_BITS-1:0] detect_range,  // 9-bit
+    output reg [5:0]  detect_range,
    output reg [4:0]  detect_doppler,
    output reg [MAG_WIDTH-1:0] detect_magnitude,
    output reg [MAG_WIDTH-1:0] detect_threshold,
@@ -105,11 +103,11 @@ module cfar_ca #(
 // INTERNAL PARAMETERS
 // ============================================================================
 localparam TOTAL_CELLS = NUM_RANGE_BINS * NUM_DOPPLER_BINS;
-localparam ADDR_WIDTH  = `RP_CFAR_MAG_ADDR_W;  // 14
+localparam ADDR_WIDTH  = 11;
 localparam COL_BITS    = 5;
-localparam ROW_BITS    = `RP_RANGE_BIN_BITS;    // 9
+localparam ROW_BITS    = 6;
-localparam SUM_WIDTH   = MAG_WIDTH + ROW_BITS;  // 26 bits: sum of up to 512 magnitudes
+localparam SUM_WIDTH   = MAG_WIDTH + 6;  // 23 bits: sum of up to 64 magnitudes
-localparam PROD_WIDTH  = SUM_WIDTH + ALPHA_WIDTH;  // 34 bits
+localparam PROD_WIDTH  = SUM_WIDTH + ALPHA_WIDTH;  // 31 bits
 localparam ALPHA_FRAC_BITS = 4;  // Q4.4
 // ============================================================================
@@ -138,7 +136,7 @@ wire [15:0] abs_q = dop_q[15] ? (~dop_q + 16'd1) : dop_q;
 wire [MAG_WIDTH-1:0] cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
 // ============================================================================
-// MAGNITUDE BRAM (16384 x 17 bits)
+// MAGNITUDE BRAM (2048 x 17 bits)
 // ============================================================================
 reg                    mag_we;
 reg [ADDR_WIDTH-1:0]   mag_waddr;
@@ -155,7 +153,7 @@ always @(posedge clk) begin
 end
 // ============================================================================
-// COLUMN LINE BUFFER (512 x 17 bits — BRAM)
+// COLUMN LINE BUFFER (64 x 17 bits — distributed RAM)
 // ============================================================================
 reg [MAG_WIDTH-1:0] col_buf [0:NUM_RANGE_BINS-1];
 reg [ROW_BITS:0] col_load_idx;
@@ -208,31 +206,20 @@ wire lead_rem_valid = (lead_rem_idx >= 0) && (lead_rem_idx < NUM_RANGE_BINS);
 wire lag_rem_valid  = (lag_rem_idx  >= 0) && (lag_rem_idx  < NUM_RANGE_BINS);
 wire lag_add_valid  = (lag_add_idx  >= 0) && (lag_add_idx  < NUM_RANGE_BINS);
-// Safe col_buf read with bounds checking (combinational — feeds pipeline regs)
+// Safe col_buf read with bounds checking (combinational)
 wire [MAG_WIDTH-1:0] lead_add_val = lead_add_valid ? col_buf[lead_add_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lead_rem_val = lead_rem_valid ? col_buf[lead_rem_idx[ROW_BITS-1:0]] : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lag_rem_val  = lag_rem_valid  ? col_buf[lag_rem_idx[ROW_BITS-1:0]]  : {MAG_WIDTH{1'b0}};
 wire [MAG_WIDTH-1:0] lag_add_val  = lag_add_valid  ? col_buf[lag_add_idx[ROW_BITS-1:0]]  : {MAG_WIDTH{1'b0}};
-// ============================================================================
+// Net deltas
-// PIPELINE REGISTERS: Break col_buf mux tree out of ST_CFAR_CMP critical path
+wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid ? $signed({1'b0, lead_add_val}) : 0)
-// ============================================================================
+                                      - (lead_rem_valid ? $signed({1'b0, lead_rem_val}) : 0);
-// Captured in ST_CFAR_THR (col_buf indices depend only on cut_idx/r_guard/r_train,
+wire signed [1:0] lead_cnt_delta = (lead_add_valid ? 1 : 0) - (lead_rem_valid ? 1 : 0);
 // all stable during THR). Used in ST_CFAR_CMP for delta/sum computation.
 // This removes ~6-8 logic levels (9-level mux tree) from the CMP critical path.
 reg [MAG_WIDTH-1:0] lead_add_val_r, lead_rem_val_r;
 reg [MAG_WIDTH-1:0] lag_rem_val_r,  lag_add_val_r;
 reg                 lead_add_valid_r, lead_rem_valid_r;
 reg                 lag_rem_valid_r,  lag_add_valid_r;
-// Net deltas (computed from registered col_buf values — combinational in CMP)
+wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid ? $signed({1'b0, lag_add_val}) : 0)
-wire signed [SUM_WIDTH:0] lead_delta = (lead_add_valid_r ? $signed({1'b0, lead_add_val_r}) : 0)
+                                     - (lag_rem_valid ? $signed({1'b0, lag_rem_val}) : 0);
-                                      - (lead_rem_valid_r ? $signed({1'b0, lead_rem_val_r}) : 0);
+wire signed [1:0] lag_cnt_delta = (lag_add_valid ? 1 : 0) - (lag_rem_valid ? 1 : 0);
 wire signed [1:0] lead_cnt_delta = (lead_add_valid_r ? 1 : 0) - (lead_rem_valid_r ? 1 : 0);
 wire signed [SUM_WIDTH:0] lag_delta = (lag_add_valid_r ? $signed({1'b0, lag_add_val_r}) : 0)
                                     - (lag_rem_valid_r ? $signed({1'b0, lag_rem_val_r}) : 0);
 wire signed [1:0] lag_cnt_delta = (lag_add_valid_r ? 1 : 0) - (lag_rem_valid_r ? 1 : 0);
 // ============================================================================
 // NOISE ESTIMATE COMPUTATION (combinational for CFAR mode selection)
@@ -280,7 +267,7 @@ always @(posedge clk or negedge reset_n) begin
        state          <= ST_IDLE;
        detect_flag    <= 1'b0;
        detect_valid   <= 1'b0;
-        detect_range   <= {ROW_BITS{1'b0}};
+        detect_range   <= 6'd0;
        detect_doppler <= 5'd0;
        detect_magnitude <= {MAG_WIDTH{1'b0}};
        detect_threshold <= {MAG_WIDTH{1'b0}};
@@ -301,14 +288,6 @@ always @(posedge clk or negedge reset_n) begin
        noise_sum_reg  <= 0;
        noise_product  <= 0;
        adaptive_thr   <= 0;
        lead_add_val_r <= 0;
        lead_rem_val_r <= 0;
        lag_rem_val_r  <= 0;
        lag_add_val_r  <= 0;
        lead_add_valid_r <= 0;
        lead_rem_valid_r <= 0;
        lag_rem_valid_r  <= 0;
        lag_add_valid_r  <= 0;
        r_guard        <= 4'd2;
        r_train        <= 5'd8;
        r_alpha        <= 8'h30;
@@ -385,7 +364,7 @@ always @(posedge clk or negedge reset_n) begin
                if (r_enable) begin
                    col_idx      <= 0;
                    col_load_idx <= 0;
-                    mag_raddr    <= {{ROW_BITS{1'b0}}, 5'd0};
+                    mag_raddr    <= {6'd0, 5'd0};
                    state        <= ST_COL_LOAD;
                end else begin
                    state <= ST_DONE;
@@ -403,14 +382,14 @@ always @(posedge clk or negedge reset_n) begin
            if (col_load_idx == 0) begin
                // First address already presented, advance to range=1
-                mag_raddr    <= {{{(ROW_BITS-1){1'b0}}, 1'b1}, col_idx};
+                mag_raddr    <= {6'd1, col_idx};
                col_load_idx <= 1;
            end else if (col_load_idx <= NUM_RANGE_BINS) begin
                // Capture previous read
                col_buf[col_load_idx - 1] <= mag_rdata;
                if (col_load_idx < NUM_RANGE_BINS) begin
-                    mag_raddr <= {col_load_idx[ROW_BITS-1:0] + {{(ROW_BITS-1){1'b0}}, 1'b1}, col_idx};
+                    mag_raddr <= {col_load_idx[ROW_BITS-1:0] + 6'd1, col_idx};
                end
                col_load_idx <= col_load_idx + 1;
@@ -462,19 +441,6 @@ always @(posedge clk or negedge reset_n) begin
            cfar_status <= {4'd4, 1'b0, col_idx[2:0]};
            noise_sum_reg <= noise_sum_comb;
            // Pipeline: register col_buf reads for next CUT's window update.
            // Indices depend only on cut_idx/r_guard/r_train (all stable here).
            // Breaks the 9-level col_buf mux tree out of ST_CFAR_CMP.
            lead_add_val_r   <= lead_add_val;
            lead_rem_val_r   <= lead_rem_val;
            lag_rem_val_r    <= lag_rem_val;
            lag_add_val_r    <= lag_add_val;
            lead_add_valid_r <= lead_add_valid;
            lead_rem_valid_r <= lead_rem_valid;
            lag_rem_valid_r  <= lag_rem_valid;
            lag_add_valid_r  <= lag_add_valid;
            state <= ST_CFAR_MUL;
        end
@@ -547,7 +513,7 @@ always @(posedge clk or negedge reset_n) begin
            if (col_idx < NUM_DOPPLER_BINS - 1) begin
                col_idx      <= col_idx + 1;
                col_load_idx <= 0;
-                mag_raddr    <= {{ROW_BITS{1'b0}}, col_idx + 5'd1};
+                mag_raddr    <= {6'd0, col_idx + 5'd1};
                state        <= ST_COL_LOAD;
            end else begin
                state <= ST_DONE;
@@ -4,6 +4,10 @@ module chirp_memory_loader_param #(
    parameter LONG_Q_FILE_SEG0 = "long_chirp_seg0_q.mem",
    parameter LONG_I_FILE_SEG1 = "long_chirp_seg1_i.mem",
    parameter LONG_Q_FILE_SEG1 = "long_chirp_seg1_q.mem",
    parameter LONG_I_FILE_SEG2 = "long_chirp_seg2_i.mem",
    parameter LONG_Q_FILE_SEG2 = "long_chirp_seg2_q.mem",
    parameter LONG_I_FILE_SEG3 = "long_chirp_seg3_i.mem",
    parameter LONG_Q_FILE_SEG3 = "long_chirp_seg3_q.mem",
    parameter SHORT_I_FILE = "short_chirp_i.mem",
    parameter SHORT_Q_FILE = "short_chirp_q.mem",
    parameter DEBUG = 1
@@ -13,17 +17,17 @@ module chirp_memory_loader_param #(
    input wire [1:0] segment_select,
    input wire mem_request,
    input wire use_long_chirp,
-    input wire [10:0] sample_addr,
+    input wire [9:0] sample_addr,
    output reg [15:0] ref_i,
    output reg [15:0] ref_q,
    output reg mem_ready
 );
-// Memory declarations — 2 long segments × 2048 = 4096 samples
+// Memory declarations - now 4096 samples for 4 segments
 (* ram_style = "block" *) reg [15:0] long_chirp_i [0:4095];
 (* ram_style = "block" *) reg [15:0] long_chirp_q [0:4095];
-(* ram_style = "block" *) reg [15:0] short_chirp_i [0:2047];
+(* ram_style = "block" *) reg [15:0] short_chirp_i [0:1023];
-(* ram_style = "block" *) reg [15:0] short_chirp_q [0:2047];
+(* ram_style = "block" *) reg [15:0] short_chirp_q [0:1023];
 // Initialize memory
 integer i;
@@ -31,47 +35,66 @@ integer i;
 initial begin
    `ifdef SIMULATION
    if (DEBUG) begin
-        $display("[MEM] Starting memory initialization for 2 long chirp segments");
+        $display("[MEM] Starting memory initialization for 4 long chirp segments");
    end
    `endif
-    // === LOAD LONG CHIRP — 2 SEGMENTS ===
+    // === LOAD LONG CHIRP - 4 SEGMENTS ===
-    // Segment 0 (addresses 0-2047)
+    // Segment 0 (addresses 0-1023)
-    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 2047);
+    $readmemh(LONG_I_FILE_SEG0, long_chirp_i, 0, 1023);
-    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 2047);
+    $readmemh(LONG_Q_FILE_SEG0, long_chirp_q, 0, 1023);
    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-2047)");
+    if (DEBUG) $display("[MEM] Loaded long chirp segment 0 (0-1023)");
    `endif
-    // Segment 1 (addresses 2048-4095)
+    // Segment 1 (addresses 1024-2047)
-    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 2048, 4095);
+    $readmemh(LONG_I_FILE_SEG1, long_chirp_i, 1024, 2047);
-    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 2048, 4095);
+    $readmemh(LONG_Q_FILE_SEG1, long_chirp_q, 1024, 2047);
    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (2048-4095)");
+    if (DEBUG) $display("[MEM] Loaded long chirp segment 1 (1024-2047)");
    `endif
    // Segment 2 (addresses 2048-3071)
    $readmemh(LONG_I_FILE_SEG2, long_chirp_i, 2048, 3071);
    $readmemh(LONG_Q_FILE_SEG2, long_chirp_q, 2048, 3071);
    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Loaded long chirp segment 2 (2048-3071)");
    `endif
    // Segment 3 (addresses 3072-4095)
    $readmemh(LONG_I_FILE_SEG3, long_chirp_i, 3072, 4095);
    $readmemh(LONG_Q_FILE_SEG3, long_chirp_q, 3072, 4095);
    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Loaded long chirp segment 3 (3072-4095)");
    `endif
    // === LOAD SHORT CHIRP ===
-    // Load first 50 samples (0-49)
+    // Load first 50 samples (0-49). Explicit range prevents iverilog warning
    // about insufficient words for the full [0:1023] array.
    $readmemh(SHORT_I_FILE, short_chirp_i, 0, 49);
    $readmemh(SHORT_Q_FILE, short_chirp_q, 0, 49);
    `ifdef SIMULATION
    if (DEBUG) $display("[MEM] Loaded short chirp (0-49)");
    `endif
-    // Zero pad remaining samples (50-2047)
+    // Zero pad remaining 974 samples (50-1023)
-    for (i = 50; i < 2048; i = i + 1) begin
+    for (i = 50; i < 1024; i = i + 1) begin
        short_chirp_i[i] = 16'h0000;
        short_chirp_q[i] = 16'h0000;
    end
    `ifdef SIMULATION
-    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-2047");
+    if (DEBUG) $display("[MEM] Zero-padded short chirp from 50-1023");
    // === VERIFICATION ===
    if (DEBUG) begin
        $display("[MEM] Memory loading complete. Verification samples:");
        $display("  Long[0]:     I=%h Q=%h", long_chirp_i[0], long_chirp_q[0]);
        $display("  Long[1023]:  I=%h Q=%h", long_chirp_i[1023], long_chirp_q[1023]);
        $display("  Long[1024]:  I=%h Q=%h", long_chirp_i[1024], long_chirp_q[1024]);
        $display("  Long[2047]:  I=%h Q=%h", long_chirp_i[2047], long_chirp_q[2047]);
        $display("  Long[2048]:  I=%h Q=%h", long_chirp_i[2048], long_chirp_q[2048]);
        $display("  Long[3071]:  I=%h Q=%h", long_chirp_i[3071], long_chirp_q[3071]);
        $display("  Long[3072]:  I=%h Q=%h", long_chirp_i[3072], long_chirp_q[3072]);
        $display("  Long[4095]:  I=%h Q=%h", long_chirp_i[4095], long_chirp_q[4095]);
        $display("  Short[0]:    I=%h Q=%h", short_chirp_i[0], short_chirp_q[0]);
        $display("  Short[49]:   I=%h Q=%h", short_chirp_i[49], short_chirp_q[49]);
@@ -81,8 +104,8 @@ initial begin
 end
 // Memory access logic
-// long_addr: segment_select[0] selects segment (0 or 1), sample_addr[10:0] selects within
+// long_addr is combinational — segment_select[1:0] concatenated with sample_addr[9:0]
-wire [11:0] long_addr = {segment_select[0], sample_addr};
+wire [11:0] long_addr = {segment_select, sample_addr};
 // ---- BRAM read block (sync-only, sync reset) ----
 // REQP-1839/1840 fix: BRAM output registers cannot have async resets.
@@ -105,7 +128,7 @@ always @(posedge clk) begin
            end
            `endif
        end else begin
-            // Short chirp (0-2047)
+            // Short chirp (0-1023)
            ref_i <= short_chirp_i[sample_addr];
            ref_q <= short_chirp_q[sample_addr];
@@ -1,7 +1,6 @@
 module cic_decimator_4x_enhanced (
    input wire clk,                 // 400MHz input clock
    input wire reset_n,
    input wire reset_h,             // Pre-registered active-high reset from parent (avoids LUT1 inverter)
    input wire signed [17:0] data_in,  // 18-bit input
    input wire data_valid,
    output reg signed [17:0] data_out, // 18-bit output
@@ -33,15 +32,50 @@ localparam COMB_WIDTH = 28;
 // adjacent DSP48E1 tiles — zero fabric delay, guaranteed to meet 400+ MHz
 // on 7-series regardless of speed grade.
 //
-// Active-high reset provided by parent module (pre-registered).
+// Active-high reset derived from reset_n (inverted and REGISTERED).
 // CEP (clock enable for P register) gated by data_valid.
-// ============================================================================
+//
-
+// ----------------------------------------------------------------------------
-// reset_h is now an input port from parent module (pre-registered active-high).
+// RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
-// Previously: wire reset_h = ~reset_n; — this LUT1 inverter + long routing to
+// ----------------------------------------------------------------------------
-// 8 DSP48E1 RSTB pins was the root cause of 400 MHz timing failure (WNS=-0.074ns).
+// Previously this was a combinational wire (`wire reset_h = ~reset_n`). Vivado
-// The parent ddc_400m.v already has a registered reset_400m derived from
+// collapsed all per-module inversions across the DDC hierarchy into a SINGLE
-// the 2-stage sync reset, so we use that directly.
+// shared LUT1, whose output fanned out to 702 loads (DSP48E1 RSTP/RSTB/RSTC
 // plus FDRE R pins of all comb-stage DSP48E1s inferred via use_dsp="yes").
 // Route delay alone on that net was 2.019–2.268 ns — nearly one full 2.5 ns
 // period. Timing failed by 626 ps on the 400 MHz domain.
 //
 // Fix: convert reset_h to a REGISTERED signal with (* max_fanout = 50 *).
 // Vivado treats max_fanout on a REG (not a wire) as authoritative and
 // replicates the register into N copies, each placed near its ≈50 loads.
 // Invariants preserved:
 //   I1 (correctness):       reset_h is still active-high, equals ~reset_n
 //                           after one clk edge; CIC reset is a RECEIVER-side
 //                           synchronizer anyway (driven by reset_n_400m which
 //                           is already sync'd in the parent DDC), so adding
 //                           one more clk cycle of latency is safe.
 //   I2 (glitch-free):       Registered output => inherently glitch-free,
 //                           feeding DSP48E1 RST pins (which are synchronous
 //                           to CLK, so they capture on the same edge anyway).
 //   I3 (power-up safety):   reset_h is NOT async-reset itself. On power-up,
 //                           FDRE INIT=0 starts reset_h LOW. First clk edge
 //                           samples ~reset_n which is LOW on power-up (the
 //                           parent DDC holds reset_n_400m low until the 2-
 //                           stage synchronizer releases), so reset_h goes
 //                           HIGH on cycle 1 and all DSPs see reset during
 //                           the following cycles. System is held in reset
 //                           for enough cycles that any initial register
 //                           state garbage is overwritten. ✅
 //   I4 (reset de-assertion):reset_h goes LOW one cycle AFTER reset_n_400m
 //                           goes HIGH. Downstream DSPs come out of reset on
 //                           the next clk edge after that. Total latency
 //                           from system reset release to first valid sample:
 //                           2 (sync chain) + 1 (reset_h reg) + 1 (first
 //                           DSP output) = 4 cycles at 400 MHz = 10 ns.
 //                           Negligible vs system reset assertion duration.
 // ----------------------------------------------------------------------------
 (* max_fanout = 50 *) reg reset_h = 1'b1;  // INIT=1'b1: registers start in reset state on power-up
 always @(posedge clk) reset_h <= ~reset_n;
 // Sign-extended input for integrator_0 C port (48-bit)
 wire [ACC_WIDTH-1:0] data_in_c = {{(ACC_WIDTH-18){data_in[17]}}, data_in};
@@ -704,8 +738,9 @@ initial begin
 end
 // Decimation control + monitoring (integrators are now DSP48E1 instances)
-// Sync reset: enables FDRE inference for better timing at 400 MHz.
+// Sync reset via reset_h (registered, max_fanout=50) — eliminates the shared
-// Reset is already synchronous to clk via reset synchronizer in parent module.
+// LUT1 inverter that previously fanned out to all fabric FDRE R pins plus
 // DSP48E1 RST pins (702 loads total). See "RESET FAN-OUT INVARIANT" at top.
 always @(posedge clk) begin
    if (reset_h) begin
        integrator_sampled <= 0;
@@ -760,7 +795,7 @@ always @(posedge clk) begin
 end
 // Pipeline the valid signal for comb section
-// Sync reset: matches decimation control block reset style.
+// Sync reset via reset_h — same replicated-register source as DSP48E1 RSTs.
 always @(posedge clk) begin
    if (reset_h) begin
        data_valid_comb <= 0;
@@ -32,8 +32,8 @@ the `USB_MODE` parameter in `radar_system_top.v`:
 | USB_MODE | Interface | Bus Width | Speed | Board Target |
 |----------|-----------|-----------|-------|--------------|
-| 0 (default) | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
+| 0 | FT601 (USB 3.0) | 32-bit | 100 MHz | 200T premium dev board |
-| 1 | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
+| 1 (default) | FT2232H (USB 2.0) | 8-bit | 60 MHz | 50T production board |
 ### How USB_MODE Works
@@ -72,7 +72,8 @@ The parameter is set via a **wrapper module** that overrides the default:
  ```
 - **200T dev board**: `radar_system_top` is used directly as the top module.
-  `USB_MODE` defaults to `0` (FT601). No wrapper needed.
+  `USB_MODE` defaults to `1` (FT2232H) since production is the primary target.
  Override with `.USB_MODE(0)` for FT601 builds.
 ### RTL Files by USB Interface
@@ -158,7 +159,7 @@ The build scripts automatically select the correct top module and constraints:
 You do NOT need to set `USB_MODE` manually. The top module selection handles it:
 - `radar_system_top_50t` forces `USB_MODE=1` internally
- `radar_system_top` defaults to `USB_MODE=0`
+- `radar_system_top` defaults to `USB_MODE=1` (FT2232H, production default)
 ## How to Select Constraints in Vivado
@@ -190,9 +191,9 @@ read_xdc constraints/te0713_te0701_minimal.xdc
 | Target | Top module | USB_MODE | USB Interface | Notes |
 |--------|------------|----------|---------------|-------|
 | 50T Production (FTG256) | `radar_system_top_50t` | 1 | FT2232H (8-bit) | Wrapper sets USB_MODE=1, ties off FT601 |
-| 200T Dev (FBG484) | `radar_system_top` | 0 (default) | FT601 (32-bit) | No wrapper needed |
+| 200T Dev (FBG484) | `radar_system_top` | 0 (override) | FT601 (32-bit) | Build script overrides default USB_MODE=1 |
-| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (default) | FT601 (32-bit) | Minimal bring-up wrapper |
+| Trenz TE0712/TE0701 | `radar_system_top_te0712_dev` | 0 (override) | FT601 (32-bit) | Minimal bring-up wrapper |
-| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (default) | FT601 (32-bit) | Alternate SoM wrapper |
+| Trenz TE0713/TE0701 | `radar_system_top_te0713_dev` | 0 (override) | FT601 (32-bit) | Alternate SoM wrapper |
 ## Trenz Split Status
@@ -70,9 +70,10 @@ set_input_jitter [get_clocks clk_100m] 0.1
 # NOTE: The physical DAC (U3, AD9708) receives its clock directly from the
 #       AD9523 via a separate net (DAC_CLOCK), NOT from the FPGA. The FPGA
 #       uses this clock input for internal DAC data timing only. The RTL port
-#       `dac_clk` is an output that assigns clk_120m directly — it has no
+#       `dac_clk` is an RTL output that assigns clk_120m directly. It has no
-#       separate physical pin on this board and should be removed from the
+#       physical pin on the 50T board and is left unconnected here. The port
-#       RTL or left unconnected.
+#       CANNOT be removed from the RTL because the 200T board uses it with
 #       ODDR clock forwarding (pin H17, see xc7a200t_fbg484.xdc).
 # FIX: Moved from C13 (IO_L12N = N-type) to D13 (IO_L12P = P-type MRCC).
 #      Clock inputs must use the P-type pin of an MRCC pair (PLIO-9 DRC).
 set_property PACKAGE_PIN D13 [get_ports {clk_120m_dac}]
@@ -224,7 +225,7 @@ set_property IOSTANDARD LVCMOS33 [get_ports {stm32_mixers_enable}]
 # DIG_5 = H11, DIG_6 = G12, DIG_7 = H12 — FPGA→STM32 status outputs
 # DIG_5: AGC saturation flag (PD13 on STM32)
-# DIG_6: reserved (PD14)
+# DIG_6: AGC enable flag (PD14) — mirrors FPGA host_agc_enable to STM32
 # DIG_7: reserved (PD15)
 set_property PACKAGE_PIN H11 [get_ports {gpio_dig5}]
 set_property PACKAGE_PIN G12 [get_ports {gpio_dig6}]
@@ -332,6 +333,44 @@ set_property DRIVE 8 [get_ports {ft_data[*]}]
 # ft_clkout constrained above in CLOCK CONSTRAINTS section (C4, 60 MHz)
 # --------------------------------------------------------------------------
 # FT2232H Source-Synchronous Timing Constraints
 # --------------------------------------------------------------------------
 # FT2232H 245 Synchronous FIFO mode timing (60 MHz, period = 16.667 ns):
 #
 # FPGA Read Path (FT2232H drives data, FPGA samples):
 #   - Data valid before CLKOUT rising edge: t_vr(max) = 7.0 ns
 #   - Data hold after CLKOUT rising edge:   t_hr(min) = 0.0 ns
 #   - Input delay max = period - t_vr = 16.667 - 7.0 = 9.667 ns
 #   - Input delay min = t_hr = 0.0 ns
 #
 # FPGA Write Path (FPGA drives data, FT2232H samples):
 #   - Data setup before next CLKOUT rising: t_su = 5.0 ns
 #   - Data hold after CLKOUT rising:        t_hd = 0.0 ns
 #   - Output delay max = period - t_su = 16.667 - 5.0 = 11.667 ns
 #   - Output delay min = t_hd = 0.0 ns
 # --------------------------------------------------------------------------
 # Input delays: FT2232H → FPGA (data bus and status signals)
 set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_data[*]}]
 set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_data[*]}]
 set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_rxf_n}]
 set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_rxf_n}]
 set_input_delay -clock [get_clocks ft_clkout] -max 9.667 [get_ports {ft_txe_n}]
 set_input_delay -clock [get_clocks ft_clkout] -min 0.0   [get_ports {ft_txe_n}]
 # Output delays: FPGA → FT2232H (control strobes and data bus when writing)
 set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_data[*]}]
 set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_data[*]}]
 set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_rd_n}]
 set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_rd_n}]
 set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_wr_n}]
 set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_wr_n}]
 set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_oe_n}]
 set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_oe_n}]
 set_output_delay -clock [get_clocks ft_clkout] -max 11.667 [get_ports {ft_siwu}]
 set_output_delay -clock [get_clocks ft_clkout] -min 0.0    [get_ports {ft_siwu}]
 # ============================================================================
 # STATUS / DEBUG OUTPUTS — NO PHYSICAL CONNECTIONS
 # ============================================================================
@@ -418,10 +457,10 @@ set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]
 # 4. JTAG: FPGA_TCK (L7), FPGA_TDI (N7), FPGA_TDO (N8), FPGA_TMS (M7).
 #    Dedicated pins — no XDC constraints needed.
 #
-# 5. dac_clk port: The RTL top module declares `dac_clk` as an output, but
+# 5. dac_clk port: Not connected on the 50T board (DAC clocked directly from
-#    the physical board wires the DAC clock (AD9708 CLOCK pin) directly from
+#    AD9523). The RTL port exists for 200T board compatibility, where the FPGA
-#    the AD9523, not from the FPGA. This port should be removed from the RTL
+#    forwards the DAC clock via ODDR to pin H17 with generated clock and
-#    or left unconnected. It currently just assigns clk_120m_dac passthrough.
+#    timing constraints (see xc7a200t_fbg484.xdc). Do NOT remove from RTL.
 #
 # ============================================================================
 # END OF CONSTRAINTS
@@ -53,46 +53,6 @@ reg [2:0] saturation_count;
 reg overflow_detected;
 reg [7:0] error_counter;
 // ============================================================================
 // 400 MHz Reset Synchronizer
 //
 // reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
 // Using it directly as an async reset in the 400 MHz domain causes the reset
 // deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
 // has its output fanning out to 1156 registers across the FPGA in the 400 MHz
 // domain, requiring 18.243ns of routing (WNS = -18.081ns).
 //
 // Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
 // 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
 // path from reset_n to all 400 MHz registers). Reset deassertion is
 // synchronized to clk_400m rising edge, preventing metastability.
 //
 // All 400 MHz submodules (NCO, CIC, mixers, LFSR) use reset_n_400m.
 // All 100 MHz submodules (FIR, output stage) continue using reset_n directly
 // (already synchronized to 100 MHz at radar_system_top level).
 // ============================================================================
 (* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m;
 (* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
 // Active-high reset for DSP48E1 RST ports (avoids LUT1 inverter fan-out)
 (* max_fanout = 50 *) reg reset_400m;
 always @(posedge clk_400m or negedge reset_n) begin
    if (!reset_n) begin
        reset_sync_400m <= 2'b00;
        reset_400m      <= 1'b1;
    end else begin
        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
        reset_400m      <= ~reset_sync_400m[1];
    end
 end
 // CDC synchronization for control signals (2-stage synchronizers)
 (* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
 (* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
 wire mixers_enable_sync;
 wire force_saturation_sync;
 // Debug monitoring signals
 reg [31:0] sample_counter;
 wire signed [17:0] debug_mixed_i_trunc;
@@ -130,8 +90,6 @@ reg baseband_valid_reg;
 wire [7:0] phase_dither_bits;
 reg [31:0] phase_inc_dithered;
 // ============================================================================
 // Debug Signal Assignments
 // ============================================================================
@@ -142,13 +100,66 @@ assign debug_mixed_i_trunc = mixed_i[25:8];
 assign debug_mixed_q_trunc = mixed_q[25:8];
 // ============================================================================
-// Clock Domain Crossing for Control Signals (2-stage synchronizers)
+// 400 MHz Reset Synchronizer
 //
 // reset_n arrives from the 100 MHz domain (sys_reset_n from radar_system_top).
 // Using it directly as an async reset in the 400 MHz domain causes the reset
 // deassertion edge to violate timing: the 100 MHz flip-flop driving reset_n
 // has its output fanning out to 1156 registers across the FPGA in the 400 MHz
 // domain, requiring 18.243ns of routing (WNS = -18.081ns).
 //
 // Solution: 2-stage async-assert, sync-deassert reset synchronizer in the
 // 400 MHz domain. Reset assertion is immediate (asynchronous — combinatorial
 // path from reset_n to all 400 MHz registers). Reset deassertion is
 //
 // reset_400m   : ACTIVE-HIGH registered reset with (* max_fanout = 50 *).
 //                This is THE signal fed to every synchronous 400 MHz FDRE
 //                and every DSP48E1 RST pin in this module and its children
 //                (NCO, CIC, LFSR). Vivado replicates the register (~14
 //                copies) so each replica drives ≈50 loads regionally,
 //                eliminating the single-LUT1 / 702-load net that caused
 //                WNS=-0.626 ns in Build N.
 //
 // System-level invariants preserved:
 //   I1  Reset assertion propagates to all 400 MHz regs within ≤3 clk edges
 //       (2 sync + 1 replicated-reg fanout).  At 400 MHz = 7.5 ns << any
 //       system-level reset assertion duration.
 //   I2  Reset de-assertion is always synchronous to clk_400m (via
 //       reset_sync_400m), never glitches.
 //   I3  DSP48E1 RST pins are all fed from Q of a register — glitch-free.
 //   I4  No new CDC introduced: reset_400m is entirely in clk_400m domain.
 //   I5  Power-up: reset_n is asserted externally and mmcm_locked is low;
 //       reset_sync_400m stays 2'b00, reset_400m stays 1'b1, downstream
 //       FDREs stay cleared. Safe.
 // ============================================================================
 (* ASYNC_REG = "TRUE" *) reg [1:0] reset_sync_400m = 2'b00;
 (* max_fanout = 50 *) wire reset_n_400m = reset_sync_400m[1];
 // Active-high replicated reset for all synchronous 400 MHz consumers
 (* max_fanout = 50 *) reg reset_400m = 1'b1;
 always @(posedge clk_400m or negedge reset_n) begin
    if (!reset_n) begin
        reset_sync_400m <= 2'b00;
        reset_400m      <= 1'b1;
    end else begin
        reset_sync_400m <= {reset_sync_400m[0], 1'b1};
        reset_400m      <= ~reset_sync_400m[1];
    end
 end
 // CDC synchronization for control signals (2-stage synchronizers)
 (* ASYNC_REG = "TRUE" *) reg [1:0] mixers_enable_sync_chain;
 (* ASYNC_REG = "TRUE" *) reg [1:0] force_saturation_sync_chain;
 wire mixers_enable_sync;
 wire force_saturation_sync;
 assign mixers_enable_sync = mixers_enable_sync_chain[1];
 assign force_saturation_sync = force_saturation_sync_chain[1];
-always @(posedge clk_400m or negedge reset_n_400m) begin
+// Sync reset via reset_400m (replicated, max_fanout=50). Was async on
-    if (!reset_n_400m) begin
+// reset_n_400m — see "400 MHz RESET DISTRIBUTION" comment above.
 always @(posedge clk_400m) begin
    if (reset_400m) begin
        mixers_enable_sync_chain <= 2'b00;
        force_saturation_sync_chain <= 2'b00;
    end else begin
@@ -160,8 +171,8 @@ end
 // ============================================================================
 // Sample Counter and Debug Monitoring
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m || reset_monitors) begin
+    if (reset_400m || reset_monitors) begin
        sample_counter <= 0;
        error_counter <= 0;
    end else if (adc_data_valid_i && adc_data_valid_q ) begin
@@ -189,8 +200,8 @@ lfsr_dither_enhanced #(
 localparam PHASE_INC_120MHZ = 32'h4CCCCCCD;
 // Apply dithering to reduce spurious tones (registered for 400 MHz timing)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m)
+    if (reset_400m)
        phase_inc_dithered <= PHASE_INC_120MHZ;
    else
        phase_inc_dithered <= PHASE_INC_120MHZ + {24'b0, phase_dither_bits};
@@ -229,8 +240,8 @@ assign adc_signed_w = {1'b0, adc_data, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} -
                      {1'b0, {ADC_WIDTH{1'b1}}, {(MIXER_WIDTH-ADC_WIDTH-1){1'b0}}} / 2;
 // Valid pipeline: 5-stage shift register (1 NCO pipe + 3 DSP48E1 AREG+MREG+PREG + 1 retiming)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        dsp_valid_pipe <= 5'b00000;
    end else begin
        dsp_valid_pipe <= {dsp_valid_pipe[3:0], (nco_ready && adc_data_valid_i && adc_data_valid_q)};
@@ -246,8 +257,8 @@ reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_internal, mult_q_internal;  // Mod
 reg signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_i_reg, mult_q_reg;            // Models PREG
 // Stage 0: NCO pipeline — breaks long NCO→DSP route (matches synthesis fabric registers)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        cos_nco_pipe <= 0;
        sin_nco_pipe <= 0;
    end else begin
@@ -257,8 +268,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 // Stage 1: AREG/BREG equivalent (uses pipelined NCO outputs)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        adc_signed_reg <= 0;
        cos_pipe_reg <= 0;
        sin_pipe_reg <= 0;
@@ -270,8 +281,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 // Stage 2: MREG equivalent
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        mult_i_internal <= 0;
        mult_q_internal <= 0;
    end else begin
@@ -281,8 +292,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 // Stage 3: PREG equivalent
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        mult_i_reg <= 0;
        mult_q_reg <= 0;
    end else begin
@@ -292,8 +303,8 @@ always @(posedge clk_400m or negedge reset_n_400m) begin
 end
 // Stage 4: Post-DSP retiming register (matches synthesis path)
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        mult_i_retimed <= 0;
        mult_q_retimed <= 0;
    end else begin
@@ -311,8 +322,8 @@ wire [47:0] dsp_p_i, dsp_p_q;
 // (1.505ns routing observed in Build 26). These fabric registers are placed
 // near the DSP by the placer, splitting the route into two shorter segments.
 // DONT_TOUCH on the reg declaration (above) prevents absorption/retiming.
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        cos_nco_pipe <= 0;
        sin_nco_pipe <= 0;
    end else begin
@@ -329,11 +340,10 @@ DSP48E1 #(
    .USE_DPORT("FALSE"),
    .USE_MULT("MULTIPLY"),
    .USE_SIMD("ONE48"),
    // Pipeline register attributes — all enabled for max timing
    .AREG(1),
    .BREG(1),
    .MREG(1),
-    .PREG(1),           // P register enabled — absorbs CLK→P delay for timing closure
+    .PREG(1),
    .ADREG(0),
    .ACASCREG(1),
    .BCASCREG(1),
@@ -344,7 +354,6 @@ DSP48E1 #(
    .DREG(0),
    .INMODEREG(0),
    .OPMODEREG(0),
    // Pattern detector (unused)
    .AUTORESET_PATDET("NO_RESET"),
    .MASK(48'h3fffffffffff),
    .PATTERN(48'h000000000000),
@@ -496,8 +505,8 @@ wire signed [MIXER_WIDTH+NCO_WIDTH-1:0] mult_q_reg = dsp_p_q[MIXER_WIDTH+NCO_WID
 // Stage 4: Post-DSP retiming register — breaks DSP48E1 CLK→P to fabric path
 // Without this, the DSP output prop delay (1.866ns) + routing (0.515ns) exceeds
 // the 2.500ns clock period at slow process corner
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        mult_i_retimed <= 0;
        mult_q_retimed <= 0;
    end else begin
@@ -513,8 +522,8 @@ end
 // force_saturation mux is intentionally AFTER the DSP48E1 output to avoid
 // polluting the critical input path with extra logic
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n_400m) begin
+always @(posedge clk_400m) begin
-    if (!reset_n_400m) begin
+    if (reset_400m) begin
        mixed_i <= 0;
        mixed_q <= 0;
        mixed_valid <= 0;
@@ -566,7 +575,6 @@ wire cic_valid_i, cic_valid_q;
 cic_decimator_4x_enhanced cic_i_inst (
    .clk(clk_400m),
    .reset_n(reset_n_400m),
    .reset_h(reset_400m),
    .data_in(mixed_i[33:16]),
    .data_valid(mixed_valid),
    .data_out(cic_i_out),
@@ -576,7 +584,6 @@ cic_decimator_4x_enhanced cic_i_inst (
 cic_decimator_4x_enhanced cic_q_inst (
    .clk(clk_400m),
    .reset_n(reset_n_400m),
    .reset_h(reset_400m),
    .data_in(mixed_q[33:16]),
    .data_valid(mixed_valid),
    .data_out(cic_q_out),
@@ -761,8 +768,17 @@ generate
    end
 endgenerate
-always @(posedge clk or negedge reset_n) begin
+// ============================================================================
-    if (!reset_n) begin
+// RESET FAN-OUT INVARIANT: registered active-high reset with max_fanout=50.
 // See cic_decimator_4x_enhanced.v for full reasoning. reset_n here is driven
 // by the parent DDC's reset_n_400m (already synchronized to clk_400m), so
 // sync reset on the LFSR is safe. INIT=1'b1 holds LFSR in reset on power-up.
 // ============================================================================
 (* max_fanout = 50 *) reg reset_h = 1'b1;
 always @(posedge clk) reset_h <= ~reset_n;
 always @(posedge clk) begin
    if (reset_h) begin
        lfsr_reg <= {DITHER_WIDTH{1'b1}};  // Non-zero initial state
        cycle_counter <= 0;
        lock_detected <= 0;
@@ -32,15 +32,13 @@
 //     w[n] = 0.54 - 0.46 * cos(2*pi*n/15), n=0..15
 // ============================================================================
 `include "radar_params.vh"
 module doppler_processor_optimized #(
-    parameter DOPPLER_FFT_SIZE   = `RP_DOPPLER_FFT_SIZE,    // 16
+    parameter DOPPLER_FFT_SIZE   = 16,     // FFT size per sub-frame (was 32)
-    parameter RANGE_BINS         = `RP_NUM_RANGE_BINS,      // 512
+    parameter RANGE_BINS         = 64,
-    parameter CHIRPS_PER_FRAME   = `RP_CHIRPS_PER_FRAME,    // 32
+    parameter CHIRPS_PER_FRAME   = 32,     // Total chirps in frame (16+16)
-    parameter CHIRPS_PER_SUBFRAME = `RP_CHIRPS_PER_SUBFRAME, // 16
+    parameter CHIRPS_PER_SUBFRAME = 16,    // Chirps per sub-frame
    parameter WINDOW_TYPE        = 0,      // 0=Hamming, 1=Rectangular
-    parameter DATA_WIDTH         = `RP_DATA_WIDTH           // 16
+    parameter DATA_WIDTH         = 16
 )(
    input wire clk,
    input wire reset_n,
@@ -50,7 +48,7 @@ module doppler_processor_optimized #(
    output reg [31:0] doppler_output,
    output reg doppler_valid,
    output reg [4:0] doppler_bin,      // {sub_frame, bin[3:0]}
-    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin,  // 9-bit
+    output reg [5:0] range_bin,
    output reg sub_frame,              // 0=long PRI, 1=short PRI
    output wire processing_active,
    output wire frame_complete,
@@ -59,16 +57,16 @@ module doppler_processor_optimized #(
 `ifdef FORMAL
    ,
    output wire [2:0]  fv_state,
-    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_write_addr,
+    output wire [10:0] fv_mem_write_addr,
-    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_read_addr,
+    output wire [10:0] fv_mem_read_addr,
-    output wire [`RP_RANGE_BIN_BITS-1:0]     fv_write_range_bin,
+    output wire [5:0]  fv_write_range_bin,
    output wire [4:0]  fv_write_chirp_index,
-    output wire [`RP_RANGE_BIN_BITS-1:0]     fv_read_range_bin,
+    output wire [5:0]  fv_read_range_bin,
    output wire [4:0]  fv_read_doppler_index,
    output wire [9:0]  fv_processing_timeout,
    output wire        fv_frame_buffer_full,
    output wire        fv_mem_we,
-    output wire [`RP_DOPPLER_MEM_ADDR_W-1:0] fv_mem_waddr_r
+    output wire [10:0] fv_mem_waddr_r
 `endif
 );
@@ -117,9 +115,9 @@ localparam MEM_DEPTH = RANGE_BINS * CHIRPS_PER_FRAME;
 // ==============================================
 // Control Registers
 // ==============================================
-reg [`RP_RANGE_BIN_BITS-1:0] write_range_bin;
+reg [5:0] write_range_bin;
 reg [4:0] write_chirp_index;
-reg [`RP_RANGE_BIN_BITS-1:0] read_range_bin;
+reg [5:0] read_range_bin;
 reg [4:0] read_doppler_index;
 reg frame_buffer_full;
 reg [9:0] chirps_received;
@@ -149,8 +147,8 @@ wire fft_output_last;
 // ==============================================
 // Addressing
 // ==============================================
-wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_write_addr;
+wire [10:0] mem_write_addr;
-wire [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_read_addr;
+wire [10:0] mem_read_addr;
 assign mem_write_addr = (write_chirp_index * RANGE_BINS) + write_range_bin;
 assign mem_read_addr = (read_doppler_index * RANGE_BINS) + read_range_bin;
@@ -182,7 +180,7 @@ reg [9:0] processing_timeout;
 // Memory write enable and data signals
 reg mem_we;
-reg [`RP_DOPPLER_MEM_ADDR_W-1:0] mem_waddr_r;
+reg [10:0] mem_waddr_r;
 reg [DATA_WIDTH-1:0] mem_wdata_i, mem_wdata_q;
 // Memory read data
@@ -533,11 +531,6 @@ xfft_16 fft_inst (
 // Status Outputs
 // ==============================================
 assign processing_active = (state != S_IDLE);
 // NOTE: frame_complete is a LEVEL, not a pulse. It is high whenever the
 // doppler processor is idle with no buffered frame. radar_receiver_final.v
 // converts this to a single-cycle rising-edge pulse before routing to
 // downstream consumers (USB FT2232H, AGC, CFAR). Do NOT connect this
 // level output directly to modules that expect a pulse.
 assign frame_complete = (state == S_IDLE && frame_buffer_full == 0);
 endmodule
@@ -28,16 +28,13 @@
 * Clock domain: single clock (clk), active-low async reset (reset_n).
 */
 // Include single source of truth for default parameters
 `include "radar_params.vh"
 module fft_engine #(
-    parameter N            = `RP_FFT_SIZE,       // 2048
+    parameter N            = 1024,
-    parameter LOG2N        = `RP_LOG2_FFT_SIZE,  // 11
+    parameter LOG2N        = 10,
    parameter DATA_W       = 16,
    parameter INTERNAL_W   = 32,
    parameter TWIDDLE_W    = 16,
-    parameter TWIDDLE_FILE = "fft_twiddle_2048.mem"
+    parameter TWIDDLE_FILE = "fft_twiddle_1024.mem"
 )(
    input wire clk,
    input wire reset_n,
@@ -1,515 +0,0 @@
 // Quarter-wave cosine ROM for 2048-point FFT
 // 512 entries, 16-bit signed Q15 ($readmemh format)
 // cos(2*pi*k/2048) for k = 0..511
 7FFF
 7FFF
 7FFE
 7FFE
 7FFD
 7FFB
 7FF9
 7FF7
 7FF5
 7FF3
 7FF0
 7FEC
 7FE9
 7FE5
 7FE1
 7FDC
 7FD8
 7FD2
 7FCD
 7FC7
 7FC1
 7FBB
 7FB4
 7FAD
 7FA6
 7F9F
 7F97
 7F8F
 7F86
 7F7D
 7F74
 7F6B
 7F61
 7F57
 7F4D
 7F42
 7F37
 7F2C
 7F21
 7F15
 7F09
 7EFC
 7EEF
 7EE2
 7ED5
 7EC7
 7EB9
 7EAB
 7E9C
 7E8D
 7E7E
 7E6F
 7E5F
 7E4F
 7E3E
 7E2E
 7E1D
 7E0B
 7DFA
 7DE8
 7DD5
 7DC3
 7DB0
 7D9D
 7D89
 7D76
 7D62
 7D4D
 7D39
 7D24
 7D0E
 7CF9
 7CE3
 7CCD
 7CB6
 7C9F
 7C88
 7C71
 7C59
 7C41
 7C29
 7C10
 7BF8
 7BDE
 7BC5
 7BAB
 7B91
 7B77
 7B5C
 7B41
 7B26
 7B0A
 7AEE
 7AD2
 7AB6
 7A99
 7A7C
 7A5F
 7A41
 7A23
 7A05
 79E6
 79C8
 79A9
 7989
 796A
 794A
 7929
 7909
 78E8
 78C7
 78A5
 7884
 7862
 783F
 781D
 77FA
 77D7
 77B3
 778F
 776B
 7747
 7722
 76FE
 76D8
 76B3
 768D
 7667
 7641
 761A
 75F3
 75CC
 75A5
 757D
 7555
 752D
 7504
 74DB
 74B2
 7488
 745F
 7435
 740A
 73E0
 73B5
 738A
 735E
 7333
 7307
 72DB
 72AE
 7281
 7254
 7227
 71F9
 71CB
 719D
 716F
 7140
 7111
 70E2
 70B2
 7083
 7053
 7022
 6FF2
 6FC1
 6F90
 6F5E
 6F2C
 6EFB
 6EC8
 6E96
 6E63
 6E30
 6DFD
 6DC9
 6D95
 6D61
 6D2D
 6CF8
 6CC3
 6C8E
 6C59
 6C23
 6BED
 6BB7
 6B81
 6B4A
 6B13
 6ADC
 6AA4
 6A6D
 6A35
 69FD
 69C4
 698B
 6952
 6919
 68E0
 68A6
 686C
 6832
 67F7
 67BC
 6781
 6746
 670A
 66CF
 6693
 6656
 661A
 65DD
 65A0
 6563
 6525
 64E8
 64AA
 646C
 642D
 63EE
 63AF
 6370
 6331
 62F1
 62B1
 6271
 6231
 61F0
 61AF
 616E
 612D
 60EB
 60AA
 6068
 6025
 5FE3
 5FA0
 5F5D
 5F1A
 5ED7
 5E93
 5E4F
 5E0B
 5DC7
 5D82
 5D3E
 5CF9
 5CB3
 5C6E
 5C28
 5BE2
 5B9C
 5B56
 5B0F
 5AC9
 5A82
 5A3B
 59F3
 59AC
 5964
 591C
 58D3
 588B
 5842
 57F9
 57B0
 5767
 571D
 56D3
 568A
 563F
 55F5
 55AA
 5560
 5515
 54C9
 547E
 5432
 53E7
 539B
 534E
 5302
 52B5
 5268
 521B
 51CE
 5181
 5133
 50E5
 5097
 5049
 4FFB
 4FAC
 4F5D
 4F0E
 4EBF
 4E70
 4E20
 4DD1
 4D81
 4D31
 4CE0
 4C90
 4C3F
 4BEE
 4B9D
 4B4C
 4AFB
 4AA9
 4A58
 4A06
 49B4
 4961
 490F
 48BC
 4869
 4816
 47C3
 4770
 471C
 46C9
 4675
 4621
 45CD
 4578
 4524
 44CF
 447A
 4425
 43D0
 437B
 4325
 42D0
 427A
 4224
 41CE
 4177
 4121
 40CA
 4073
 401D
 3FC5
 3F6E
 3F17
 3EBF
 3E68
 3E10
 3DB8
 3D60
 3D07
 3CAF
 3C56
 3BFE
 3BA5
 3B4C
 3AF2
 3A99
 3A40
 39E6
 398C
 3933
 38D9
 387E
 3824
 37CA
 376F
 3715
 36BA
 365F
 3604
 35A8
 354D
 34F2
 3496
 343A
 33DF
 3383
 3326
 32CA
 326E
 3211
 31B5
 3158
 30FB
 309E
 3041
 2FE4
 2F87
 2F2A
 2ECC
 2E6E
 2E11
 2DB3
 2D55
 2CF7
 2C99
 2C3A
 2BDC
 2B7D
 2B1F
 2AC0
 2A61
 2A02
 29A3
 2944
 28E5
 2886
 2826
 27C7
 2767
 2708
 26A8
 2648
 25E8
 2588
 2528
 24C8
 2467
 2407
 23A6
 2346
 22E5
 2284
 2223
 21C2
 2161
 2100
 209F
 203E
 1FDD
 1F7B
 1F1A
 1EB8
 1E57
 1DF5
 1D93
 1D31
 1CCF
 1C6D
 1C0B
 1BA9
 1B47
 1AE5
 1A82
 1A20
 19BE
 195B
 18F9
 1896
 1833
 17D0
 176E
 170B
 16A8
 1645
 15E2
 157F
 151C
 14B9
 1455
 13F2
 138F
 132B
 12C8
 1264
 1201
 119D
 113A
 10D6
 1072
 100F
 0FAB
 0F47
 0EE3
 0E80
 0E1C
 0DB8
 0D54
 0CF0
 0C8C
 0C28
 0BC4
 0B5F
 0AFB
 0A97
 0A33
 09CF
 096A
 0906
 08A2
 083E
 07D9
 0775
 0711
 06AC
 0648
 05E3
 057F
 051B
 04B6
 0452
 03ED
 0389
 0324
 02C0
 025B
 01F7
 0192
 012E
 00C9
 0065
@@ -1,8 +1,5 @@
 `timescale 1ns / 1ps
 // matched_filter_multi_segment.v
 `include "radar_params.vh"
 module matched_filter_multi_segment (
    input wire clk,           // 100MHz
    input wire reset_n,
@@ -21,13 +18,14 @@ module matched_filter_multi_segment (
    input wire mc_new_elevation,    // Toggle for new elevation (32)
    input wire mc_new_azimuth,      // Toggle for new azimuth (50)
-    // Reference chirp (upstream memory loader selects long/short via use_long_chirp)
+    input wire [15:0] long_chirp_real,
-    input wire [15:0] ref_chirp_real,
+    input wire [15:0] long_chirp_imag,
-    input wire [15:0] ref_chirp_imag,
+    input wire [15:0] short_chirp_real,
    input wire [15:0] short_chirp_imag,
    // Memory system interface
    output reg [1:0] segment_request,
-    output wire [10:0] sample_addr_out,  // Tell memory which sample we need (11-bit for 2048)
+    output wire [9:0] sample_addr_out,  // Tell memory which sample we need
    output reg mem_request,
    input wire mem_ready,
@@ -41,18 +39,18 @@ module matched_filter_multi_segment (
 );
 // ========== FIXED PARAMETERS ==========
-parameter BUFFER_SIZE = `RP_FFT_SIZE;              // 2048
+parameter BUFFER_SIZE = 1024;
 parameter LONG_CHIRP_SAMPLES = 3000;  // Still 3000 samples total
-parameter SHORT_CHIRP_SAMPLES = 50;                // 0.5 us @ 100MHz
+parameter SHORT_CHIRP_SAMPLES = 50;   // 0.5�s @ 100MHz
-parameter OVERLAP_SAMPLES = `RP_OVERLAP_SAMPLES;   // 128
+parameter OVERLAP_SAMPLES = 128;      // Standard for 1024-pt FFT
-parameter SEGMENT_ADVANCE = `RP_SEGMENT_ADVANCE;   // 2048 - 128 = 1920 samples
+parameter SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES;  // 896 samples
 parameter DEBUG = 1;                  // Debug output control
 // Calculate segments needed with overlap
-// For 3000 samples with 128 overlap:
+// For 3072 samples with 128 overlap: 
-// Segments = ceil((3000 - 2048) / 1920) + 1 = ceil(952/1920) + 1 = 2
+// Segments = ceil((3072 - 128) / 896) = ceil(2944/896) = 4
-parameter LONG_SEGMENTS = `RP_LONG_SEGMENTS_3KM;   // 2 segments
+parameter LONG_SEGMENTS = 4;          // Now exactly 4 segments!
-parameter SHORT_SEGMENTS = 1;                      // 50 samples padded to 2048
+parameter SHORT_SEGMENTS = 1;         // 50 samples padded to 1024
 // ========== FIXED INTERNAL SIGNALS ==========
 reg signed [31:0] pc_i, pc_q;
@@ -61,19 +59,19 @@ reg pc_valid;
 // Dual buffer for overlap-save — BRAM inferred for synthesis
 (* ram_style = "block" *) reg signed [15:0] input_buffer_i [0:BUFFER_SIZE-1];
 (* ram_style = "block" *) reg signed [15:0] input_buffer_q [0:BUFFER_SIZE-1];
-reg [11:0] buffer_write_ptr;    // 12-bit for 0..2048
+reg [10:0] buffer_write_ptr;
-reg [11:0] buffer_read_ptr;     // 12-bit for 0..2048
+reg [10:0] buffer_read_ptr;
 reg buffer_has_data;
 reg buffer_processing;
 reg [15:0] chirp_samples_collected;
 // BRAM write port signals
 reg        buf_we;
-reg [10:0] buf_waddr;           // 11-bit for 0..2047
+reg [9:0]  buf_waddr;
 reg signed [15:0] buf_wdata_i, buf_wdata_q;
 // BRAM read port signals
-reg [10:0] buf_raddr;           // 11-bit for 0..2047
+reg [9:0]  buf_raddr;
 reg signed [15:0] buf_rdata_i, buf_rdata_q;
 // State machine
@@ -96,22 +94,15 @@ reg chirp_complete;
 reg saw_chain_output;             // Flag: chain started producing output
 // Overlap cache — captured during ST_PROCESSING, written back in ST_OVERLAP_COPY
 // Uses sync-only write block to allow distributed RAM inference (not FFs).
 // 128 entries = distributed RAM (LUTRAM), NOT BRAM (too shallow).
 reg signed [15:0] overlap_cache_i [0:OVERLAP_SAMPLES-1];
 reg signed [15:0] overlap_cache_q [0:OVERLAP_SAMPLES-1];
 reg [7:0] overlap_copy_count;
 // Overlap cache write port signals (driven from FSM, used in sync-only block)
 reg        ov_we;
 reg [6:0]  ov_waddr;
 reg signed [15:0] ov_wdata_i, ov_wdata_q;
 // Microcontroller sync detection
 reg mc_new_chirp_prev, mc_new_elevation_prev, mc_new_azimuth_prev;
-wire chirp_start_pulse = mc_new_chirp ^ mc_new_chirp_prev;           // Toggle-to-pulse (any edge)
+wire chirp_start_pulse = mc_new_chirp && !mc_new_chirp_prev;
-wire elevation_change_pulse = mc_new_elevation ^ mc_new_elevation_prev; // Toggle-to-pulse
+wire elevation_change_pulse = mc_new_elevation && !mc_new_elevation_prev;
-wire azimuth_change_pulse = mc_new_azimuth ^ mc_new_azimuth_prev;     // Toggle-to-pulse
+wire azimuth_change_pulse = mc_new_azimuth && !mc_new_azimuth_prev;
 // Processing chain signals
 wire [15:0] fft_pc_i, fft_pc_q;
@@ -124,7 +115,7 @@ reg fft_input_valid;
 reg fft_start;
 // ========== SAMPLE ADDRESS OUTPUT ==========
-assign sample_addr_out = buffer_read_ptr[10:0];
+assign sample_addr_out = buffer_read_ptr;
 // ========== MICROCONTROLLER SYNC ==========
 always @(posedge clk or negedge reset_n) begin
@@ -161,16 +152,6 @@ always @(posedge clk) begin
    end
 end
 // ========== OVERLAP CACHE WRITE PORT (sync only — distributed RAM inference) ==========
 // Removing async reset from memory write path prevents Vivado from
 // synthesizing the 128x16 arrays as FFs + mux trees.
 always @(posedge clk) begin
    if (ov_we) begin
        overlap_cache_i[ov_waddr] <= ov_wdata_i;
        overlap_cache_q[ov_waddr] <= ov_wdata_q;
    end
 end
 // ========== BRAM READ PORT (synchronous, no async reset) ==========
 always @(posedge clk) begin
    buf_rdata_i <= input_buffer_i[buf_raddr];
@@ -202,17 +183,12 @@ always @(posedge clk or negedge reset_n) begin
        buf_wdata_i <= 0;
        buf_wdata_q <= 0;
        buf_raddr <= 0;
        ov_we <= 0;
        ov_waddr <= 0;
        ov_wdata_i <= 0;
        ov_wdata_q <= 0;
        overlap_copy_count <= 0;
    end else begin
        pc_valid <= 0;
        mem_request <= 0;
        fft_input_valid <= 0;
        buf_we <= 0;  // Default: no write
        ov_we <= 0;   // Default: no overlap write
        case (state)
            ST_IDLE: begin
@@ -247,7 +223,7 @@ always @(posedge clk or negedge reset_n) begin
                if (ddc_valid && buffer_write_ptr < BUFFER_SIZE) begin
                    // Store in buffer via BRAM write port
                    buf_we <= 1;
-                    buf_waddr <= buffer_write_ptr[10:0];
+                    buf_waddr <= buffer_write_ptr[9:0];
                    buf_wdata_i <= ddc_i[17:2] + ddc_i[1];
                    buf_wdata_q <= ddc_q[17:2] + ddc_q[1];
@@ -268,7 +244,6 @@ always @(posedge clk or negedge reset_n) begin
                    if (!use_long_chirp) begin
                        if (chirp_samples_collected >= SHORT_CHIRP_SAMPLES - 1) begin
                            state <= ST_ZERO_PAD;
                            chirp_complete <= 1;  // Bug A fix: mark chirp done so ST_OUTPUT exits to IDLE
                            `ifdef SIMULATION
                            $display("[MULTI_SEG_FIXED] Short chirp: collected %d samples, starting zero-pad",
                                     chirp_samples_collected + 1);
@@ -282,8 +257,8 @@ always @(posedge clk or negedge reset_n) begin
                // missing the transition when buffer_write_ptr updates via
                // non-blocking assignment one cycle after the last write.
                //
-                // Overlap-save fix: fill the FULL FFT_SIZE-sample buffer before
+                // Overlap-save fix: fill the FULL 1024-sample buffer before
-                // processing.  For segment 0 this means FFT_SIZE fresh samples.
+                // processing.  For segment 0 this means 1024 fresh samples.
                // For segments 1+, write_ptr starts at OVERLAP_SAMPLES (128)
                // so we collect 896 new samples to fill the buffer.
                if (use_long_chirp) begin
@@ -320,7 +295,7 @@ always @(posedge clk or negedge reset_n) begin
            ST_ZERO_PAD: begin
                // Zero-pad remaining buffer via BRAM write port
                buf_we <= 1;
-                buf_waddr <= buffer_write_ptr[10:0];
+                buf_waddr <= buffer_write_ptr[9:0];
                buf_wdata_i <= 16'd0;
                buf_wdata_q <= 16'd0;
                buffer_write_ptr <= buffer_write_ptr + 1;
@@ -340,7 +315,7 @@ always @(posedge clk or negedge reset_n) begin
            ST_WAIT_REF: begin
                // Wait for memory to provide reference coefficients
-                buf_raddr <= 11'd0;  // Pre-present addr 0 so buf_rdata is ready next cycle
+                buf_raddr <= 10'd0;  // Pre-present addr 0 so buf_rdata is ready next cycle
                if (mem_ready) begin
                    // Start processing — buf_rdata[0] will be valid on FIRST clock of ST_PROCESSING
                    buffer_processing <= 1;
@@ -369,12 +344,10 @@ always @(posedge clk or negedge reset_n) begin
                    // 2. Request corresponding reference sample
                    mem_request <= 1'b1;
-                    // 3. Cache tail samples for overlap-save (via sync-only write port)
+                    // 3. Cache tail samples for overlap-save
                    if (buffer_read_ptr >= SEGMENT_ADVANCE) begin
-                        ov_we <= 1;
+                        overlap_cache_i[buffer_read_ptr - SEGMENT_ADVANCE] <= buf_rdata_i;
-                        ov_waddr <= buffer_read_ptr - SEGMENT_ADVANCE;  // 0..OVERLAP-1
+                        overlap_cache_q[buffer_read_ptr - SEGMENT_ADVANCE] <= buf_rdata_q;
                        ov_wdata_i <= buf_rdata_i;
                        ov_wdata_q <= buf_rdata_q;
                    end
                    // Debug every 100 samples
@@ -388,7 +361,7 @@ always @(posedge clk or negedge reset_n) begin
                    end
                    // Present NEXT read address (for next cycle)
-                    buf_raddr <= buffer_read_ptr[10:0] + 11'd1;
+                    buf_raddr <= buffer_read_ptr[9:0] + 10'd1;
                    buffer_read_ptr <= buffer_read_ptr + 1;
                end else if (buffer_read_ptr >= BUFFER_SIZE) begin
@@ -409,7 +382,7 @@ always @(posedge clk or negedge reset_n) begin
            ST_WAIT_FFT: begin
                // Wait for the processing chain to complete ALL outputs.
-                // The chain streams FFT_SIZE samples (fft_pc_valid=1 for FFT_SIZE clocks),
+                // The chain streams 1024 samples (fft_pc_valid=1 for 1024 clocks),
                // then transitions to ST_DONE (9) -> ST_IDLE (0).
                // We track when output starts (saw_chain_output) and only
                // proceed once the chain returns to idle after outputting.
@@ -481,7 +454,7 @@ always @(posedge clk or negedge reset_n) begin
            ST_OVERLAP_COPY: begin
                // Write one cached overlap sample per cycle to BRAM
                buf_we <= 1;
-                buf_waddr <= {{3{1'b0}}, overlap_copy_count};
+                buf_waddr <= {{2{1'b0}}, overlap_copy_count};
                buf_wdata_i <= overlap_cache_i[overlap_copy_count];
                buf_wdata_q <= overlap_cache_q[overlap_copy_count];
@@ -527,9 +500,11 @@ matched_filter_processing_chain m_f_p_c(
    // Chirp Selection
    .chirp_counter(chirp_counter),
-    // Reference Chirp Memory Interface (single pair — upstream selects long/short)
+    // Reference Chirp Memory Interfaces
-    .ref_chirp_real(ref_chirp_real),
+    .long_chirp_real(long_chirp_real),
-    .ref_chirp_imag(ref_chirp_imag),
+    .long_chirp_imag(long_chirp_imag),
    .short_chirp_real(short_chirp_real),
    .short_chirp_imag(short_chirp_imag),
    // Output
    .range_profile_i(fft_pc_i),
@@ -15,28 +15,26 @@
 *   .clk, .reset_n
 *   .adc_data_i, .adc_data_q, .adc_valid      <- from input buffer
 *   .chirp_counter                              <- 6-bit frame counter
- *   .ref_chirp_real/imag                     <- reference (time-domain)
+ *   .long_chirp_real/imag, .short_chirp_real/imag <- reference (time-domain)
 *   .range_profile_i, .range_profile_q, .range_profile_valid -> output
 *   .chain_state                                -> 4-bit status
 *
 * Clock domain: clk (100 MHz system clock)
 * Data format:  16-bit signed (Q15 fixed-point)
- * FFT size:     2048 points (parameterized via radar_params.vh)
+ * FFT size:     1024 points
 *
 * Pipeline states:
- *   IDLE -> FWD_FFT (collect 2048 samples + bit-reverse copy)
+ *   IDLE -> FWD_FFT (collect 1024 samples + bit-reverse copy)
 *        -> FWD_BUTTERFLY (forward FFT of signal)
 *        -> REF_BITREV (bit-reverse copy reference into work arrays)
 *        -> REF_BUTTERFLY (forward FFT of reference)
 *        -> MULTIPLY (conjugate multiply in freq domain)
 *        -> INV_BITREV (bit-reverse copy product)
 *        -> INV_BUTTERFLY (inverse FFT + 1/N scaling)
- *        -> OUTPUT (stream 2048 samples)
+ *        -> OUTPUT (stream 1024 samples)
 *        -> DONE -> IDLE
 */
 `include "radar_params.vh"
 module matched_filter_processing_chain (
    input wire clk,
    input wire reset_n,
@@ -50,10 +48,10 @@ module matched_filter_processing_chain (
    input wire [5:0] chirp_counter,
    // Reference chirp (time-domain, latency-aligned by upstream buffer)
-    // Upstream chirp_memory_loader_param selects long/short reference
+    input wire [15:0] long_chirp_real,
-    // via use_long_chirp — this single pair carries whichever is active.
+    input wire [15:0] long_chirp_imag,
-    input wire [15:0] ref_chirp_real,
+    input wire [15:0] short_chirp_real,
-    input wire [15:0] ref_chirp_imag,
+    input wire [15:0] short_chirp_imag,
    // Output: range profile (pulse-compressed)
    output wire signed [15:0] range_profile_i,
@@ -68,8 +66,8 @@ module matched_filter_processing_chain (
 // ============================================================================
 // PARAMETERS
 // ============================================================================
-localparam FFT_SIZE   = `RP_FFT_SIZE;    // 2048
+localparam FFT_SIZE   = 1024;
-localparam ADDR_BITS  = `RP_LOG2_FFT_SIZE; // log2(2048) = 11
+localparam ADDR_BITS  = 10;    // log2(1024)
 // State encoding (4-bit, up to 16 states)
 localparam [3:0] ST_IDLE           = 4'd0;
@@ -89,8 +87,8 @@ reg [3:0] state;
 // SIGNAL BUFFERS
 // ============================================================================
 // Input sample counter
-reg [ADDR_BITS:0] fwd_in_count;     // 0..FFT_SIZE
+reg [ADDR_BITS:0] fwd_in_count;     // 0..1024
-reg fwd_frame_done;                  // All FFT_SIZE samples received
+reg fwd_frame_done;                  // All 1024 samples received
 // Signal time-domain buffer
 reg signed [15:0] fwd_buf_i [0:FFT_SIZE-1];
@@ -177,7 +175,7 @@ always @(posedge clk or negedge reset_n) begin
        case (state)
        // ================================================================
-        // IDLE: Wait for valid ADC data, start collecting 2048 samples
+        // IDLE: Wait for valid ADC data, start collecting 1024 samples
        // ================================================================
        ST_IDLE: begin
            fwd_in_count   <= 0;
@@ -191,8 +189,8 @@ always @(posedge clk or negedge reset_n) begin
                // Store first sample (signal + reference)
                fwd_buf_i[0] <= $signed(adc_data_i);
                fwd_buf_q[0] <= $signed(adc_data_q);
-                ref_buf_i[0] <= $signed(ref_chirp_real);
+                ref_buf_i[0] <= $signed(long_chirp_real);
-                ref_buf_q[0] <= $signed(ref_chirp_imag);
+                ref_buf_q[0] <= $signed(long_chirp_imag);
                fwd_in_count <= 1;
                state        <= ST_FWD_FFT;
            end
@@ -200,7 +198,6 @@ always @(posedge clk or negedge reset_n) begin
        // ================================================================
        // FWD_FFT: Collect remaining samples, then bit-reverse copy signal
        // (2048 samples total)
        // ================================================================
        ST_FWD_FFT: begin
            if (!fwd_frame_done) begin
@@ -208,8 +205,8 @@ always @(posedge clk or negedge reset_n) begin
                if (adc_valid && fwd_in_count < FFT_SIZE) begin
                    fwd_buf_i[fwd_in_count] <= $signed(adc_data_i);
                    fwd_buf_q[fwd_in_count] <= $signed(adc_data_q);
-                    ref_buf_i[fwd_in_count] <= $signed(ref_chirp_real);
+                    ref_buf_i[fwd_in_count] <= $signed(long_chirp_real);
-                    ref_buf_q[fwd_in_count] <= $signed(ref_chirp_imag);
+                    ref_buf_q[fwd_in_count] <= $signed(long_chirp_imag);
                    fwd_in_count <= fwd_in_count + 1;
                end
@@ -440,7 +437,7 @@ always @(posedge clk or negedge reset_n) begin
                end
            end
-            // Scale by 1/N (right shift by log2(2048) = 11) and store
+            // Scale by 1/N (right shift by log2(1024) = 10) and store
            for (i = 0; i < FFT_SIZE; i = i + 1) begin : ifft_scale
                reg signed [31:0] scaled_re, scaled_im;
                scaled_re = work_re[i] >>> ADDR_BITS;
@@ -470,7 +467,7 @@ always @(posedge clk or negedge reset_n) begin
        end
        // ================================================================
-        // OUTPUT: Stream out 2048 range profile samples, one per clock
+        // OUTPUT: Stream out 1024 range profile samples, one per clock
        // ================================================================
        ST_OUTPUT: begin
            if (out_count < FFT_SIZE) begin
@@ -534,16 +531,16 @@ end
 // ============================================================================
 // SYNTHESIS IMPLEMENTATION — Radix-2 DIT FFT via fft_engine
 // ============================================================================
-// Uses a single fft_engine instance (2048-pt) reused 3 times:
+// Uses a single fft_engine instance (1024-pt) reused 3 times:
 //   1. Forward FFT of signal
 //   2. Forward FFT of reference
 //   3. Inverse FFT of conjugate product
 // Conjugate multiply done via frequency_matched_filter (4-stage pipeline).
 //
 // Buffer scheme (BRAM-inferrable):
-//   sig_buf[2048]:  ADC input -> signal FFT output
+//   sig_buf[1024]:  ADC input -> signal FFT output
-//   ref_buf[2048]:  Reference input -> reference FFT output
+//   ref_buf[1024]:  Reference input -> reference FFT output
-//   prod_buf[2048]: Conjugate multiply output -> IFFT output
+//   prod_buf[1024]: Conjugate multiply output -> IFFT output
 //
 // Memory access is INSIDE always @(posedge clk) blocks (no async reset)
 // using local blocking variables. This eliminates NBA race conditions
@@ -555,12 +552,12 @@ end
 //   out_primed   — for output streaming
 // ============================================================================
-localparam FFT_SIZE  = `RP_FFT_SIZE;    // 2048
+localparam FFT_SIZE  = 1024;
-localparam ADDR_BITS = `RP_LOG2_FFT_SIZE; // 11
+localparam ADDR_BITS = 10;
 // State encoding
 localparam [3:0] ST_IDLE     = 4'd0,
-                 ST_COLLECT  = 4'd1,   // Collect FFT_SIZE ADC + ref samples
+                 ST_COLLECT  = 4'd1,   // Collect 1024 ADC + ref samples
                 ST_SIG_FFT  = 4'd2,   // Forward FFT of signal
                 ST_SIG_CAP  = 4'd3,   // Capture signal FFT output
                 ST_REF_FFT  = 4'd4,   // Forward FFT of reference
@@ -568,7 +565,7 @@ localparam [3:0] ST_IDLE     = 4'd0,
                 ST_MULTIPLY = 4'd6,   // Conjugate multiply (pipelined)
                 ST_INV_FFT  = 4'd7,   // Inverse FFT of product
                 ST_INV_CAP  = 4'd8,   // Capture IFFT output
-                 ST_OUTPUT   = 4'd9,   // Stream FFT_SIZE results
+                 ST_OUTPUT   = 4'd9,   // Stream 1024 results
                 ST_DONE     = 4'd10;
 reg [3:0] state;
@@ -591,11 +588,11 @@ reg signed [15:0] prod_rdata_i, prod_rdata_q;
 // ============================================================================
 // COUNTERS
 // ============================================================================
-reg [ADDR_BITS:0] collect_count;   // 0..FFT_SIZE for sample collection
+reg [ADDR_BITS:0] collect_count;   // 0..1024 for sample collection
-reg [ADDR_BITS:0] feed_count;      // 0..FFT_SIZE for feeding FFT engine
+reg [ADDR_BITS:0] feed_count;      // 0..1024 for feeding FFT engine
-reg [ADDR_BITS:0] cap_count;       // 0..FFT_SIZE for capturing FFT output
+reg [ADDR_BITS:0] cap_count;       // 0..1024 for capturing FFT output
-reg [ADDR_BITS:0] mult_count;      // 0..FFT_SIZE for multiply feeding
+reg [ADDR_BITS:0] mult_count;      // 0..1024 for multiply feeding
-reg [ADDR_BITS:0] out_count;       // 0..FFT_SIZE for output streaming
+reg [ADDR_BITS:0] out_count;       // 0..1024 for output streaming
 // BRAM read latency pipeline flags
 reg feed_primed;   // 1 = BRAM rdata valid for feed operations
@@ -620,7 +617,7 @@ fft_engine #(
    .DATA_W(16),
    .INTERNAL_W(32),
    .TWIDDLE_W(16),
-    .TWIDDLE_FILE("fft_twiddle_2048.mem")
+    .TWIDDLE_FILE("fft_twiddle_1024.mem")
 ) fft_inst (
    .clk(clk),
    .reset_n(reset_n),
@@ -778,16 +775,16 @@ always @(posedge clk) begin : ref_bram_port
        if (adc_valid) begin
            we      = 1'b1;
            addr    = 0;
-            wdata_i = $signed(ref_chirp_real);
+            wdata_i = $signed(long_chirp_real);
-            wdata_q = $signed(ref_chirp_imag);
+            wdata_q = $signed(long_chirp_imag);
        end
    end
    ST_COLLECT: begin
        if (adc_valid && collect_count < FFT_SIZE) begin
            we      = 1'b1;
            addr    = collect_count[ADDR_BITS-1:0];
-            wdata_i = $signed(ref_chirp_real);
+            wdata_i = $signed(long_chirp_real);
-            wdata_q = $signed(ref_chirp_imag);
+            wdata_q = $signed(long_chirp_imag);
        end
    end
    ST_REF_FFT: begin
@@ -971,7 +968,7 @@ always @(posedge clk or negedge reset_n) begin
        end
        // ================================================================
-        // COLLECT: Gather 2048 ADC + reference samples
+        // COLLECT: Gather 1024 ADC + reference samples
        // Writes happen in sig/ref BRAM ports (they see state==ST_COLLECT)
        // ================================================================
        ST_COLLECT: begin
@@ -980,7 +977,7 @@ always @(posedge clk or negedge reset_n) begin
            end
            if (collect_count == FFT_SIZE) begin
-                // All 2048 samples collected — start signal FFT
+                // All 1024 samples collected — start signal FFT
                state       <= ST_SIG_FFT;
                fft_start   <= 1'b1;
                fft_inverse <= 1'b0;  // Forward FFT
@@ -1094,7 +1091,7 @@ always @(posedge clk or negedge reset_n) begin
        // ================================================================
        // MULTIPLY: Stream sig FFT and ref FFT through freq_matched_filter
        // Both sig_buf and ref_buf are read simultaneously (separate BRAM
-        // ports). Pipeline latency = 4 clocks. Feed 2048 pairs, then flush.
+        // ports). Pipeline latency = 4 clocks. Feed 1024 pairs, then flush.
        // ================================================================
        ST_MULTIPLY: begin
            if (mult_count < FFT_SIZE) begin
@@ -1183,7 +1180,7 @@ always @(posedge clk or negedge reset_n) begin
        end
        // ================================================================
-        // OUTPUT: Stream 2048 range profile samples
+        // OUTPUT: Stream 1024 range profile samples
        // BRAM read latency: present address, data valid next cycle.
        // ================================================================
        ST_OUTPUT: begin
@@ -19,33 +19,25 @@
 *     mti_out_i[r] = current_i[r] - previous_i[r]
 *     mti_out_q[r] = current_q[r] - previous_q[r]
 *
- * The previous chirp's 512 range bins are stored in BRAM (inferred via
+ * The previous chirp's 64 range bins are stored in a small BRAM.
 * sync-only read/write always blocks — NO async reset on memory arrays).
 * On the very first chirp after reset (or enable), there is no previous
 * data — output is zero (muted) for that first chirp.
 *
- * When mti_enable=0, the module is a transparent pass-through.
+ * When mti_enable=0, the module is a transparent pass-through with zero
 * latency penalty (data goes straight through combinationally registered).
 *
- * BRAM inference note:
+ * Resources:
- *   prev_i/prev_q arrays use dedicated sync-only always blocks for read
+ *   - 2 BRAM18 (64 x 16-bit I + 64 x 16-bit Q) or distributed RAM
- *   and write. This ensures Vivado infers BRAM (RAMB18) instead of fabric
+ *   - ~30 LUTs (subtract + mux)
- *   FFs + mux trees. The registered read adds 1 cycle of latency, which
+ *   - ~40 FFs (pipeline + control)
 *   is compensated by a pipeline stage on the input data path.
 *
 * Resources (target):
 *   - 2 BRAM18 (512 x 16-bit I + 512 x 16-bit Q)
 *   - ~30 LUTs (subtract + mux + saturation)
 *   - ~80 FFs (pipeline + control)
 *   - 0 DSP48
 *
 * Clock domain: clk (100 MHz)
 */
 `include "radar_params.vh"
 module mti_canceller #(
-    parameter NUM_RANGE_BINS = `RP_NUM_RANGE_BINS,    // 512
+    parameter NUM_RANGE_BINS = 64,
-    parameter DATA_WIDTH     = `RP_DATA_WIDTH         // 16
+    parameter DATA_WIDTH     = 16
 ) (
    input wire clk,
    input wire reset_n,
@@ -54,13 +46,13 @@ module mti_canceller #(
    input wire signed [DATA_WIDTH-1:0] range_i_in,
    input wire signed [DATA_WIDTH-1:0] range_q_in,
    input wire                         range_valid_in,
-    input wire [`RP_RANGE_BIN_BITS-1:0] range_bin_in,   // 9-bit
+    input wire [5:0]                   range_bin_in,
    // ========== OUTPUT (to Doppler processor) ==========
    output reg signed [DATA_WIDTH-1:0] range_i_out,
    output reg signed [DATA_WIDTH-1:0] range_q_out,
    output reg                         range_valid_out,
-    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_out,   // 9-bit
+    output reg [5:0]                   range_bin_out,
    // ========== CONFIGURATION ==========
    input wire mti_enable,   // 1=MTI active, 0=pass-through
@@ -70,79 +62,30 @@ module mti_canceller #(
 );
 // ============================================================================
-// PREVIOUS CHIRP BUFFER (512 x 16-bit I, 512 x 16-bit Q)
+// PREVIOUS CHIRP BUFFER (64 x 16-bit I, 64 x 16-bit Q)
 // ============================================================================
-// BRAM-inferred on XC7A50T/200T (512 entries, sync-only read/write).
+// Small enough for distributed RAM on XC7A200T (64 entries).
-// Using separate I/Q arrays for clean dual-port inference.
+// Using separate I/Q arrays for clean read/write.
-(* ram_style = "block" *) reg signed [DATA_WIDTH-1:0] prev_i [0:NUM_RANGE_BINS-1];
+reg signed [DATA_WIDTH-1:0] prev_i [0:NUM_RANGE_BINS-1];
-(* ram_style = "block" *) reg signed [DATA_WIDTH-1:0] prev_q [0:NUM_RANGE_BINS-1];
+reg signed [DATA_WIDTH-1:0] prev_q [0:NUM_RANGE_BINS-1];
 // ============================================================================
 // INPUT PIPELINE STAGE (1 cycle delay to match BRAM read latency)
 // ============================================================================
 // Declarations must precede the BRAM write block that references them.
 reg signed [DATA_WIDTH-1:0] range_i_d1, range_q_d1;
 reg                         range_valid_d1;
 reg [`RP_RANGE_BIN_BITS-1:0] range_bin_d1;
 reg                         mti_enable_d1;
 always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        range_i_d1     <= {DATA_WIDTH{1'b0}};
        range_q_d1     <= {DATA_WIDTH{1'b0}};
        range_valid_d1 <= 1'b0;
        range_bin_d1   <= {`RP_RANGE_BIN_BITS{1'b0}};
        mti_enable_d1  <= 1'b0;
    end else begin
        range_i_d1     <= range_i_in;
        range_q_d1     <= range_q_in;
        range_valid_d1 <= range_valid_in;
        range_bin_d1   <= range_bin_in;
        mti_enable_d1  <= mti_enable;
    end
 end
 // ============================================================================
 // BRAM WRITE PORT (sync only — NO async reset for BRAM inference)
 // ============================================================================
 // Writes the current chirp sample into prev_i/prev_q for next chirp's
 // subtraction. Uses the delayed (d1) signals so the write happens 1 cycle
 // after the read address is presented, avoiding RAW hazards.
 always @(posedge clk) begin
    if (range_valid_d1) begin
        prev_i[range_bin_d1] <= range_i_d1;
        prev_q[range_bin_d1] <= range_q_d1;
    end
 end
 // ============================================================================
 // BRAM READ PORT (sync only — 1 cycle read latency)
 // ============================================================================
 // Address is always driven by range_bin_in (cycle 0). Read data appears
 // on prev_i_rd / prev_q_rd at cycle 1, aligned with the d1 pipeline stage.
 reg signed [DATA_WIDTH-1:0] prev_i_rd, prev_q_rd;
 always @(posedge clk) begin
    prev_i_rd <= prev_i[range_bin_in];
    prev_q_rd <= prev_q[range_bin_in];
 end
 // Track whether we have valid previous data
 reg has_previous;
 // ============================================================================
-// MTI PROCESSING (operates on d1 pipeline stage + BRAM read data)
+// MTI PROCESSING
 // ============================================================================
 // Read previous chirp data (combinational)
 wire signed [DATA_WIDTH-1:0] prev_i_rd = prev_i[range_bin_in];
 wire signed [DATA_WIDTH-1:0] prev_q_rd = prev_q[range_bin_in];
 // Compute difference with saturation
 // Subtraction can produce DATA_WIDTH+1 bits; saturate back to DATA_WIDTH.
-wire signed [DATA_WIDTH:0] diff_i_full = {range_i_d1[DATA_WIDTH-1], range_i_d1}
+wire signed [DATA_WIDTH:0] diff_i_full = {range_i_in[DATA_WIDTH-1], range_i_in}
                                        - {prev_i_rd[DATA_WIDTH-1], prev_i_rd};
-wire signed [DATA_WIDTH:0] diff_q_full = {range_q_d1[DATA_WIDTH-1], range_q_d1}
+wire signed [DATA_WIDTH:0] diff_q_full = {range_q_in[DATA_WIDTH-1], range_q_in}
                                        - {prev_q_rd[DATA_WIDTH-1], prev_q_rd};
 // Saturate to DATA_WIDTH bits
@@ -162,28 +105,32 @@ assign diff_q_sat = (diff_q_full > $signed({{2{1'b0}}, {(DATA_WIDTH-1){1'b1}}}))
                  : diff_q_full[DATA_WIDTH-1:0];
 // ============================================================================
-// MAIN OUTPUT LOGIC (operates on d1 pipeline stage)
+// MAIN LOGIC
 // ============================================================================
 always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        range_i_out     <= {DATA_WIDTH{1'b0}};
        range_q_out     <= {DATA_WIDTH{1'b0}};
        range_valid_out <= 1'b0;
-        range_bin_out   <= {`RP_RANGE_BIN_BITS{1'b0}};
+        range_bin_out   <= 6'd0;
        has_previous    <= 1'b0;
        mti_first_chirp <= 1'b1;
    end else begin
        // Default: no valid output
        range_valid_out <= 1'b0;
-        if (range_valid_d1) begin
+        if (range_valid_in) begin
-            // Output path — range_bin is from the delayed pipeline
+            // Always store current sample as "previous" for next chirp
-            range_bin_out <= range_bin_d1;
+            prev_i[range_bin_in] <= range_i_in;
            prev_q[range_bin_in] <= range_q_in;
-            if (!mti_enable_d1) begin
+            // Output path
            range_bin_out <= range_bin_in;
            if (!mti_enable) begin
                // Pass-through mode: no MTI processing
-                range_i_out     <= range_i_d1;
+                range_i_out     <= range_i_in;
-                range_q_out     <= range_q_d1;
+                range_q_out     <= range_q_in;
                range_valid_out <= 1'b1;
                // Reset first-chirp state when MTI is disabled
                has_previous    <= 1'b0;
@@ -197,7 +144,7 @@ always @(posedge clk or negedge reset_n) begin
                range_valid_out <= 1'b1;
                // After last range bin of first chirp, mark previous as valid
-                if (range_bin_d1 == NUM_RANGE_BINS - 1) begin
+                if (range_bin_in == NUM_RANGE_BINS - 1) begin
                    has_previous    <= 1'b1;
                    mti_first_chirp <= 1'b0;
                end
@@ -59,6 +59,25 @@ reg [1:0] quadrant_reg2;                 // Pass-through for Stage 5 MUX
 // Valid pipeline: tracks 6-stage latency
 reg [5:0] valid_pipe;
 // ============================================================================
 // RESET FAN-OUT INVARIANT (Build N+1 fix for WNS=-0.626ns at 400 MHz):
 // ============================================================================
 // reset_h is an ACTIVE-HIGH, REGISTERED copy of ~reset_n with (* max_fanout=50 *).
 // Vivado replicates this register (14+ copies) so each copy drives ≈50 loads
 // regionally, avoiding the single-LUT1 / 702-load net that caused timing
 // failure in Build N. It feeds:
 //   - DSP48E1 RSTP/RSTC on the phase-accumulator DSP (below)
 //   - All pipeline-stage fabric FDREs (synchronous reset)
 // Invariants (see cic_decimator_4x_enhanced.v for full reasoning):
 //   I1 correctness:      reset_h == ~reset_n one cycle later
 //   I2 glitch-free:      registered output
 //   I3 power-up safe:    INIT=1'b1 holds all downstream in reset until first
 //                        valid clock edge; reset_n is low on power-up anyway
 //   I4 de-assert lat.:   +1 cycle vs. direct async; negligible at 400 MHz
 // ============================================================================
 (* max_fanout = 50 *) reg reset_h = 1'b1;
 always @(posedge clk_400m) reset_h <= ~reset_n;
 // Use only the top 8 bits for LUT addressing (256-entry LUT equivalent)
 wire [7:0] lut_address = phase_with_offset[31:24];
@@ -135,8 +154,8 @@ wire [15:0] cos_abs_w = sin_lut[63 - lut_index_pipe_cos];
 // Stage 2: phase_with_offset adds phase offset
 reg [31:0] phase_accumulator;
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
        phase_accumulator <= 32'h00000000;
        phase_accum_reg   <= 32'h00000000;
        phase_with_offset <= 32'h00000000;
@@ -190,8 +209,8 @@ DSP48E1 #(
    .RSTA(1'b0),
    .RSTB(1'b0),
    .RSTM(1'b0),
-    .RSTP(!reset_n),             // Reset P register (phase accumulator) on !reset_n
+    .RSTP(reset_h),              // Reset P register (phase accumulator) — registered, max_fanout=50
-    .RSTC(!reset_n),             // Reset C register (tuning word) on !reset_n
+    .RSTC(reset_h),              // Reset C register (tuning word)       — registered, max_fanout=50
    .RSTALLCARRYIN(1'b0),
    .RSTALUMODE(1'b0),
    .RSTCTRL(1'b0),
@@ -245,8 +264,8 @@ DSP48E1 #(
 // Stage 1: Capture DSP48E1 P output into fabric register
 // Stage 2: Add phase offset to captured value
 // Split into two registered stages to break DSP48E1.P→CARRY4 critical path
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
        phase_accum_reg   <= 32'h00000000;
        phase_with_offset <= 32'h00000000;
    end else if (phase_valid) begin
@@ -264,8 +283,8 @@ end
 //           Only 2 registers driven (lut_index_pipe + quadrant_pipe)
 //           Minimal fanout → short routes → easy timing
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
        lut_index_pipe_sin <= 6'b000000;
        lut_index_pipe_cos <= 6'b000000;
        quadrant_pipe      <= 2'b00;
@@ -281,8 +300,8 @@ end
 //           Registered address → combinational LUT6 read → register
 //           Only 1 logic level (LUT6), trivial timing
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
        sin_abs_reg <= 16'h0000;
        cos_abs_reg <= 16'h7FFF;
        quadrant_reg <= 2'b00;
@@ -298,8 +317,8 @@ end
 //          CARRY4 x4 chain has registered inputs — easily fits in 2.5ns
 //          Also pass through abs values and quadrant for Stage 5
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
        sin_neg_reg <= 16'h0000;
        cos_neg_reg <= -16'h7FFF;
        sin_abs_reg2 <= 16'h0000;
@@ -318,8 +337,8 @@ end
 // Stage 5: Quadrant sign application → final sin/cos output
 //          Uses pre-computed negated values from Stage 4 — pure MUX, no arithmetic
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
        sin_out <= 16'h0000;
        cos_out <= 16'h7FFF;
    end else if (valid_pipe[4]) begin
@@ -347,8 +366,8 @@ end
 // ============================================================================
 // Valid pipeline and dds_ready (6-stage latency)
 // ============================================================================
-always @(posedge clk_400m or negedge reset_n) begin
+always @(posedge clk_400m) begin
-    if (!reset_n) begin
+    if (reset_h) begin
        valid_pipe <= 6'b000000;
        dds_ready <= 1'b0;
    end else begin
@@ -1,7 +1,5 @@
 `timescale 1ns / 1ps
 `include "radar_params.vh"
 /**
 * radar_mode_controller.v
 *
@@ -20,18 +18,12 @@
 *   - 32 chirps per elevation
 *   - 31 elevations per azimuth
 *   - 50 azimuths per full scan
 *   - Each chirp: Long chirp → Listen → Guard → Short chirp → Listen
 *
- * Chirp sequence depends on range_mode (host_range_mode, opcode 0x20):
+ * Modes of operation:
 *   range_mode 2'b00 (3 km):  All short chirps only. Long chirp blind zone
 *     (4500 m) exceeds 3 km max range, so long chirps are useless.
 *   range_mode 2'b01 (long-range): Dual chirp — Long chirp → Listen → Guard
 *     → Short chirp → Listen. First half of chirps_per_elev are long, second
 *     half are short (blind-zone fill).
 *
 * Modes of operation (host_radar_mode, opcode 0x01):
 *   mode[1:0]:
 *     2'b00 = STM32-driven (pass through stm32 toggle signals)
- *     2'b01 = Free-running auto-scan (internal timing, short chirps only)
+ *     2'b01 = Free-running auto-scan (internal timing)
 *     2'b10 = Single-chirp (fire one chirp per trigger, for debug)
 *     2'b11 = Reserved
 *
@@ -39,7 +31,7 @@
 */
 module radar_mode_controller #(
-    parameter CHIRPS_PER_ELEVATION  = `RP_DEF_CHIRPS_PER_ELEV,
+    parameter CHIRPS_PER_ELEVATION = 32,
    parameter ELEVATIONS_PER_AZIMUTH = 31,
    parameter AZIMUTHS_PER_SCAN = 50,
@@ -49,24 +41,18 @@ module radar_mode_controller #(
    // Guard: 175.4us = 17540 cycles
    // Short chirp: 0.5us = 50 cycles
    // Short listen: 174.5us = 17450 cycles
-    parameter LONG_CHIRP_CYCLES   = `RP_DEF_LONG_CHIRP_CYCLES,
+    parameter LONG_CHIRP_CYCLES   = 3000,
-    parameter LONG_LISTEN_CYCLES  = `RP_DEF_LONG_LISTEN_CYCLES,
+    parameter LONG_LISTEN_CYCLES  = 13700,
-    parameter GUARD_CYCLES        = `RP_DEF_GUARD_CYCLES,
+    parameter GUARD_CYCLES        = 17540,
-    parameter SHORT_CHIRP_CYCLES  = `RP_DEF_SHORT_CHIRP_CYCLES,
+    parameter SHORT_CHIRP_CYCLES  = 50,
-    parameter SHORT_LISTEN_CYCLES = `RP_DEF_SHORT_LISTEN_CYCLES
+    parameter SHORT_LISTEN_CYCLES = 17450
 ) (
    input wire clk,
    input wire reset_n,
-    // Mode selection (host_radar_mode, opcode 0x01)
+    // Mode selection
    input wire [1:0] mode,          // 00=STM32, 01=auto, 10=single, 11=rsvd
    // Range mode (host_range_mode, opcode 0x20)
    // Determines chirp type selection in pass-through and auto-scan modes.
    //   2'b00 = 3 km  (all short chirps — long blind zone > max range)
    //   2'b01 = Long-range (dual chirp: first half long, second half short)
    input wire [1:0] range_mode,
    // STM32 pass-through inputs (active in mode 00)
    input wire stm32_new_chirp,
    input wire stm32_new_elevation,
@@ -75,8 +61,10 @@ module radar_mode_controller #(
    // Single-chirp trigger (active in mode 10)
    input wire trigger,
-    // Runtime-configurable timing inputs from host USB commands.
+    // Gap 2: Runtime-configurable timing inputs from host USB commands.
    // When connected, these override the compile-time parameters.
    // When left at default (tied to parameter values at instantiation),
    // behavior is identical to pre-Gap-2.
    input wire [15:0] cfg_long_chirp_cycles,
    input wire [15:0] cfg_long_listen_cycles,
    input wire [15:0] cfg_guard_cycles,
@@ -168,7 +156,7 @@ always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        scan_state      <= S_IDLE;
        timer           <= 18'd0;
-        use_long_chirp  <= 1'b0;  // Default short chirp (safe for 3 km mode)
+        use_long_chirp  <= 1'b1;
        mc_new_chirp    <= 1'b0;
        mc_new_elevation <= 1'b0;
        mc_new_azimuth  <= 1'b0;
@@ -184,12 +172,7 @@ always @(posedge clk or negedge reset_n) begin
        // ================================================================
        // MODE 00: STM32-driven pass-through
        // The STM32 firmware controls timing; we just detect toggle edges
-        // and forward them to the receiver chain. Chirp type is determined
+        // and forward them to the receiver chain.
        // by range_mode:
        //   range_mode 00 (3 km):  ALL chirps are short (long blind zone
        //     4500 m exceeds 3072 m max range, so long chirps are useless).
        //   range_mode 01 (long-range): First half of chirps_per_elev are
        //     long, second half are short (blind-zone fill).
        // ================================================================
        2'b00: begin
            // Reset auto-scan state
@@ -199,29 +182,9 @@ always @(posedge clk or negedge reset_n) begin
            // Pass through toggle signals
            if (stm32_chirp_toggle) begin
                mc_new_chirp <= ~mc_new_chirp;  // Toggle output
                use_long_chirp <= 1'b1;         // Default to long chirp
-                // Determine chirp type based on range_mode
+                // Track chirp count (Gap 2: use runtime cfg_chirps_per_elev)
                case (range_mode)
                `RP_RANGE_MODE_3KM: begin
                    // 3 km mode: all short chirps
                    use_long_chirp <= 1'b0;
                end
                `RP_RANGE_MODE_LONG: begin
                    // Long-range: first half long, second half short.
                    // chirps_per_elev is typically 32 (16 long + 16 short).
                    // Use cfg_chirps_per_elev[5:1] as the halfway point.
                    if (chirp_count < {1'b0, cfg_chirps_per_elev[5:1]})
                        use_long_chirp <= 1'b1;
                    else
                        use_long_chirp <= 1'b0;
                end
                default: begin
                    // Reserved modes: default to short chirp (safe)
                    use_long_chirp <= 1'b0;
                end
                endcase
                // Track chirp count
                if (chirp_count < cfg_chirps_per_elev - 1)
                    chirp_count <= chirp_count + 1;
                else
@@ -254,33 +217,21 @@ always @(posedge clk or negedge reset_n) begin
        // ================================================================
        // MODE 01: Free-running auto-scan
        // Internally generates chirp timing matching the transmitter.
        // For 3 km mode (range_mode 00): short chirps only. The long chirp
        // blind zone (4500 m) exceeds the 3072 m max range, making long
        // chirps useless. State machine skips S_LONG_CHIRP/LISTEN/GUARD.
        // For long-range mode (range_mode 01): full dual-chirp sequence.
        // NOTE: Auto-scan is primarily for bench testing without STM32.
        // ================================================================
        2'b01: begin
            case (scan_state)
            S_IDLE: begin
                // Start first chirp immediately
                scan_state     <= S_LONG_CHIRP;
                timer          <= 18'd0;
                use_long_chirp <= 1'b1;
                mc_new_chirp   <= ~mc_new_chirp;  // Toggle to start chirp
                chirp_count    <= 6'd0;
                elevation_count <= 6'd0;
                azimuth_count  <= 6'd0;
                mc_new_chirp    <= ~mc_new_chirp;  // Toggle to start chirp
                // For 3 km mode, skip directly to short chirp
                if (range_mode == `RP_RANGE_MODE_3KM) begin
                    scan_state     <= S_SHORT_CHIRP;
                    use_long_chirp <= 1'b0;
                end else begin
                    scan_state     <= S_LONG_CHIRP;
                    use_long_chirp <= 1'b1;
                end
                `ifdef SIMULATION
-                $display("[MODE_CTRL] Auto-scan starting, range_mode=%0d", range_mode);
+                $display("[MODE_CTRL] Auto-scan starting");
                `endif
            end
@@ -334,19 +285,13 @@ always @(posedge clk or negedge reset_n) begin
            S_ADVANCE: begin
                // Advance chirp/elevation/azimuth counters
                // (Gap 2: use runtime cfg_chirps_per_elev)
                if (chirp_count < cfg_chirps_per_elev - 1) begin
                    // Next chirp in current elevation
                    chirp_count  <= chirp_count + 1;
                    mc_new_chirp <= ~mc_new_chirp;
                    // For 3 km mode: short chirps only, skip long phases
                    if (range_mode == `RP_RANGE_MODE_3KM) begin
                        scan_state     <= S_SHORT_CHIRP;
                        use_long_chirp <= 1'b0;
                    end else begin
                    scan_state   <= S_LONG_CHIRP;
                    use_long_chirp <= 1'b1;
                    end
                end else begin
                    chirp_count <= 6'd0;
@@ -355,14 +300,8 @@ always @(posedge clk or negedge reset_n) begin
                        elevation_count  <= elevation_count + 1;
                        mc_new_chirp     <= ~mc_new_chirp;
                        mc_new_elevation <= ~mc_new_elevation;
                        if (range_mode == `RP_RANGE_MODE_3KM) begin
                            scan_state     <= S_SHORT_CHIRP;
                            use_long_chirp <= 1'b0;
                        end else begin
                        scan_state       <= S_LONG_CHIRP;
                        use_long_chirp   <= 1'b1;
                        end
                    end else begin
                        elevation_count <= 6'd0;
@@ -372,14 +311,8 @@ always @(posedge clk or negedge reset_n) begin
                            mc_new_chirp     <= ~mc_new_chirp;
                            mc_new_elevation <= ~mc_new_elevation;
                            mc_new_azimuth   <= ~mc_new_azimuth;
                            if (range_mode == `RP_RANGE_MODE_3KM) begin
                                scan_state     <= S_SHORT_CHIRP;
                                use_long_chirp <= 1'b0;
                            end else begin
                            scan_state       <= S_LONG_CHIRP;
                            use_long_chirp   <= 1'b1;
                            end
                        end else begin
                            // Full scan complete — restart
                            azimuth_count   <= 6'd0;
@@ -387,14 +320,8 @@ always @(posedge clk or negedge reset_n) begin
                            mc_new_chirp    <= ~mc_new_chirp;
                            mc_new_elevation <= ~mc_new_elevation;
                            mc_new_azimuth  <= ~mc_new_azimuth;
                            if (range_mode == `RP_RANGE_MODE_3KM) begin
                                scan_state     <= S_SHORT_CHIRP;
                                use_long_chirp <= 1'b0;
                            end else begin
                            scan_state      <= S_LONG_CHIRP;
                            use_long_chirp  <= 1'b1;
                            end
                            `ifdef SIMULATION
                            $display("[MODE_CTRL] Full scan complete, restarting");
@@ -410,27 +337,16 @@ always @(posedge clk or negedge reset_n) begin
        // ================================================================
        // MODE 10: Single-chirp (debug mode)
-        // Fire one chirp per trigger pulse, no scanning.
+        // Fire one long chirp per trigger pulse, no scanning.
        // Chirp type depends on range_mode:
        //   3 km:  short chirp only
        //   Long-range: long chirp (for testing long-chirp path)
        // ================================================================
        2'b10: begin
            case (scan_state)
            S_IDLE: begin
                if (trigger_pulse) begin
                    timer        <= 18'd0;
                    mc_new_chirp <= ~mc_new_chirp;
                    if (range_mode == `RP_RANGE_MODE_3KM) begin
                        // 3 km: fire short chirp
                        scan_state     <= S_SHORT_CHIRP;
                        use_long_chirp <= 1'b0;
                    end else begin
                        // Long-range: fire long chirp
                    scan_state     <= S_LONG_CHIRP;
                    timer          <= 18'd0;
                    use_long_chirp <= 1'b1;
-                    end
+                    mc_new_chirp   <= ~mc_new_chirp;
                end
            end
@@ -447,27 +363,7 @@ always @(posedge clk or negedge reset_n) begin
                if (timer < cfg_long_listen_cycles - 1)
                    timer <= timer + 1;
                else begin
-                    // Single long chirp done, return to idle
+                    // Single chirp done, return to idle
                    timer      <= 18'd0;
                    scan_state <= S_IDLE;
                end
            end
            S_SHORT_CHIRP: begin
                use_long_chirp <= 1'b0;
                if (timer < cfg_short_chirp_cycles - 1)
                    timer <= timer + 1;
                else begin
                    timer <= 18'd0;
                    scan_state <= S_SHORT_LISTEN;
                end
            end
            S_SHORT_LISTEN: begin
                if (timer < cfg_short_listen_cycles - 1)
                    timer <= timer + 1;
                else begin
                    // Single short chirp done, return to idle
                    timer      <= 18'd0;
                    scan_state <= S_IDLE;
                end
@@ -1,228 +0,0 @@
 // ============================================================================
 // radar_params.vh — Single Source of Truth for AERIS-10 FPGA Parameters
 // ============================================================================
 //
 // ALL modules in the FPGA processing chain MUST `include this file instead of
 // hardcoding range bins, segment counts, chirp samples, or timing values.
 //
 // This file uses `define macros (not localparam) so it can be included at any
 // scope. Each consuming module should include this file inside its body and
 // optionally alias macros to localparams for readability.
 //
 // BOARD VARIANTS:
 //   SUPPORT_LONG_RANGE = 0  (50T, USB_MODE=1)  — 3 km mode only
 //   SUPPORT_LONG_RANGE = 1  (200T, USB_MODE=0) — 3 km + 20 km modes
 //
 // RADAR MODES (runtime, via host_radar_mode register, opcode 0x01):
 //   2'b00 = STM32 pass-through (production — STM32 controls chirp timing)
 //   2'b01 = Auto-scan 3 km     (FPGA-timed, short chirps only)
 //   2'b10 = Single-chirp debug (one long chirp per trigger)
 //   2'b11 = Reserved / idle
 //
 // RANGE MODES (runtime, via host_range_mode register, opcode 0x20):
 //   2'b00 = 3 km   (default — pass-through treats all chirps as short)
 //   2'b01 = Long-range (pass-through: first half long, second half short)
 //   2'b10 = Reserved
 //   2'b11 = Reserved
 //
 // USAGE:
 //   `include "radar_params.vh"
 //   Then reference `RP_FFT_SIZE, `RP_NUM_RANGE_BINS, etc.
 //
 // PHYSICAL CONSTANTS (derived from hardware):
 //   ADC clock:           400 MSPS
 //   CIC decimation:      4x
 //   Processing rate:     100 MSPS (post-DDC)
 //   Range per sample:    c / (2 * 100e6) = 1.5 m
 //   FFT size:            2048
 //   Decimation factor:   4  (2048 FFT bins -> 512 output range bins)
 //   Range per dec. bin:  1.5 m * 4 = 6.0 m
 //   Max range (3 km):    512 * 6.0 = 3072 m
 //   Carrier frequency:   10.5 GHz
 //   IF frequency:        120 MHz
 //
 // CHIRP BANDWIDTH (Phase 1 target — currently 20 MHz, planned 30 MHz):
 //   Range resolution:    c / (2 * BW)
 //     20 MHz -> 7.5 m
 //     30 MHz -> 5.0 m
 //   NOTE: Range resolution is independent of range-per-bin. Resolution
 //   determines the minimum separation between two targets; range-per-bin
 //   determines the spatial sampling grid.
 // ============================================================================
 `ifndef RADAR_PARAMS_VH
 `define RADAR_PARAMS_VH
 // ============================================================================
 // BOARD VARIANT — set at synthesis time, NOT runtime
 // ============================================================================
 // Default to 50T (conservative). Override in top-level or synthesis script:
 //   +define+SUPPORT_LONG_RANGE
 // or via Vivado: set_property verilog_define {SUPPORT_LONG_RANGE} [current_fileset]
 // Note: SUPPORT_LONG_RANGE is a flag define (ifdef/ifndef), not a value.
 // `ifndef SUPPORT_LONG_RANGE means 50T (no long range).
 // `ifdef SUPPORT_LONG_RANGE means 200T (long range supported).
 // ============================================================================
 // FFT AND PROCESSING CONSTANTS (fixed, both modes)
 // ============================================================================
 `define RP_FFT_SIZE             2048    // Range FFT points per segment
 `define RP_LOG2_FFT_SIZE        11      // log2(2048)
 `define RP_OVERLAP_SAMPLES      128     // Overlap between adjacent segments
 `define RP_SEGMENT_ADVANCE      1920    // FFT_SIZE - OVERLAP = 2048 - 128
 `define RP_DECIMATION_FACTOR    4       // Range bin decimation (2048 -> 512)
 `define RP_NUM_RANGE_BINS       512     // FFT_SIZE / DECIMATION_FACTOR
 `define RP_RANGE_BIN_BITS       9       // ceil(log2(512))
 `define RP_DOPPLER_FFT_SIZE     16      // Per sub-frame Doppler FFT
 `define RP_CHIRPS_PER_FRAME     32      // Total chirps (16 long + 16 short)
 `define RP_CHIRPS_PER_SUBFRAME  16      // Chirps per Doppler sub-frame
 `define RP_NUM_DOPPLER_BINS     32      // 2 sub-frames * 16 = 32
 `define RP_DATA_WIDTH           16      // ADC/processing data width
 // ============================================================================
 // 3 KM MODE PARAMETERS (both 50T and 200T)
 // ============================================================================
 `define RP_LONG_CHIRP_SAMPLES_3KM   3000    // 30 us at 100 MSPS
 `define RP_LONG_SEGMENTS_3KM        2       // ceil((3000-2048)/1920) + 1 = 2
 `define RP_SHORT_CHIRP_SAMPLES      50      // 0.5 us at 100 MSPS (same both modes)
 `define RP_SHORT_SEGMENTS           1       // Single segment for short chirp
 // Derived 3 km limits
 `define RP_MAX_RANGE_3KM            3072    // 512 bins * 6 m = 3072 m
 // ============================================================================
 // 20 KM MODE PARAMETERS (200T only — Phase 2)
 // ============================================================================
 `define RP_LONG_CHIRP_SAMPLES_20KM  13700   // 137 us at 100 MSPS (= listen window)
 `define RP_LONG_SEGMENTS_20KM       8       // 1 + ceil((13700-2048)/1920) = 1 + 7 = 8
 `define RP_OUTPUT_RANGE_BINS_20KM   4096    // 8 segments * 512 dec. bins each
 // Derived 20 km limits
 `define RP_MAX_RANGE_20KM           24576   // 4096 bins * 6 m = 24576 m
 // ============================================================================
 // MAX VALUES (for sizing buffers — compile-time, based on board variant)
 // ============================================================================
 `ifdef SUPPORT_LONG_RANGE
  `define RP_MAX_SEGMENTS           8
  `define RP_MAX_OUTPUT_BINS        4096
  `define RP_MAX_CHIRP_SAMPLES      13700
 `else
  `define RP_MAX_SEGMENTS           2
  `define RP_MAX_OUTPUT_BINS        512
  `define RP_MAX_CHIRP_SAMPLES      3000
 `endif
 // ============================================================================
 // BIT WIDTHS (derived from MAX values)
 // ============================================================================
 // Segment index: ceil(log2(MAX_SEGMENTS))
 //   50T:  log2(2) = 1 bit  (use 2 for safety)
 //   200T: log2(8) = 3 bits
 `ifdef SUPPORT_LONG_RANGE
  `define RP_SEGMENT_IDX_WIDTH      3
  `define RP_RANGE_BIN_WIDTH_MAX    12      // ceil(log2(4096))
  `define RP_DOPPLER_MEM_ADDR_W     17      // ceil(log2(4096*32)) = 17
  `define RP_CFAR_MAG_ADDR_W        17      // ceil(log2(4096*32)) = 17
 `else
  `define RP_SEGMENT_IDX_WIDTH      2
  `define RP_RANGE_BIN_WIDTH_MAX    9       // ceil(log2(512))
  `define RP_DOPPLER_MEM_ADDR_W     14      // ceil(log2(512*32)) = 14
  `define RP_CFAR_MAG_ADDR_W        14      // ceil(log2(512*32)) = 14
 `endif
 // Derived depths (for memory declarations)
 // Usage: reg [15:0] mem [0:`RP_DOPPLER_MEM_DEPTH-1];
 `define RP_DOPPLER_MEM_DEPTH    (`RP_MAX_OUTPUT_BINS * `RP_CHIRPS_PER_FRAME)
 `define RP_CFAR_MAG_DEPTH       (`RP_MAX_OUTPUT_BINS * `RP_NUM_DOPPLER_BINS)
 // ============================================================================
 // CHIRP TIMING DEFAULTS (100 MHz clock cycles)
 // ============================================================================
 // Reset defaults for host-configurable timing registers.
 // Match radar_mode_controller.v parameters and main.cpp STM32 defaults.
 `define RP_DEF_LONG_CHIRP_CYCLES    3000    // 30 us
 `define RP_DEF_LONG_LISTEN_CYCLES   13700   // 137 us
 `define RP_DEF_GUARD_CYCLES         17540   // 175.4 us
 `define RP_DEF_SHORT_CHIRP_CYCLES   50      // 0.5 us
 `define RP_DEF_SHORT_LISTEN_CYCLES  17450   // 174.5 us
 `define RP_DEF_CHIRPS_PER_ELEV      32
 // ============================================================================
 // BLIND ZONE CONSTANTS (informational, for comments and GUI)
 // ============================================================================
 // Long chirp blind zone:  c * 30 us / 2 = 4500 m
 // Short chirp blind zone: c * 0.5 us / 2 = 75 m
 `define RP_LONG_BLIND_ZONE_M        4500
 `define RP_SHORT_BLIND_ZONE_M       75
 // ============================================================================
 // PHYSICAL CONSTANTS (integer-scaled for Verilog — use in comments/assertions)
 // ============================================================================
 // Range per ADC sample:     1.5 m  (stored as 15 in units of 0.1 m)
 // Range per decimated bin:  6.0 m  (stored as 60 in units of 0.1 m)
 // Processing rate:         100 MSPS
 `define RP_RANGE_PER_SAMPLE_DM      15      // 1.5 m in decimeters
 `define RP_RANGE_PER_BIN_DM         60      // 6.0 m in decimeters
 `define RP_PROCESSING_RATE_MHZ      100
 // ============================================================================
 // AGC DEFAULTS
 // ============================================================================
 `define RP_DEF_AGC_TARGET           200
 `define RP_DEF_AGC_ATTACK           1
 `define RP_DEF_AGC_DECAY            1
 `define RP_DEF_AGC_HOLDOFF          4
 // ============================================================================
 // CFAR DEFAULTS
 // ============================================================================
 `define RP_DEF_CFAR_GUARD           2
 `define RP_DEF_CFAR_TRAIN           8
 `define RP_DEF_CFAR_ALPHA           8'h30   // 3.0 in Q4.4
 `define RP_DEF_CFAR_MODE            2'b00   // CA-CFAR
 // ============================================================================
 // DETECTION DEFAULTS
 // ============================================================================
 `define RP_DEF_DETECT_THRESHOLD     10000
 // ============================================================================
 // RADAR MODE ENCODING (host_radar_mode, opcode 0x01)
 // ============================================================================
 `define RP_MODE_STM32_PASSTHROUGH   2'b00
 `define RP_MODE_AUTO_3KM            2'b01
 `define RP_MODE_SINGLE_DEBUG        2'b10
 `define RP_MODE_RESERVED            2'b11
 // ============================================================================
 // RANGE MODE ENCODING (host_range_mode, opcode 0x20)
 // ============================================================================
 `define RP_RANGE_MODE_3KM           2'b00
 `define RP_RANGE_MODE_LONG          2'b01
 `define RP_RANGE_MODE_RSVD2         2'b10
 `define RP_RANGE_MODE_RSVD3         2'b11
 // ============================================================================
 // STREAM CONTROL (host_stream_control, opcode 0x04, 6-bit)
 // ============================================================================
 // Bits [2:0]: Stream enable mask
 //   Bit 0 = range profile stream
 //   Bit 1 = doppler map stream
 //   Bit 2 = cfar/detection stream
 // Bits [5:3]: Stream format control
 //   Bit 3 = mag_only    (0=I/Q pairs, 1=Manhattan magnitude only)
 //   Bit 4 = sparse_det  (0=dense detection flags, 1=sparse detection list)
 //   Bit 5 = reserved (was frame_decimate, not needed with mag-only fitting)
 `define RP_STREAM_CTRL_DEFAULT      6'b001_111  // all streams, mag-only mode
 `endif // RADAR_PARAMS_VH
@@ -1,7 +1,5 @@
 `timescale 1ns / 1ps
 `include "radar_params.vh"
 module radar_receiver_final (
    input wire clk,           // 100MHz    
 	 input wire reset_n,
@@ -13,28 +11,25 @@ module radar_receiver_final (
    input wire adc_dco_n,            // Data Clock Output N (400MHz LVDS)
 	 output wire adc_pwdn,
-    // Chirp counter from transmitter (for frame sync and matched filter)
+    // Chirp counter from transmitter (for matched filter indexing)
    input wire [5:0] chirp_counter,
    // Frame-start pulse from transmitter (CDC-synchronized, 1 clk_100m cycle)
    input wire tx_frame_start,
    output wire [31:0] doppler_output,
    output wire doppler_valid,
    output wire [4:0] doppler_bin,
-    output wire [`RP_RANGE_BIN_BITS-1:0] range_bin,  // 9-bit
+    output wire [5:0] range_bin,
-    // Raw matched-filter output (debug/bring-up)
+    // Matched filter range profile output (for USB)
    output wire signed [15:0] range_profile_i_out,
    output wire signed [15:0] range_profile_q_out,
    output wire range_profile_valid_out,
    // Decimated 512-bin range profile (for USB bulk frames / downstream consumers)
    output wire [15:0] decimated_range_mag_out,
    output wire decimated_range_valid_out,
    // Host command inputs (Gap 4: USB Read Path, CDC-synchronized)
    // CDC-synchronized in radar_system_top.v before reaching here
    input wire [1:0] host_mode,      // Radar mode: 00=STM32, 01=auto-scan, 10=single-chirp
    input wire host_trigger,          // Single-chirp trigger pulse (1 clk cycle)
    input wire [1:0] host_range_mode, // Range mode: 00=3km (short only), 01=long-range (dual chirp)
    // Gap 2: Host-configurable chirp timing (CDC-synchronized in radar_system_top.v)
    input wire [15:0] host_long_chirp_cycles,
@@ -109,9 +104,9 @@ wire [7:0] gc_saturation_count;  // Diagnostic: per-frame clipped sample counter
 wire [7:0] gc_peak_magnitude;    // Diagnostic: per-frame peak magnitude
 wire [3:0] gc_current_gain;      // Diagnostic: effective gain_shift
-// Reference signal for the processing chain (carries long OR short ref
+// Reference signals for the processing chain
-// depending on use_long_chirp — selected by chirp_memory_loader_param)
+wire [15:0] long_chirp_real, long_chirp_imag;
-wire [15:0] ref_chirp_real, ref_chirp_imag;
+wire [15:0] short_chirp_real, short_chirp_imag;
 // ========== DOPPLER PROCESSING SIGNALS ==========
 wire [31:0] range_data_32bit;
@@ -123,36 +118,20 @@ wire [31:0] doppler_spectrum;
 wire doppler_spectrum_valid;
 wire [4:0] doppler_bin_out;
 wire doppler_processing;
-
+wire doppler_frame_done;
 // frame_complete from doppler_processor is a LEVEL signal (high whenever
 // state == S_IDLE && !frame_buffer_full). Downstream consumers (USB FT2232H,
 // AGC, CFAR) expect a single-cycle PULSE. Convert here at the source so all
 // consumers are safe.
 wire doppler_frame_done_level;  // raw level from doppler_processor
 reg  doppler_frame_done_prev;
 wire doppler_frame_done;        // rising-edge pulse (1 clk cycle)
 always @(posedge clk or negedge reset_n) begin
    if (!reset_n)
        doppler_frame_done_prev <= 1'b0;
    else
        doppler_frame_done_prev <= doppler_frame_done_level;
 end
 assign doppler_frame_done = doppler_frame_done_level & ~doppler_frame_done_prev;
 assign doppler_frame_done_out = doppler_frame_done;
 // ========== RANGE BIN DECIMATOR SIGNALS ==========
 wire signed [15:0] decimated_range_i;
 wire signed [15:0] decimated_range_q;
 wire decimated_range_valid;
-wire [`RP_RANGE_BIN_BITS-1:0] decimated_range_bin;  // 9-bit
+wire [5:0] decimated_range_bin;
 // ========== MTI CANCELLER SIGNALS ==========
 wire signed [15:0] mti_range_i;
 wire signed [15:0] mti_range_q;
 wire mti_range_valid;
-wire [`RP_RANGE_BIN_BITS-1:0] mti_range_bin;  // 9-bit
+wire [5:0] mti_range_bin;
 wire mti_first_chirp;
 // ========== RADAR MODE CONTROLLER SIGNALS ==========
@@ -170,7 +149,6 @@ radar_mode_controller rmc (
    .clk(clk),
    .reset_n(reset_n),
    .mode(host_mode),                     // Controlled by host via USB (default: 2'b01 auto-scan)
    .range_mode(host_range_mode),          // Range mode: 00=3km, 01=long-range (drives chirp type)
    .stm32_new_chirp(stm32_new_chirp_rx),
    .stm32_new_elevation(stm32_new_elevation_rx),
    .stm32_new_azimuth(stm32_new_azimuth_rx),
@@ -289,7 +267,7 @@ rx_gain_control gain_ctrl (
 );
 // 3. Dual Chirp Memory Loader
-wire [10:0] sample_addr_from_chain;
+wire [9:0] sample_addr_from_chain;
 chirp_memory_loader_param chirp_mem (
    .clk(clk),
@@ -303,9 +281,20 @@ chirp_memory_loader_param chirp_mem (
    .mem_ready(mem_ready)
 );
 // Sample address generator
 reg [9:0] sample_addr_reg;
 always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        sample_addr_reg <= 0;
    end else if (mem_request) begin
        sample_addr_reg <= sample_addr_reg + 1;
        if (sample_addr_reg == 1023) sample_addr_reg <= 0;
    end
 end
 // sample_addr_wire removed — was unused implicit wire (synthesis warning)
 // 4. CRITICAL: Reference Chirp Latency Buffer
-// This aligns reference data with FFT output (3187 cycle delay)
+// This aligns reference data with FFT output (2159 cycle delay)
 // TODO: verify empirically during hardware bring-up with correlation test
 wire [15:0] delayed_ref_i, delayed_ref_q;
 wire mem_ready_delayed;
@@ -321,10 +310,11 @@ latency_buffer #(
    .valid_out(mem_ready_delayed)
 );
-// Assign delayed reference signals (single pair — chirp_memory_loader_param
+// Assign delayed reference signals
-// selects long/short reference upstream via use_long_chirp)
+assign long_chirp_real = delayed_ref_i;
-assign ref_chirp_real = delayed_ref_i;
+assign long_chirp_imag = delayed_ref_q;
-assign ref_chirp_imag = delayed_ref_q;
+assign short_chirp_real = delayed_ref_i;
 assign short_chirp_imag = delayed_ref_q;
 // 5. Dual Chirp Matched Filter
@@ -336,12 +326,6 @@ wire range_valid;
 assign range_profile_i_out = range_profile_i;
 assign range_profile_q_out = range_profile_q;
 assign range_profile_valid_out = range_valid;
 // Manhattan magnitude: |I| + |Q|, saturated to 16 bits
 wire [15:0] abs_mti_i = mti_range_i[15] ? (~mti_range_i + 16'd1) : mti_range_i;
 wire [15:0] abs_mti_q = mti_range_q[15] ? (~mti_range_q + 16'd1) : mti_range_q;
 wire [16:0] manhattan_sum = {1'b0, abs_mti_i} + {1'b0, abs_mti_q};
 assign decimated_range_mag_out = manhattan_sum[16] ? 16'hFFFF : manhattan_sum[15:0];
 assign decimated_range_valid_out = mti_range_valid;
 matched_filter_multi_segment mf_dual (
    .clk(clk),
@@ -354,8 +338,10 @@ matched_filter_multi_segment mf_dual (
    .mc_new_chirp(mc_new_chirp),
    .mc_new_elevation(mc_new_elevation),
    .mc_new_azimuth(mc_new_azimuth),
-	 .ref_chirp_real(delayed_ref_i),       // From latency buffer (long or short ref)
+	 .long_chirp_real(delayed_ref_i),      // From latency buffer
-    .ref_chirp_imag(delayed_ref_q),
+    .long_chirp_imag(delayed_ref_q),
    .short_chirp_real(delayed_ref_i),     // Same for short chirp
    .short_chirp_imag(delayed_ref_q),
    .segment_request(segment_request),
    .mem_request(mem_request),
 	 .sample_addr_out(sample_addr_from_chain),
@@ -366,11 +352,11 @@ matched_filter_multi_segment mf_dual (
 );
 // ========== CRITICAL: RANGE BIN DECIMATOR ==========
-// Convert 2048 range bins to 512 bins for Doppler
+// Convert 1024 range bins to 64 bins for Doppler
 range_bin_decimator #(
-    .INPUT_BINS(`RP_FFT_SIZE),              // 2048
+    .INPUT_BINS(1024),
-    .OUTPUT_BINS(`RP_NUM_RANGE_BINS),       // 512
+    .OUTPUT_BINS(64),
-    .DECIMATION_FACTOR(`RP_DECIMATION_FACTOR)  // 4
+    .DECIMATION_FACTOR(16)
 ) range_decim (
    .clk(clk),
    .reset_n(reset_n),
@@ -382,7 +368,7 @@ range_bin_decimator #(
    .range_valid_out(decimated_range_valid),
    .range_bin_index(decimated_range_bin),
    .decimation_mode(2'b01),           // Peak detection mode
-    .start_bin(11'd0),
+    .start_bin(10'd0),
    .watchdog_timeout()                // Diagnostic — unconnected (monitored via ILA if needed)
 );
@@ -391,8 +377,8 @@ range_bin_decimator #(
 // H(z) = 1 - z^{-1} → null at DC Doppler, removes stationary clutter.
 // When host_mti_enable=0: transparent pass-through.
 mti_canceller #(
-    .NUM_RANGE_BINS(`RP_NUM_RANGE_BINS),    // 512
+    .NUM_RANGE_BINS(64),
-    .DATA_WIDTH(`RP_DATA_WIDTH)             // 16
+    .DATA_WIDTH(16)
 ) mti_inst (
    .clk(clk),
    .reset_n(reset_n),
@@ -408,32 +394,31 @@ mti_canceller #(
    .mti_first_chirp(mti_first_chirp)
 );
-// ========== FRAME SYNC USING chirp_counter ==========
+// ========== FRAME SYNC FROM TRANSMITTER ==========
-reg [5:0] chirp_counter_prev;
+// [FPGA-001 FIXED] Use the authoritative new_chirp_frame signal from the
 // transmitter (via plfm_chirp_controller_enhanced), CDC-synchronized to
 // clk_100m in radar_system_top.  Previous code tried to derive frame
 // boundaries from chirp_counter == 0, but that counter comes from the
 // transmitter path (plfm_chirp_controller_enhanced) which does NOT wrap
 // at chirps_per_elev — it overflows to N and only wraps at 6-bit rollover
 // (64).  This caused frame pulses at half the expected rate for N=32.
 reg tx_frame_start_prev;
 reg new_frame_pulse;
 always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
-        chirp_counter_prev <= 6'd0;
+        tx_frame_start_prev <= 1'b0;
        new_frame_pulse <= 1'b0;
    end else begin
        // Default: no pulse
        new_frame_pulse <= 1'b0;
-        // Dynamic frame detection using host_chirps_per_elev.
+        // Edge detect: tx_frame_start is a toggle-CDC derived pulse that
-        // Detect frame boundary when chirp_counter changes AND is a
+        // may be 1 clock wide.  Capture rising edge for clean 1-cycle pulse.
-        // multiple of host_chirps_per_elev (0, N, 2N, 3N, ...).
+        if (tx_frame_start && !tx_frame_start_prev) begin
        // Uses a modulo counter that resets at host_chirps_per_elev.
        if (chirp_counter != chirp_counter_prev) begin
            if (chirp_counter == 6'd0 ||
                chirp_counter == host_chirps_per_elev ||
                chirp_counter == {host_chirps_per_elev, 1'b0}) begin
            new_frame_pulse <= 1'b1;
        end
        end
-        // Store previous value
+        tx_frame_start_prev <= tx_frame_start;
        chirp_counter_prev <= chirp_counter;
    end
 end
@@ -446,10 +431,10 @@ assign range_data_valid = mti_range_valid;
 // ========== DOPPLER PROCESSOR ==========
 doppler_processor_optimized #(
-    .DOPPLER_FFT_SIZE(`RP_DOPPLER_FFT_SIZE),        // 16
+    .DOPPLER_FFT_SIZE(16),
-    .RANGE_BINS(`RP_NUM_RANGE_BINS),                // 512
+    .RANGE_BINS(64),
-    .CHIRPS_PER_FRAME(`RP_CHIRPS_PER_FRAME),        // 32
+    .CHIRPS_PER_FRAME(32),
-    .CHIRPS_PER_SUBFRAME(`RP_CHIRPS_PER_SUBFRAME)   // 16
+    .CHIRPS_PER_SUBFRAME(16)
 ) doppler_proc (
    .clk(clk),
    .reset_n(reset_n),
@@ -465,7 +450,7 @@ doppler_processor_optimized #(
    // Status
    .processing_active(doppler_processing),
-    .frame_complete(doppler_frame_done_level),
+    .frame_complete(doppler_frame_done),
    .status()
 );
@@ -499,14 +484,6 @@ always @(posedge clk or negedge reset_n) begin
            `endif
            chirps_in_current_frame <= 0;
        end
        // Monitor chirp counter pattern
        if (chirp_counter != chirp_counter_prev) begin
            `ifdef SIMULATION
            $display("[TOP] chirp_counter: %0d ? %0d", 
                     chirp_counter_prev, chirp_counter);
            `endif
        end
    end
 end
@@ -1,7 +1,5 @@
 `timescale 1ns / 1ps
 `include "radar_params.vh"
 /**
 * radar_system_top.v
 * 
@@ -124,7 +122,7 @@ module radar_system_top (
    output wire [31:0] dbg_doppler_data,
    output wire dbg_doppler_valid,
    output wire [4:0] dbg_doppler_bin,
-    output wire [`RP_RANGE_BIN_BITS-1:0] dbg_range_bin,
+    output wire [5:0] dbg_range_bin,
    // System status
    output wire [3:0] system_status,
@@ -132,7 +130,7 @@ module radar_system_top (
    // FPGA→STM32 GPIO outputs (DIG_5..DIG_7 on 50T board)
    // Used by STM32 outer AGC loop to read saturation state without USB polling.
    output wire gpio_dig5,          // DIG_5 (H11→PD13): AGC saturation flag (1=clipping detected)
-    output wire gpio_dig6,          // DIG_6 (G12→PD14): reserved (tied low)
+    output wire gpio_dig6,          // DIG_6 (G12→PD14): AGC enable flag (mirrors host_agc_enable)
    output wire gpio_dig7           // DIG_7 (H12→PD15): reserved (tied low)
 );
@@ -144,7 +142,7 @@ module radar_system_top (
 parameter USE_LONG_CHIRP = 1'b1;          // Default to long chirp
 parameter DOPPLER_ENABLE = 1'b1;           // Enable Doppler processing
 parameter USB_ENABLE = 1'b1;               // Enable USB data transfer
-parameter USB_MODE = 0;                    // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T)
+parameter USB_MODE = 1;                    // 0=FT601 (32-bit, 200T), 1=FT2232H (8-bit, 50T production default)
 // ============================================================================
 // INTERNAL SIGNALS
@@ -178,11 +176,9 @@ wire tx_current_chirp_sync_valid;
 wire [31:0] rx_doppler_output;
 wire rx_doppler_valid;
 wire [4:0] rx_doppler_bin;
-wire [`RP_RANGE_BIN_BITS-1:0] rx_range_bin;
+wire [5:0] rx_range_bin;
 wire [31:0] rx_range_profile;
 wire rx_range_valid;
 wire [15:0] rx_range_profile_decimated;
 wire rx_range_profile_decimated_valid;
 wire [15:0] rx_doppler_real;
 wire [15:0] rx_doppler_imag;
 wire rx_doppler_data_valid;
@@ -227,7 +223,7 @@ wire [15:0] usb_cmd_value;
 reg [1:0]  host_radar_mode;
 reg        host_trigger_pulse;
 reg [15:0] host_detect_threshold;  // (was host_cfar_threshold)
-reg [5:0]  host_stream_control;
+reg [2:0]  host_stream_control;
 // Fix 3: Digital gain control register
 // [3]=direction: 0=amplify, 1=attenuate. [2:0]=shift amount 0..7.
@@ -254,12 +250,13 @@ reg        host_status_request;       // Opcode 0xFF (self-clearing pulse)
 localparam DOPPLER_FRAME_CHIRPS = 32; // Total chirps per Doppler frame
 reg        chirps_mismatch_error;     // Set if host tried to set chirps != FFT size
-// Range-mode register (opcode 0x20)
+// Fix 7: Range-mode register (opcode 0x20)
-// Controls chirp type selection in the mode controller:
+// Future-proofing for 3km/10km antenna switching.
-//   2'b00 = 3 km mode (all short chirps — long blind zone > max range)
+//   2'b00 = Auto (default — system selects based on scene)
-//   2'b01 = Long-range (dual chirp: first half long, second half short)
+//   2'b01 = Short-range (3km)
-//   2'b10 = Reserved
+//   2'b10 = Long-range (10km)
 //   2'b11 = Reserved
 // Currently a configuration store only — antenna/timing switching TBD.
 reg [1:0]  host_range_mode;
 // CFAR configuration registers (host-configurable via USB)
@@ -508,6 +505,8 @@ radar_receiver_final rx_inst (
    // Chirp counter from transmitter (CDC-synchronized from 120 MHz domain)
    .chirp_counter(tx_current_chirp_sync),
    // Frame-start pulse from transmitter (CDC-synchronized toggle→pulse)
    .tx_frame_start(tx_new_chirp_frame_sync),
    // ADC Physical Interface
    .adc_d_p(adc_d_p),
@@ -522,16 +521,14 @@ radar_receiver_final rx_inst (
    .doppler_bin(rx_doppler_bin),
    .range_bin(rx_range_bin),
-    // Range-profile outputs
+    // Matched filter range profile (for USB)
    .range_profile_i_out(rx_range_profile[15:0]),
    .range_profile_q_out(rx_range_profile[31:16]),
    .range_profile_valid_out(rx_range_valid),
    .decimated_range_mag_out(rx_range_profile_decimated),
    .decimated_range_valid_out(rx_range_profile_decimated_valid),
    // Host command inputs (Gap 4: USB Read Path)
    .host_mode(host_radar_mode),
    .host_trigger(host_trigger_pulse),
    .host_range_mode(host_range_mode),
    // Gap 2: Host-configurable chirp timing
    .host_long_chirp_cycles(host_long_chirp_cycles),
    .host_long_listen_cycles(host_long_listen_cycles),
@@ -601,7 +598,7 @@ assign dc_notch_active = (host_dc_notch_width != 3'd0) &&
 wire [31:0] notched_doppler_data  = dc_notch_active ? 32'd0 : rx_doppler_output;
 wire        notched_doppler_valid = rx_doppler_valid;
 wire [4:0]  notched_doppler_bin   = rx_doppler_bin;
-wire [`RP_RANGE_BIN_BITS-1:0]  notched_range_bin     = rx_range_bin;
+wire [5:0]  notched_range_bin     = rx_range_bin;
 // ============================================================================
 // CFAR DETECTOR (replaces simple threshold detector)
@@ -612,7 +609,7 @@ wire [`RP_RANGE_BIN_BITS-1:0]  notched_range_bin     = rx_range_bin;
 wire cfar_detect_flag;
 wire cfar_detect_valid;
-wire [`RP_RANGE_BIN_BITS-1:0]  cfar_detect_range;
+wire [5:0]  cfar_detect_range;
 wire [4:0]  cfar_detect_doppler;
 wire [16:0] cfar_detect_magnitude;
 wire [16:0] cfar_detect_threshold;
@@ -703,10 +700,9 @@ end
 // DATA PACKING FOR USB
 // ============================================================================
-// USB range profile must match the advertised 512-bin frame payload, so source it
+// Range profile from matched filter output (wired through radar_receiver_final)
-// from the decimated range stream that feeds Doppler rather than raw MF samples.
+assign usb_range_profile = rx_range_profile;
-assign usb_range_profile = {16'd0, rx_range_profile_decimated};
+assign usb_range_valid = rx_range_valid;
 assign usb_range_valid = rx_range_profile_decimated_valid;
 assign usb_doppler_real = rx_doppler_real;
 assign usb_doppler_imag = rx_doppler_imag;
@@ -809,11 +805,6 @@ end else begin : gen_ft2232h
        .cfar_detection(usb_detect_flag),
        .cfar_valid(usb_detect_valid),
        // Bulk frame protocol inputs
        .range_bin_in(notched_range_bin),
        .doppler_bin_in(notched_doppler_bin),
        .frame_complete(rx_frame_complete),
        // FT2232H Interface
        .ft_data(ft_data),
        .ft_rxf_n(ft_rxf_n),
@@ -922,7 +913,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
        host_radar_mode    <= 2'b01;   // Default: auto-scan
        host_trigger_pulse <= 1'b0;
        host_detect_threshold <= 16'd10000; // Default threshold
-        host_stream_control <= `RP_STREAM_CTRL_DEFAULT; // Default: all streams, mag-only mode
+        host_stream_control <= 3'b111;    // Default: all streams enabled
        host_gain_shift     <= 4'd0;      // Default: pass-through (no gain change)
        // Gap 2: chirp timing defaults (match radar_mode_controller parameters)
        host_long_chirp_cycles  <= 16'd3000;
@@ -933,7 +924,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
        host_chirps_per_elev    <= 6'd32;
        host_status_request     <= 1'b0;
        chirps_mismatch_error   <= 1'b0;
-        host_range_mode         <= 2'b00;     // Default: 3 km mode (all short chirps)
+        host_range_mode         <= 2'b00;     // Default: auto
        // CFAR defaults (disabled by default — backward-compatible)
        host_cfar_guard         <= 4'd2;      // 2 guard cells each side
        host_cfar_train         <= 5'd8;      // 8 training cells each side
@@ -960,7 +951,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
                8'h01: host_radar_mode     <= usb_cmd_value[1:0];
                8'h02: host_trigger_pulse  <= 1'b1;
                8'h03: host_detect_threshold <= usb_cmd_value;
-                8'h04: host_stream_control <= usb_cmd_value[5:0];
+                8'h04: host_stream_control <= usb_cmd_value[2:0];
                // Gap 2: chirp timing configuration
                8'h10: host_long_chirp_cycles  <= usb_cmd_value;
                8'h11: host_long_listen_cycles <= usb_cmd_value;
@@ -983,7 +974,7 @@ always @(posedge clk_100m_buf or negedge sys_reset_n) begin
                    end
                end
                8'h16: host_gain_shift         <= usb_cmd_value[3:0];  // Fix 3: digital gain
-                8'h20: host_range_mode         <= usb_cmd_value[1:0];  // Range mode
+                8'h20: host_range_mode         <= usb_cmd_value[1:0];  // Fix 7: range mode
                // CFAR configuration opcodes
                8'h21: host_cfar_guard         <= usb_cmd_value[3:0];
                8'h22: host_cfar_train         <= usb_cmd_value[4:0];
@@ -1046,9 +1037,11 @@ assign system_status = status_reg;
 // ============================================================================
 // DIG_5: AGC saturation flag — high when per-frame saturation_count > 0.
 //        STM32 reads PD13 to detect clipping and adjust ADAR1000 VGA gain.
-// DIG_6, DIG_7: Reserved (tied low for future use).
+// DIG_6: AGC enable flag — mirrors host_agc_enable so STM32 outer-loop AGC
 //        tracks the FPGA register as single source of truth.
 // DIG_7: Reserved (tied low for future use).
 assign gpio_dig5 = (rx_agc_saturation_count != 8'd0);
-assign gpio_dig6 = 1'b0;
+assign gpio_dig6 = host_agc_enable;
 assign gpio_dig7 = 1'b0;
 // ============================================================================
@@ -138,7 +138,12 @@ usb_data_interface usb_inst (
    .status_range_mode(2'b01),
    .status_self_test_flags(5'b11111),
    .status_self_test_detail(8'hA5),
-    .status_self_test_busy(1'b0)
+    .status_self_test_busy(1'b0),
    // AGC status: tie off with benign defaults (no AGC on dev board)
    .status_agc_current_gain(4'd0),
    .status_agc_peak_magnitude(8'd0),
    .status_agc_saturation_count(8'd0),
    .status_agc_enable(1'b0)
 );
 endmodule
@@ -3,7 +3,7 @@
 /**
 * range_bin_decimator.v
 *
- * Reduces 2048 range bins from the matched filter output down to 512 bins
+ * Reduces 1024 range bins from the matched filter output down to 64 bins
 * for the Doppler processor. Supports multiple decimation modes:
 *
 *   Mode 2'b00: Simple decimation (take every Nth sample)
@@ -11,31 +11,29 @@
 *   Mode 2'b10: Averaging (sum group and divide by N)
 *   Mode 2'b11: Reserved
 *
- * Interface contract (from radar_receiver_final.v):
+ * Interface contract (from radar_receiver_final.v line 229):
 *   .clk, .reset_n
- *   .range_i_in, .range_q_in, .range_valid_in   <- from matched_filter output
+ *   .range_i_in, .range_q_in, .range_valid_in   ← from matched_filter output
- *   .range_i_out, .range_q_out, .range_valid_out -> to Doppler processor
+ *   .range_i_out, .range_q_out, .range_valid_out → to Doppler processor
- *   .range_bin_index                             -> 9-bit output bin index
+ *   .range_bin_index                             → 6-bit output bin index
- *   .decimation_mode                             <- 2-bit mode select
+ *   .decimation_mode                             ← 2-bit mode select
- *   .start_bin                                   <- 11-bit start offset
+ *   .start_bin                                   ← 10-bit start offset
 *
 * start_bin usage:
 *   When start_bin > 0, the decimator skips the first 'start_bin' valid
 *   input samples before beginning decimation. This allows selecting a
- *   region of interest within the 2048 range bins (e.g., to focus on
+ *   region of interest within the 1024 range bins (e.g., to focus on
 *   near-range or far-range targets). When start_bin = 0 (default),
- *   all 2048 bins are processed starting from bin 0.
+ *   all 1024 bins are processed starting from bin 0.
 *
 * Clock domain: clk (100 MHz)
- * Decimation: 2048 -> 512 (factor of 4)
+ * Decimation: 1024 → 64 (factor of 16)
 */
 `include "radar_params.vh"
 module range_bin_decimator #(
-    parameter INPUT_BINS        = `RP_FFT_SIZE,          // 2048
+    parameter INPUT_BINS        = 1024,
-    parameter OUTPUT_BINS       = `RP_NUM_RANGE_BINS,    // 512
+    parameter OUTPUT_BINS       = 64,
-    parameter DECIMATION_FACTOR = `RP_DECIMATION_FACTOR  // 4
+    parameter DECIMATION_FACTOR = 16
 ) (
    input wire clk,
    input wire reset_n,
@@ -49,11 +47,11 @@ module range_bin_decimator #(
    output reg signed [15:0] range_i_out,
    output reg signed [15:0] range_q_out,
    output reg range_valid_out,
-    output reg [`RP_RANGE_BIN_BITS-1:0] range_bin_index,  // 9-bit
+    output reg [5:0] range_bin_index,
    // Configuration
    input wire [1:0] decimation_mode,  // 00=decimate, 01=peak, 10=average
-    input wire [10:0] start_bin,       // First input bin to process (11-bit for 2048)
+    input wire [9:0] start_bin,        // First input bin to process
    // Diagnostics
    output reg watchdog_timeout        // Pulses high for 1 cycle on watchdog reset
@@ -61,10 +59,10 @@ module range_bin_decimator #(
 `ifdef FORMAL
    ,
    output wire [2:0]  fv_state,
-    output wire [10:0] fv_in_bin_count,
+    output wire [9:0]  fv_in_bin_count,
-    output wire [1:0]  fv_group_sample_count,
+    output wire [3:0]  fv_group_sample_count,
-    output wire [8:0]  fv_output_bin_count,
+    output wire [5:0]  fv_output_bin_count,
-    output wire [10:0] fv_skip_count
+    output wire [9:0]  fv_skip_count
 `endif
 );
@@ -77,12 +75,12 @@ localparam WATCHDOG_LIMIT = 10'd256;
 // INTERNAL SIGNALS
 // ============================================================================
-// Input bin counter (0..2047)
+// Input bin counter (0..1023)
-reg [10:0] in_bin_count;
+reg [9:0] in_bin_count;
 // Group tracking
-reg [1:0] group_sample_count;   // 0..3 within current group of 4
+reg [3:0] group_sample_count;  // 0..15 within current group of 16
-reg [8:0] output_bin_count;     // 0..511 output bin index
+reg [5:0] output_bin_count;    // 0..63 output bin index
 // State machine
 reg [2:0] state;
@@ -93,7 +91,7 @@ localparam ST_EMIT    = 3'd3;
 localparam ST_DONE    = 3'd4;
 // Skip counter for start_bin
-reg [10:0] skip_count;
+reg [9:0] skip_count;
 // Watchdog counter — counts consecutive clocks with no range_valid_in
 reg [9:0] watchdog_count;
@@ -109,7 +107,7 @@ assign fv_skip_count         = skip_count;
 // ============================================================================
 // PEAK DETECTION (Mode 01)
 // ============================================================================
-// Track the sample with the largest magnitude in the current group of 4
+// Track the sample with the largest magnitude in the current group of 16
 reg signed [15:0] peak_i, peak_q;
 reg [16:0] peak_mag;  // |I| + |Q| approximation
 wire [16:0] cur_mag;
@@ -122,8 +120,8 @@ assign cur_mag = {1'b0, abs_i} + {1'b0, abs_q};
 // ============================================================================
 // AVERAGING (Mode 10)
 // ============================================================================
-// Accumulate I and Q separately, then divide by DECIMATION_FACTOR (>>2)
+// Accumulate I and Q separately, then divide by DECIMATION_FACTOR (>>4)
-reg signed [17:0] sum_i, sum_q;  // 16 + 2 guard bits for sum of 4 values
+reg signed [19:0] sum_i, sum_q;  // 16 + 4 guard bits for sum of 16 values
 // ============================================================================
 // SIMPLE DECIMATION (Mode 00)
@@ -137,21 +135,21 @@ reg signed [15:0] decim_i, decim_q;
 always @(posedge clk or negedge reset_n) begin
    if (!reset_n) begin
        state             <= ST_IDLE;
-        in_bin_count      <= 11'd0;
+        in_bin_count      <= 10'd0;
-        group_sample_count <= 2'd0;
+        group_sample_count <= 4'd0;
-        output_bin_count  <= 9'd0;
+        output_bin_count  <= 6'd0;
-        skip_count        <= 11'd0;
+        skip_count        <= 10'd0;
        watchdog_count    <= 10'd0;
        watchdog_timeout  <= 1'b0;
        range_valid_out   <= 1'b0;
        range_i_out       <= 16'd0;
        range_q_out       <= 16'd0;
-        range_bin_index   <= {`RP_RANGE_BIN_BITS{1'b0}};
+        range_bin_index   <= 6'd0;
        peak_i            <= 16'd0;
        peak_q            <= 16'd0;
        peak_mag          <= 17'd0;
-        sum_i             <= 18'd0;
+        sum_i             <= 20'd0;
-        sum_q             <= 18'd0;
+        sum_q             <= 20'd0;
        decim_i           <= 16'd0;
        decim_q           <= 16'd0;
    end else begin
@@ -164,33 +162,33 @@ always @(posedge clk or negedge reset_n) begin
        // IDLE: Wait for first valid input
        // ================================================================
        ST_IDLE: begin
-            in_bin_count       <= 11'd0;
+            in_bin_count       <= 10'd0;
-            group_sample_count <= 2'd0;
+            group_sample_count <= 4'd0;
-            output_bin_count   <= 9'd0;
+            output_bin_count   <= 6'd0;
-            skip_count         <= 11'd0;
+            skip_count         <= 10'd0;
            watchdog_count     <= 10'd0;
            peak_i             <= 16'd0;
            peak_q             <= 16'd0;
            peak_mag           <= 17'd0;
-            sum_i              <= 18'd0;
+            sum_i              <= 20'd0;
-            sum_q              <= 18'd0;
+            sum_q              <= 20'd0;
            if (range_valid_in) begin
-                in_bin_count <= 11'd1;
+                in_bin_count <= 10'd1;
-                if (start_bin > 11'd0) begin
+                if (start_bin > 10'd0) begin
                    // Need to skip 'start_bin' samples first
-                    skip_count <= 11'd1;
+                    skip_count <= 10'd1;
                    state      <= ST_SKIP;
                end else begin
                    // No skip — process first sample immediately
                    state              <= ST_PROCESS;
-                    group_sample_count <= 2'd1;
+                    group_sample_count <= 4'd1;
                    // Mode-specific first sample handling
                    case (decimation_mode)
                    2'b00: begin  // Simple decimation — check if center sample
-                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
                            decim_i <= range_i_in;
                            decim_q <= range_q_in;
                        end
@@ -201,8 +199,8 @@ always @(posedge clk or negedge reset_n) begin
                        peak_mag <= cur_mag;
                    end
                    2'b10: begin  // Averaging
-                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
+                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
                    end
                    default: ;
                    endcase
@@ -221,11 +219,11 @@ always @(posedge clk or negedge reset_n) begin
                if (skip_count >= start_bin) begin
                    // Done skipping — this sample is the first to process
                    state              <= ST_PROCESS;
-                    group_sample_count <= 2'd1;
+                    group_sample_count <= 4'd1;
                    case (decimation_mode)
                    2'b00: begin
-                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
                            decim_i <= range_i_in;
                            decim_q <= range_q_in;
                        end
@@ -236,8 +234,8 @@ always @(posedge clk or negedge reset_n) begin
                        peak_mag <= cur_mag;
                    end
                    2'b10: begin
-                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
+                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
                    end
                    default: ;
                    endcase
@@ -283,8 +281,8 @@ always @(posedge clk or negedge reset_n) begin
                    end
                end
                2'b10: begin  // Averaging
-                    sum_i <= sum_i + {{2{range_i_in[15]}}, range_i_in};
+                    sum_i <= sum_i + {{4{range_i_in[15]}}, range_i_in};
-                    sum_q <= sum_q + {{2{range_q_in[15]}}, range_q_in};
+                    sum_q <= sum_q + {{4{range_q_in[15]}}, range_q_in};
                end
                default: ;
                endcase
@@ -293,7 +291,7 @@ always @(posedge clk or negedge reset_n) begin
                if (group_sample_count == DECIMATION_FACTOR - 1) begin
                    // Group complete — emit output
                    state <= ST_EMIT;
-                    group_sample_count <= 2'd0;
+                    group_sample_count <= 4'd0;
                end else if (in_bin_count >= INPUT_BINS - 1) begin
                    // Overflow guard: consumed all input bins but group
                    // is not yet complete. Stop to prevent corruption of
@@ -333,9 +331,9 @@ always @(posedge clk or negedge reset_n) begin
                range_i_out <= peak_i;
                range_q_out <= peak_q;
            end
-            2'b10: begin  // Averaging (sum >> 2 = divide by 4)
+            2'b10: begin  // Averaging (sum >> 4 = divide by 16)
-                range_i_out <= sum_i[17:2];
+                range_i_out <= sum_i[19:4];
-                range_q_out <= sum_q[17:2];
+                range_q_out <= sum_q[19:4];
            end
            default: begin
                range_i_out <= 16'd0;
@@ -347,8 +345,8 @@ always @(posedge clk or negedge reset_n) begin
            peak_i   <= 16'd0;
            peak_q   <= 16'd0;
            peak_mag <= 17'd0;
-            sum_i    <= 18'd0;
+            sum_i    <= 20'd0;
-            sum_q    <= 18'd0;
+            sum_q    <= 20'd0;
            // Advance output bin
            output_bin_count <= output_bin_count + 1;
@@ -360,12 +358,12 @@ always @(posedge clk or negedge reset_n) begin
                // If we already have valid input waiting, process it immediately
                if (range_valid_in) begin
                    state              <= ST_PROCESS;
-                    group_sample_count <= 2'd1;
+                    group_sample_count <= 4'd1;
                    in_bin_count       <= in_bin_count + 1;
                    case (decimation_mode)
                    2'b00: begin
-                        if (2'd0 == (DECIMATION_FACTOR / 2)) begin
+                        if (4'd0 == (DECIMATION_FACTOR / 2)) begin
                            decim_i <= range_i_in;
                            decim_q <= range_q_in;
                        end
@@ -376,20 +374,20 @@ always @(posedge clk or negedge reset_n) begin
                        peak_mag <= cur_mag;
                    end
                    2'b10: begin
-                        sum_i <= {{2{range_i_in[15]}}, range_i_in};
+                        sum_i <= {{4{range_i_in[15]}}, range_i_in};
-                        sum_q <= {{2{range_q_in[15]}}, range_q_in};
+                        sum_q <= {{4{range_q_in[15]}}, range_q_in};
                    end
                    default: ;
                    endcase
                end else begin
                    state <= ST_PROCESS;
-                    group_sample_count <= 2'd0;
+                    group_sample_count <= 4'd0;
                end
            end
        end
        // ================================================================
-        // DONE: All 512 output bins emitted, return to idle
+        // DONE: All 64 output bins emitted, return to idle
        // ================================================================
        ST_DONE: begin
            state <= ST_IDLE;
@@ -70,6 +70,7 @@ PROD_RTL=(
    xfft_16.v
    fft_engine.v
    usb_data_interface.v
    usb_data_interface_ft2232h.v
    edge_detector.v
    radar_mode_controller.v
    rx_gain_control.v
@@ -86,6 +87,33 @@ EXTRA_RTL=(
    frequency_matched_filter.v
 )
 # ---------------------------------------------------------------------------
 # Shared RTL file lists for integration / system tests
 # Centralised here so a new module only needs adding once.
 # ---------------------------------------------------------------------------
 # Receiver chain (used by golden generate/compare tests)
 RECEIVER_RTL=(
    radar_receiver_final.v
    radar_mode_controller.v
    tb/ad9484_interface_400m_stub.v
    ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v
    cdc_modules.v fir_lowpass.v ddc_input_interface.v
    chirp_memory_loader_param.v latency_buffer.v
    matched_filter_multi_segment.v matched_filter_processing_chain.v
    range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v
    rx_gain_control.v mti_canceller.v
 )
 # Full system top (receiver chain + TX + USB + detection + self-test)
 SYSTEM_RTL=(
    radar_system_top.v
    radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v
    "${RECEIVER_RTL[@]}"
    usb_data_interface.v usb_data_interface_ft2232h.v edge_detector.v
    cfar_ca.v fpga_self_test.v
 )
 # ---- Layer A: iverilog -Wall compilation ----
 run_lint_iverilog() {
    local label="$1"
@@ -219,26 +247,9 @@ run_lint_static() {
        fi
    done
-    # --- Single-line regex checks across all production RTL ---
+    # CHECK 5 ($readmemh in synth code) and CHECK 6 (unused includes)
-    for f in "$@"; do
+    # require multi-line ifdef tracking / cross-file analysis. Not feasible
-        [[ -f "$f" ]] || continue
+    # with line-by-line regex. Omitted — use Vivado lint instead.
        case "$f" in tb/*) continue ;; esac
        local linenum=0
        while IFS= read -r line; do
            linenum=$((linenum + 1))
            # CHECK 5: $readmemh / $readmemb in synthesizable code
            # (Only valid in simulation blocks — flag if outside `ifdef SIMULATION)
            # This is hard to check line-by-line without tracking ifdefs.
            # Skip for v1.
            # CHECK 6: Unused `include files (informational only)
            # Skip for v1.
            :  # placeholder — prevents empty loop body
        done < "$f"
    done
    if [[ "$err_count" -gt 0 ]]; then
        echo -e "${RED}FAIL${NC} ($err_count errors, $warn_count warnings)"
@@ -253,141 +264,11 @@ run_lint_static() {
    fi
 }
 # ---------------------------------------------------------------------------
 # Helper: compile, run, and compare a matched-filter co-sim scenario
 #   run_mf_cosim <scenario_name> <define_flag>
 # ---------------------------------------------------------------------------
 run_mf_cosim() {
    local name="$1"
    local define="$2"
    local vvp="tb/tb_mf_cosim_${name}.vvp"
    local scenario_lower="$name"
    printf "  %-45s " "MF Co-Sim ($name)"
    # Compile — build command as string to handle optional define
    local cmd="iverilog -g2001 -DSIMULATION"
    if [[ -n "$define" ]]; then
        cmd="$cmd $define"
    fi
    cmd="$cmd -o $vvp tb/tb_mf_cosim.v matched_filter_processing_chain.v fft_engine.v chirp_memory_loader_param.v"
    if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
        echo -e "${RED}COMPILE FAIL${NC}"
        ERRORS="$ERRORS\n  MF Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
        FAIL=$((FAIL + 1))
        return
    fi
    # Run TB
    local output
    output=$(timeout 120 vvp "$vvp" 2>&1) || true
    rm -f "$vvp"
    # Check TB internal pass/fail
    local tb_fail
    tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
    if [[ "$tb_fail" -gt 0 ]]; then
        echo -e "${RED}FAIL${NC} (TB internal failure)"
        ERRORS="$ERRORS\n  MF Co-Sim ($name): TB internal failure"
        FAIL=$((FAIL + 1))
        return
    fi
    # Run Python compare
    if command -v python3 >/dev/null 2>&1; then
        local compare_out
        local compare_rc=0
        compare_out=$(python3 tb/cosim/compare_mf.py "$scenario_lower" 2>&1) || compare_rc=$?
        if [[ "$compare_rc" -ne 0 ]]; then
            echo -e "${RED}FAIL${NC} (compare_mf.py mismatch)"
            ERRORS="$ERRORS\n  MF Co-Sim ($name): Python compare failed"
            FAIL=$((FAIL + 1))
            return
        fi
    else
        echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
        SKIP=$((SKIP + 1))
        return
    fi
    echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
    PASS=$((PASS + 1))
 }
 # ---------------------------------------------------------------------------
 # Helper: compile, run, and compare a Doppler co-sim scenario
 #   run_doppler_cosim <scenario_name> <define_flag>
 # ---------------------------------------------------------------------------
 run_doppler_cosim() {
    local name="$1"
    local define="$2"
    local vvp="tb/tb_doppler_cosim_${name}.vvp"
    printf "  %-45s " "Doppler Co-Sim ($name)"
    # Compile — build command as string to handle optional define
    local cmd="iverilog -g2001 -DSIMULATION"
    if [[ -n "$define" ]]; then
        cmd="$cmd $define"
    fi
    cmd="$cmd -o $vvp tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v"
    if ! eval "$cmd" 2>/tmp/iverilog_err_$$; then
        echo -e "${RED}COMPILE FAIL${NC}"
        ERRORS="$ERRORS\n  Doppler Co-Sim ($name): compile error ($(head -1 /tmp/iverilog_err_$$))"
        FAIL=$((FAIL + 1))
        return
    fi
    # Run TB
    local output
    output=$(timeout 120 vvp "$vvp" 2>&1) || true
    rm -f "$vvp"
    # Check TB internal pass/fail
    local tb_fail
    tb_fail=$(echo "$output" | grep -Ec '^\[FAIL' || true)
    if [[ "$tb_fail" -gt 0 ]]; then
        echo -e "${RED}FAIL${NC} (TB internal failure)"
        ERRORS="$ERRORS\n  Doppler Co-Sim ($name): TB internal failure"
        FAIL=$((FAIL + 1))
        return
    fi
    # Run Python compare
    if command -v python3 >/dev/null 2>&1; then
        local compare_out
        local compare_rc=0
        compare_out=$(python3 tb/cosim/compare_doppler.py "$name" 2>&1) || compare_rc=$?
        if [[ "$compare_rc" -ne 0 ]]; then
            echo -e "${RED}FAIL${NC} (compare_doppler.py mismatch)"
            ERRORS="$ERRORS\n  Doppler Co-Sim ($name): Python compare failed"
            FAIL=$((FAIL + 1))
            return
        fi
    else
        echo -e "${YELLOW}SKIP${NC} (RTL passed, python3 not found — compare skipped)"
        SKIP=$((SKIP + 1))
        return
    fi
    echo -e "${GREEN}PASS${NC} (RTL + Python compare)"
    PASS=$((PASS + 1))
 }
 # ---------------------------------------------------------------------------
 # Helper: compile and run a single testbench
 #   run_test <name> <vvp_path> <iverilog_args...>
 # ---------------------------------------------------------------------------
 run_test() {
    # Optional: --timeout=N as first arg overrides default 120s
    local timeout_secs=120
    if [[ "$1" == --timeout=* ]]; then
        timeout_secs="${1#--timeout=}"
        shift
    fi
    local name="$1"
    local vvp="$2"
    shift 2
@@ -405,7 +286,7 @@ run_test() {
    # Run
    local output
-    output=$(timeout "$timeout_secs" vvp "$vvp" 2>&1) || true
+    output=$(timeout 120 vvp "$vvp" 2>&1) || true
    # Count PASS/FAIL in output (testbenches use explicit [PASS]/[FAIL] markers)
    local test_pass test_fail
@@ -497,9 +378,9 @@ run_test "Chirp Contract" \
    tb/tb_chirp_ctr_reg.vvp \
    tb/tb_chirp_contract.v plfm_chirp_controller.v
-run_doppler_cosim "stationary"   ""
+run_test "Doppler Processor (DSP48)" \
-run_doppler_cosim "moving"       "-DSCENARIO_MOVING"
+    tb/tb_doppler_reg.vvp \
-run_doppler_cosim "two_targets"  "-DSCENARIO_TWO"
+    tb/tb_doppler_cosim.v doppler_processor.v xfft_16.v fft_engine.v
 run_test "Threshold Detector (detection bugs)" \
    tb/tb_threshold_detector.vvp \
@@ -546,82 +427,44 @@ run_test "Full-Chain Real-Data (decim→Doppler, exact match)" \
    doppler_processor.v xfft_16.v fft_engine.v
 if [[ "$QUICK" -eq 0 ]]; then
-    # NOTE: The "Receiver golden generate/compare" pair was REMOVED because
+    # Golden generate
-    # it was self-blessing: both passes ran the same RTL with the same
+    run_test "Receiver (golden generate)" \
-    # deterministic stimulus, so the test always passed regardless of bugs.
+        tb/tb_rx_golden_reg.vvp \
-    # Real co-sim coverage is provided by:
+        -DGOLDEN_GENERATE \
-    #   - tb_doppler_realdata.v  (committed Python golden hex, exact match)
+        tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
    #   - tb_fullchain_realdata.v (committed Python golden hex, exact match)
    # A proper full-pipeline co-sim (DDC→MF→Decim→Doppler vs Python) is
    # planned as a replacement (Phase C of CI test plan).
-    # Receiver integration (structural + bounds + pulse assertions)
+    # Golden compare
-    # Tests the full RX pipeline: ADC stub → DDC → MF → Decim → Doppler
+    run_test "Receiver (golden compare)" \
-    # Verifies doppler_frame_done is a single-cycle pulse (catches
+        tb/tb_rx_compare_reg.vvp \
-    # level-vs-pulse wiring bugs at module boundaries).
+        tb/tb_radar_receiver_final.v "${RECEIVER_RTL[@]}"
    run_test --timeout=600 "Receiver Integration (tb_radar_receiver_final)" \
        tb/tb_rx_final_reg.vvp \
        tb/tb_radar_receiver_final.v \
        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
        rx_gain_control.v \
        chirp_memory_loader_param.v latency_buffer.v \
        matched_filter_multi_segment.v matched_filter_processing_chain.v \
        range_bin_decimator.v mti_canceller.v \
        doppler_processor.v xfft_16.v fft_engine.v \
        radar_mode_controller.v
    # Full system top (monitoring-only, legacy)
    run_test "System Top (radar_system_tb)" \
        tb/tb_system_reg.vvp \
-        tb/radar_system_tb.v radar_system_top.v \
+        tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
        radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
        chirp_memory_loader_param.v latency_buffer.v \
        matched_filter_multi_segment.v matched_filter_processing_chain.v \
        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
        usb_data_interface.v edge_detector.v radar_mode_controller.v \
        rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
    # E2E integration (46 strict checks: TX, RX, USB R/W, CDC, safety, reset)
    run_test "System E2E (tb_system_e2e)" \
        tb/tb_system_e2e_reg.vvp \
-        tb/tb_system_e2e.v radar_system_top.v \
+        tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
-        radar_transmitter.v dac_interface_single.v plfm_chirp_controller.v \
+
-        radar_receiver_final.v tb/ad9484_interface_400m_stub.v \
+    # USB_MODE=1 (FT2232H production) variants of system tests
-        ddc_400m.v nco_400m_enhanced.v cic_decimator_4x_enhanced.v \
+    run_test "System Top USB_MODE=1 (FT2232H)" \
-        cdc_modules.v fir_lowpass.v ddc_input_interface.v \
+        tb/tb_system_ft2232h_reg.vvp \
-        chirp_memory_loader_param.v latency_buffer.v \
+        -DUSB_MODE_1 \
-        matched_filter_multi_segment.v matched_filter_processing_chain.v \
+        tb/radar_system_tb.v "${SYSTEM_RTL[@]}"
-        range_bin_decimator.v doppler_processor.v xfft_16.v fft_engine.v \
+
-        usb_data_interface.v edge_detector.v radar_mode_controller.v \
+    run_test "System E2E USB_MODE=1 (FT2232H)" \
-        rx_gain_control.v cfar_ca.v mti_canceller.v fpga_self_test.v
+        tb/tb_system_e2e_ft2232h_reg.vvp \
        -DUSB_MODE_1 \
        tb/tb_system_e2e.v "${SYSTEM_RTL[@]}"
 else
-    echo "  (skipped system top + E2E — use without --quick)"
+    echo "  (skipped receiver golden + system top + E2E — use without --quick)"
-    SKIP=$((SKIP + 2))
+    SKIP=$((SKIP + 6))
 fi
 echo ""
 # ===========================================================================
 # PHASE 2b: MATCHED FILTER CO-SIMULATION (RTL vs Python golden reference)
 # Runs tb_mf_cosim.v for 4 scenarios, then compare_mf.py validates output
 # against committed Python golden CSV files. In SIMULATION mode, thresholds
 # are generous (behavioral vs fixed-point twiddles differ) — validates
 # state machine mechanics, output count, and energy sanity.
 # ===========================================================================
 echo "--- PHASE 2b: Matched Filter Co-Sim ---"
 run_mf_cosim "chirp"   ""
 run_mf_cosim "dc"      "-DSCENARIO_DC"
 run_mf_cosim "impulse" "-DSCENARIO_IMPULSE"
 run_mf_cosim "tone5"   "-DSCENARIO_TONE5"
 echo ""
 # ===========================================================================
 # PHASE 3: UNIT TESTS — Signal Processing
 # ===========================================================================
@@ -54,7 +54,7 @@ module rx_gain_control (
    input  wire [3:0]  agc_decay,      // 0x2B: amplification step when weak (default 1)
    input  wire [3:0]  agc_holdoff,    // 0x2C: frames to wait before gain-up (default 4)
-    // Frame boundary pulse (1 clk cycle, from edge detector in radar_receiver_final)
+    // Frame boundary pulse (1 clk cycle, from Doppler frame_complete)
    input  wire        frame_boundary,
    // Data output (to matched filter)
@@ -169,11 +169,11 @@ endfunction
 // =========================================================================
 // Clamp a wider signed value to [-7, +7]
 function signed [3:0] clamp_gain;
-    input signed [4:0] val;  // 5-bit to handle overflow from add
+    input signed [5:0] val;  // 6-bit: covers [-22,+22] (max |gain|+step = 7+15)
    begin
-        if (val > 5'sd7)
+        if (val > 6'sd7)
            clamp_gain = 4'sd7;
-        else if (val < -5'sd7)
+        else if (val < -6'sd7)
            clamp_gain = -4'sd7;
        else
            clamp_gain = val[3:0];
@@ -246,15 +246,15 @@ always @(posedge clk or negedge reset_n) begin
                // Use inclusive counts/peaks (accounting for simultaneous valid_in)
                if (wire_frame_sat_incr || frame_sat_count > 8'd0) begin
                    // Clipping detected: reduce gain immediately (attack)
-                    agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) -
+                    agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain[3], agc_gain}) -
-                                           $signed({1'b0, agc_attack}));
+                                           $signed({2'b00, agc_attack}));
                    holdoff_counter <= agc_holdoff;  // Reset holdoff
                end else if ((wire_frame_peak_update ? max_iq[14:7] : frame_peak[14:7])
                             < agc_target) begin
                    // Signal too weak: increase gain after holdoff expires
                    if (holdoff_counter == 4'd0) begin
-                        agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain}) +
+                        agc_gain <= clamp_gain($signed({agc_gain[3], agc_gain[3], agc_gain}) +
-                                               $signed({1'b0, agc_decay}));
+                                               $signed({2'b00, agc_decay}));
                    end else begin
                        holdoff_counter <= holdoff_counter - 4'd1;
                    end
@@ -108,6 +108,9 @@ add_files -fileset constrs_1 -norecurse [file join $project_root "constraints" "
 set_property top $top_module [current_fileset]
 set_property verilog_define {FFT_XPM_BRAM} [current_fileset]
 # Override USB_MODE to 0 (FT601) for 200T premium board.
 # The RTL default is USB_MODE=1 (FT2232H, production 50T).
 set_property generic {USB_MODE=0} [current_fileset]
 # ==============================================================================
 # 2. Synthesis
@@ -34,8 +34,8 @@ sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 # =============================================================================
 DOPPLER_FFT = 32
-RANGE_BINS = 512
+RANGE_BINS = 64
-TOTAL_OUTPUTS = RANGE_BINS * DOPPLER_FFT  # 16384
+TOTAL_OUTPUTS = RANGE_BINS * DOPPLER_FFT  # 2048
 SUBFRAME_SIZE = 16
 SCENARIOS = {
@@ -246,7 +246,7 @@ def compare_scenario(name, config, base_dir):
    # ---- Pass/Fail ----
    checks = []
-    checks.append(('RTL output count == 16384', count_ok))
+    checks.append(('RTL output count == 2048', count_ok))
    energy_ok = (ENERGY_RATIO_MIN < energy_ratio < ENERGY_RATIO_MAX)
    checks.append((f'Energy ratio in bounds '
@@ -36,7 +36,7 @@ sys.path.insert(0, os.path.dirname(os.path.abspath(__file__)))
 # Configuration
 # =============================================================================
-FFT_SIZE = 2048
+FFT_SIZE = 1024
 SCENARIOS = {
    'chirp': {
@@ -243,7 +243,7 @@ def compare_scenario(scenario_name, config, base_dir):
    # Check 2: RTL produced expected sample count
    correct_count = len(rtl_i) == FFT_SIZE
-    checks.append(('Correct output count (2048)', correct_count))
+    checks.append(('Correct output count (1024)', correct_count))
    # Check 3: Energy ratio within generous bounds
    # Allow very wide range since twiddle differences cause large gain variation
@@ -291,9 +291,12 @@ class Mixer:
        Convert 8-bit unsigned ADC to 18-bit signed.
        RTL: adc_signed_w = {1'b0, adc_data, {9{1'b0}}} -
                            {1'b0, {8{1'b1}}, {9{1'b0}}} / 2
-        = (adc_data << 9) - (0xFF << 9) / 2
+
-        = (adc_data << 9) - (0xFF << 8)  [integer division]
+        Verilog '/' binds tighter than '-', so the division applies
-        = (adc_data << 9) - 0x7F80
+        only to the second concatenation:
            {1'b0, 8'hFF, 9'b0} = 0x1FE00
            0x1FE00 / 2 = 0xFF00 = 65280
        Result: (adc_data << 9) - 0xFF00
        """
        adc_data_8bit = adc_data_8bit & 0xFF
        # {1'b0, adc_data, 9'b0} = adc_data << 9, zero-padded to 18 bits
@@ -709,23 +712,14 @@ class DDCInputInterface:
 # FFT Engine (1024-point radix-2 DIT, in-place, 32-bit internal)
 # =============================================================================
-def load_twiddle_rom(filepath=None, n=2048):
+def load_twiddle_rom(filepath=None):
    """
-    Load quarter-wave cosine ROM from hex file.
+    Load 256-entry quarter-wave cosine ROM from hex file.
-    Returns list of N/4 signed 16-bit integers.
+    Returns list of 256 signed 16-bit integers.
    For N=2048: loads fft_twiddle_2048.mem (512 entries).
    For N=1024: loads fft_twiddle_1024.mem (256 entries).
    For N=16:   loads fft_twiddle_16.mem (4 entries).
    """
    if filepath is None:
        # Default path relative to this file
        base = os.path.dirname(os.path.abspath(__file__))
        if n == 2048:
            filepath = os.path.join(base, '..', '..', 'fft_twiddle_2048.mem')
        elif n == 16:
            filepath = os.path.join(base, '..', '..', 'fft_twiddle_16.mem')
        else:
        filepath = os.path.join(base, '..', '..', 'fft_twiddle_1024.mem')
    values = []
@@ -768,17 +762,17 @@ class FFTEngine:
    """
    Bit-accurate model of fft_engine.v
-    2048-point radix-2 DIT FFT/IFFT.
+    1024-point radix-2 DIT FFT/IFFT.
    Internal: 32-bit signed working data.
    Twiddle: 16-bit Q15 from quarter-wave cosine ROM.
    Butterfly: multiply 32x16->49 bits, >>>15, add/subtract.
    Output: saturate 32->16 bits. IFFT also >>>LOG2N before saturate.
    """
-    def __init__(self, n=2048, twiddle_file=None):
+    def __init__(self, n=1024, twiddle_file=None):
        self.N = n
        self.LOG2N = n.bit_length() - 1
-        self.cos_rom = load_twiddle_rom(twiddle_file, n=n)
+        self.cos_rom = load_twiddle_rom(twiddle_file)
        # Working memory (32-bit signed I/Q pairs)
        self.mem_re = [0] * n
        self.mem_im = [0] * n
@@ -951,21 +945,21 @@ class MatchedFilterChain:
    Uses a single FFTEngine instance (as in RTL, engine is reused).
    """
-    def __init__(self, fft_size=2048, twiddle_file=None):
+    def __init__(self, fft_size=1024, twiddle_file=None):
        self.fft_size = fft_size
        self.fft = FFTEngine(n=fft_size, twiddle_file=twiddle_file)
        self.conj_mult = FreqMatchedFilter()
    def process(self, sig_re, sig_im, ref_re, ref_im):
        """
-        Run matched filter on signal + reference.
+        Run matched filter on 1024-sample signal + reference.
        Args:
-            sig_re/im: signal I/Q (16-bit signed, fft_size samples)
+            sig_re/im: signal I/Q (16-bit signed, 1024 samples)
-            ref_re/im: reference chirp I/Q (16-bit signed, fft_size samples)
+            ref_re/im: reference chirp I/Q (16-bit signed, 1024 samples)
        Returns:
-            (range_profile_re, range_profile_im): fft_size x 16-bit signed
+            (range_profile_re, range_profile_im): 1024 x 16-bit signed
        """
        # Forward FFT of signal
        sig_fft_re, sig_fft_im = self.fft.compute(sig_re, sig_im, inverse=False)
@@ -993,27 +987,27 @@ class RangeBinDecimator:
    Bit-accurate model of range_bin_decimator.v
    Three modes:
-      00: Simple decimation (take center sample at index 2)
+      00: Simple decimation (take center sample at index 8)
      01: Peak detection (max |I|+|Q|)
-      10: Averaging (sum >> 2, truncation)
+      10: Averaging (sum >> 4, truncation)
      11: Reserved (output 0)
    """
-    DECIMATION_FACTOR = 4
+    DECIMATION_FACTOR = 16
-    OUTPUT_BINS = 512
+    OUTPUT_BINS = 64
    @staticmethod
    def decimate(range_re, range_im, mode=1, start_bin=0):
        """
-        Decimate 2048 range bins to 512.
+        Decimate 1024 range bins to 64.
        Args:
-            range_re/im: 2048 x signed 16-bit
+            range_re/im: 1024 x signed 16-bit
            mode: 0=center, 1=peak, 2=average, 3=zero
-            start_bin: first input bin to process (0-2047)
+            start_bin: first input bin to process (0-1023)
        Returns:
-            (out_re, out_im): 512 x signed 16-bit
+            (out_re, out_im): 64 x signed 16-bit
        """
        out_re = []
        out_im = []
@@ -1061,9 +1055,9 @@ class RangeBinDecimator:
                    if idx < len(range_re):
                        sum_re += sign_extend(range_re[idx] & 0xFFFF, 16)
                        sum_im += sign_extend(range_im[idx] & 0xFFFF, 16)
-                # Truncate (arithmetic right shift by 2), take 16 bits
+                # Truncate (arithmetic right shift by 4), take 16 bits
-                out_re.append(sign_extend((sum_re >> 2) & 0xFFFF, 16))
+                out_re.append(sign_extend((sum_re >> 4) & 0xFFFF, 16))
-                out_im.append(sign_extend((sum_im >> 2) & 0xFFFF, 16))
+                out_im.append(sign_extend((sum_im >> 4) & 0xFFFF, 16))
            else:
                # Mode 3: reserved, output 0
@@ -1099,7 +1093,7 @@ class DopplerProcessor:
    """
    DOPPLER_FFT_SIZE = 16     # Per sub-frame
-    RANGE_BINS = 512
+    RANGE_BINS = 64
    CHIRPS_PER_FRAME = 32
    CHIRPS_PER_SUBFRAME = 16
@@ -1135,11 +1129,11 @@ class DopplerProcessor:
        Process one complete Doppler frame using dual 16-pt FFTs.
        Args:
-            chirp_data_i: 2D array [32 chirps][512 range bins] of signed 16-bit I
+            chirp_data_i: 2D array [32 chirps][64 range bins] of signed 16-bit I
-            chirp_data_q: 2D array [32 chirps][512 range bins] of signed 16-bit Q
+            chirp_data_q: 2D array [32 chirps][64 range bins] of signed 16-bit Q
        Returns:
-            (doppler_map_i, doppler_map_q): 2D arrays [512 range bins][32 doppler bins]
+            (doppler_map_i, doppler_map_q): 2D arrays [64 range bins][32 doppler bins]
                                            of signed 16-bit
                                            Bins 0-15 = sub-frame 0 (long PRI)
                                            Bins 16-31 = sub-frame 1 (short PRI)
@@ -1222,7 +1216,7 @@ class SignalChain:
    IF_FREQ = 120_000_000    # IF frequency
    FTW_120MHZ = 0x4CCCCCCD  # Phase increment for 120 MHz at 400 MSPS
-    def __init__(self, twiddle_file_2048=None, twiddle_file_16=None):
+    def __init__(self, twiddle_file_1024=None, twiddle_file_16=None):
        self.nco = NCO()
        self.mixer = Mixer()
        self.cic_i = CICDecimator()
@@ -1230,7 +1224,7 @@ class SignalChain:
        self.fir_i = FIRFilter()
        self.fir_q = FIRFilter()
        self.ddc_interface = DDCInputInterface()
-        self.matched_filter = MatchedFilterChain(fft_size=2048, twiddle_file=twiddle_file_2048)
+        self.matched_filter = MatchedFilterChain(fft_size=1024, twiddle_file=twiddle_file_1024)
        self.range_decimator = RangeBinDecimator()
        self.doppler = DopplerProcessor(twiddle_file_16=twiddle_file_16)
@@ -2,22 +2,34 @@
 """
 gen_chirp_mem.py — Generate all chirp .mem files for AERIS-10 FPGA.
-Generates the 6 chirp .mem files used by chirp_memory_loader_param.v:
+Generates the 10 chirp .mem files used by chirp_memory_loader_param.v:
-  - long_chirp_seg{0,1}_{i,q}.mem  (4 files, 2048 lines each)
+  - long_chirp_seg{0,1,2,3}_{i,q}.mem  (8 files, 1024 lines each)
  - short_chirp_{i,q}.mem              (2 files, 50 lines each)
 Long chirp:
  The 3000-sample baseband chirp (30 us at 100 MHz system clock) is
-  segmented into 2 blocks of 2048 samples.  Each segment covers a
+  segmented into 4 blocks of 1024 samples.  Each segment covers a
  different time window of the chirp:
-    seg0: samples    0 .. 2047
+    seg0: samples   0 .. 1023
-    seg1: samples 2048 .. 4095  (only 952 valid chirp samples; 1096 zeros)
+    seg1: samples 1024 .. 2047
    seg2: samples 2048 .. 3071  (only 952 valid chirp samples; 72 zeros)
    seg3: all zeros (seg3 starts at sample 3072, past chirp end at 3000)
-  The memory loader stores 2*2048 = 4096 contiguous samples indexed
+  Wait — actually the memory loader stores 4*1024 = 4096 contiguous
-  by {segment_select[0], sample_addr[10:0]}.  The long chirp has
+  samples indexed by {segment_select[1:0], sample_addr[9:0]}.  The
-  3000 samples, so:
+  long chirp has 3000 samples, so:
-    seg0: chirp[0..2047] — all valid data
+    seg0: chirp[0..1023]
-    seg1: chirp[2048..2999] + 1096 zeros (samples past chirp end)
+    seg1: chirp[1024..2047]
    seg2: chirp[2048..2999] + 24 zeros  (samples 2048..3071 but chirp
          ends at 2999, so indices 3000..3071 relative to full chirp
          => mem indices 952..1023 in seg2 file are zero)
  Wait, let me re-count.  seg2 covers global indices 2048..3071.
  The chirp has samples 0..2999 (3000 samples).  So seg2 has valid
  data at global indices 2048..2999 = 952 valid samples (seg2 file
  indices 0..951), then zeros at file indices 952..1023 (72 zeros).
  seg3 covers global indices 3072..4095, all past chirp end => all zeros.
 Short chirp:
  50 samples (0.5 us at 100 MHz), same chirp formula with
@@ -44,10 +56,10 @@ CHIRP_BW = 20e6           # 20 MHz sweep bandwidth
 FS_SYS = 100e6            # System clock (100 MHz, post-CIC)
 T_LONG_CHIRP = 30e-6      # 30 us long chirp duration
 T_SHORT_CHIRP = 0.5e-6    # 0.5 us short chirp duration
-FFT_SIZE = 2048
+FFT_SIZE = 1024
 LONG_CHIRP_SAMPLES = int(T_LONG_CHIRP * FS_SYS)   # 3000
 SHORT_CHIRP_SAMPLES = int(T_SHORT_CHIRP * FS_SYS)  # 50
-LONG_SEGMENTS = 2
+LONG_SEGMENTS = 4
 SCALE = 0.9               # Q15 scaling factor (matches radar_scene.py)
 Q15_MAX = 32767
@@ -175,14 +187,13 @@ def main():
    # Check magnitude envelope
    max(math.sqrt(i*i + q*q) for i, q in zip(long_i, long_q, strict=False))
-    # Check seg1 zero padding (samples 3000-4095 should be zero)
+    # Check seg3 zero padding
-    seg1_i_path = os.path.join(MEM_DIR, 'long_chirp_seg1_i.mem')
+    seg3_i_path = os.path.join(MEM_DIR, 'long_chirp_seg3_i.mem')
-    with open(seg1_i_path) as f:
+    with open(seg3_i_path) as f:
-        seg1_lines = [line.strip() for line in f if line.strip()]
+        seg3_lines = [line.strip() for line in f if line.strip()]
-    # Indices 952..2047 in seg1 (global 3000..4095) should be zero
+    nonzero_seg3 = sum(1 for line in seg3_lines if line != '0000')
    nonzero_tail = sum(1 for line in seg1_lines[952:] if line != '0000')
-    if nonzero_tail == 0:
+    if nonzero_seg3 == 0:
        pass
    else:
        pass
@@ -35,9 +35,9 @@ from radar_scene import Target, generate_doppler_frame
 DOPPLER_FFT_SIZE = 16     # Per sub-frame
 DOPPLER_TOTAL_BINS = 32   # Total output (2 sub-frames x 16)
-RANGE_BINS = 512
+RANGE_BINS = 64
 CHIRPS_PER_FRAME = 32
-TOTAL_SAMPLES = CHIRPS_PER_FRAME * RANGE_BINS  # 16384
+TOTAL_SAMPLES = CHIRPS_PER_FRAME * RANGE_BINS  # 2048
 # =============================================================================
@@ -30,7 +30,7 @@ from fpga_model import (
 )
-FFT_SIZE = 2048
+FFT_SIZE = 1024
 def load_hex_16bit(filepath):
@@ -143,13 +143,9 @@ def main():
        bb_q = load_hex_16bit(bb_q_path)
        ref_i = load_hex_16bit(ref_i_path)
        ref_q = load_hex_16bit(ref_q_path)
        # Zero-pad to FFT_SIZE if shorter (legacy 1024-entry files → 2048)
        for lst in [bb_i, bb_q, ref_i, ref_q]:
            while len(lst) < FFT_SIZE:
                lst.append(0)
        r = generate_case("chirp", bb_i, bb_q, ref_i, ref_q,
                          "Radar chirp: 2 targets (500m, 1500m) vs ref chirp",
-                          base_dir, write_inputs=True)
+                          base_dir)
        results.append(r)
    else:
        pass
@@ -5,8 +5,8 @@ gen_multiseg_golden.py
 Generate golden reference data for matched_filter_multi_segment co-simulation.
 Tests the overlap-save segmented convolution wrapper:
-  - Long chirp: 3072 samples (2 segments x 2048, with overlap)
+  - Long chirp: 3072 samples (4 segments x 1024, with 128-sample overlap)
-  - Short chirp: 50 samples zero-padded to 2048 (1 segment)
+  - Short chirp: 50 samples zero-padded to 1024 (1 segment)
 The matched_filter_processing_chain is already verified bit-perfect.
 This test validates that the multi_segment wrapper:
@@ -17,7 +17,7 @@ This test validates that the multi_segment wrapper:
 Strategy:
  - Generate known input data (identifiable per-segment patterns)
-  - Generate per-segment reference chirp data (2048 samples each)
+  - Generate per-segment reference chirp data (1024 samples each)
  - Run each segment through MatchedFilterChain independently in Python
  - Compare RTL multi-segment outputs against per-segment Python outputs
@@ -64,7 +64,7 @@ def generate_long_chirp_test():
      - buffer_write_ptr starts at 0 (from ST_IDLE reset)
      - Collects 896 samples into positions [0:895]
      - Positions [896:1023] remain zero (from initial block)
-      - Processes full 2048-sample buffer
+      - Processes full 1024-sample buffer
    For segment 1 (ST_NEXT_SEGMENT):
      - Copies input_buffer[SEGMENT_ADVANCE+i] to input_buffer[i] for i=0..127
@@ -89,7 +89,7 @@ def generate_long_chirp_test():
                          positions 0-895: input data
                          positions 896-1023: zeros from initial block
-    Processing chain sees: 2048 samples = [data[0:1919], zeros[1920:2047]]
+    Processing chain sees: 1024 samples = [data[0:895], zeros[896:1023]]
    OVERLAP-SAVE (ST_NEXT_SEGMENT):
      - Copies buffer[SEGMENT_ADVANCE+i] -> buffer[i] for i=0..OVERLAP-1
@@ -105,12 +105,12 @@ def generate_long_chirp_test():
        It was 896 after segment 0, then continues: 896+768 = 1664
    Actually I realize the overlap-save implementation in this RTL has an issue:
-    For segment 0, the buffer is only partially filled (1920 out of 2048),
+    For segment 0, the buffer is only partially filled (896 out of 1024),
    with zeros in positions 896-1023. The "overlap" that gets carried to
    segment 1 is those zeros, not actual signal data.
    A proper overlap-save would:
-    1. Fill the entire 2048-sample buffer for each segment
+    1. Fill the entire 1024-sample buffer for each segment
    2. The overlap region is the LAST 128 samples of the previous segment
    But this RTL only fills 896 samples per segment and relies on the
@@ -140,7 +140,7 @@ def generate_long_chirp_test():
    [768 new data samples at positions [128:895]] +
    [128 stale/zero samples at positions [896:1023]]
-    This is NOT standard overlap-save. It's a 2048-pt buffer but only
+    This is NOT standard overlap-save. It's a 1024-pt buffer but only
    896 positions are "active" for triggering, and positions 896-1023
    are never filled after init.
@@ -153,16 +153,22 @@ def generate_long_chirp_test():
    """
    # Parameters matching RTL
-    BUFFER_SIZE = 2048
+    BUFFER_SIZE = 1024
    OVERLAP_SAMPLES = 128
-    SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES  # 1920
+    SEGMENT_ADVANCE = BUFFER_SIZE - OVERLAP_SAMPLES  # 896
-    LONG_SEGMENTS = 2
+    LONG_SEGMENTS = 4
-    # Total input samples needed: seg0 needs 1920, seg1 needs 1792 (3712 total).
+    # Total input samples needed:
-    # chirp_complete triggers at chirp_samples_collected >= LONG_CHIRP_SAMPLES-1 (2999),
+    # Segment 0: 896 samples (ptr goes from 0 to 896)
-    # so the last segment may be truncated. We generate 3800 samples to be safe.
+    # Segment 1: 768 samples (ptr goes from 128 to 896)
    # Segment 2: 768 samples (ptr goes from 128 to 896)
    # Segment 3: 768 samples (ptr goes from 128 to 896)
    # Total: 896 + 3*768 = 896 + 2304 = 3200
    # But chirp_complete triggers at chirp_samples_collected >= LONG_CHIRP_SAMPLES-1 = 2999
    # So the last segment may be truncated.
    # Let's generate 3072 input samples (to be safe, more than 3000).
-    TOTAL_SAMPLES = 3800  # More than enough for 2 segments
+    TOTAL_SAMPLES = 3200  # More than enough for 4 segments
    # Generate input signal: identifiable pattern per segment
    # Use a tone at different frequencies for each expected segment region
@@ -178,7 +184,7 @@ def generate_long_chirp_test():
        input_q.append(saturate(val_q, 16))
    # Generate per-segment reference chirps (just use known patterns)
-    # Each segment gets a different reference (2048 samples each)
+    # Each segment gets a different reference (1024 samples each)
    ref_segs_i = []
    ref_segs_q = []
    for seg in range(LONG_SEGMENTS):
@@ -196,7 +202,7 @@ def generate_long_chirp_test():
        ref_segs_q.append(ref_q)
    # Now simulate the RTL's overlap-save algorithm in Python
-    mf_chain = MatchedFilterChain(fft_size=2048)
+    mf_chain = MatchedFilterChain(fft_size=1024)
    # Simulate the buffer exactly as RTL does it
    input_buffer_i = [0] * BUFFER_SIZE
@@ -304,7 +310,7 @@ def generate_long_chirp_test():
        f.write('segment,bin,golden_i,golden_q\n')
        for seg in range(LONG_SEGMENTS):
            out_re, out_im = segment_results[seg]
-            for b in range(2048):
+            for b in range(1024):
                f.write(f'{seg},{b},{out_re[b]},{out_im[b]}\n')
@@ -315,9 +321,9 @@ def generate_short_chirp_test():
    """
    Generate test data for single-segment short chirp.
-    Short chirp: 50 samples of data, zero-padded to 2048.
+    Short chirp: 50 samples of data, zero-padded to 1024.
    """
-    BUFFER_SIZE = 2048
+    BUFFER_SIZE = 1024
    SHORT_SAMPLES = 50
    # Generate 50-sample input
@@ -330,7 +336,7 @@ def generate_short_chirp_test():
        input_i.append(saturate(val_i, 16))
        input_q.append(saturate(val_q, 16))
-    # Zero-pad to 2048 (as RTL does in ST_ZERO_PAD)
+    # Zero-pad to 1024 (as RTL does in ST_ZERO_PAD)
    # Note: padding computed here for documentation; actual buffer uses buf_i/buf_q below
    _padded_i = list(input_i) + [0] * (BUFFER_SIZE - SHORT_SAMPLES)
    _padded_q = list(input_q) + [0] * (BUFFER_SIZE - SHORT_SAMPLES)
@@ -353,7 +359,7 @@ def generate_short_chirp_test():
            buf_i.append(0)
            buf_q.append(0)
-    # Reference chirp (2048 samples)
+    # Reference chirp (1024 samples)
    ref_i = []
    ref_q = []
    for n in range(BUFFER_SIZE):
@@ -364,7 +370,7 @@ def generate_short_chirp_test():
        ref_q.append(saturate(val_q, 16))
    # Process through MF chain
-    mf_chain = MatchedFilterChain(fft_size=2048)
+    mf_chain = MatchedFilterChain(fft_size=1024)
    out_re, out_im = mf_chain.process(buf_i, buf_q, ref_i, ref_q)
    # Write hex files
@@ -388,7 +394,7 @@ def generate_short_chirp_test():
    csv_path = os.path.join(out_dir, 'multiseg_short_golden.csv')
    with open(csv_path, 'w') as f:
        f.write('bin,golden_i,golden_q\n')
-        for b in range(2048):
+        for b in range(1024):
            f.write(f'{b},{out_re[b]},{out_im[b]}\n')
    return out_re, out_im
@@ -403,7 +409,7 @@ if __name__ == '__main__':
        # Find peak
        max_mag = 0
        peak_bin = 0
-        for b in range(2048):
+        for b in range(1024):
            mag = abs(out_re[b]) + abs(out_im[b])
            if mag > max_mag:
                max_mag = mag
@@ -412,7 +418,7 @@ if __name__ == '__main__':
    short_re, short_im = generate_short_chirp_test()
    max_mag = 0
    peak_bin = 0
-    for b in range(2048):
+    for b in range(1024):
        mag = abs(short_re[b]) + abs(short_im[b])
        if mag > max_mag:
            max_mag = mag
--- a/Show More
+++ b/Show More